JP2004047889A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

A memory transistor and a memory peripheral circuit are improved in commonality in structure and reduced in manufacturing cost.
A plurality of insulated gate transistors and memory transistors (formation regions (10c)) constituting a memory peripheral circuit are formed on the same semiconductor substrate (10). A plurality of stacked films in which a memory transistor is formed between the semiconductor substrate 10 and the gate electrode 25 and includes therein discrete charge storage means (charge traps) into which charges are injected when information is stored or erased. The semiconductor substrate 10 and the gate electrode 23 or 24 of at least the high withstand voltage transistor (formation region 10b) having the highest withstand voltage in the memory peripheral circuit among the plurality of insulated gate transistors having the charge storage film 14m The gate insulating film 14 formed therebetween has the same structure (three layers 14a to 14c) as the charge storage film 14m.
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device including a memory transistor having a plurality of stacked films including discrete charge storage means between a semiconductor substrate and a gate electrode, and a method of manufacturing the same.
[0002]
[Prior art]
Non-volatile memory transistors are roughly classified into a stand-alone type and a mixed type. In the stand-alone type, a nonvolatile memory transistor is used as a memory element of the dedicated memory IC. In the embedded type, a memory block and a logic circuit block are provided as a core of a system-on-chip, and a nonvolatile memory transistor is used as a memory element of the memory block.
In the embedded nonvolatile memory IC, the memory block includes a memory cell array in which a large number of memory cells each including at least one nonvolatile memory transistor are arranged in a matrix, and a memory peripheral circuit that controls the operation of the memory cell array. The logic circuit block has a logic circuit and a control circuit mainly including logic transistors that operate at high speed with a power supply voltage.
[0003]
The non-volatile memory transistor has an FG (Floating Gate) type in which the charge storage means is formed of a single conductive layer, and a MONOS (Metal-Oxide-Nitride-Oxide-) in which the charge storage means is formed of a charge trap which is discretely planarized. Semiconductor type and MNOS (Metal-Nitride-Oxide-Nitride-Oxide) type are known.
[0004]
In the FG memory transistor, a first potential barrier layer is formed over a surface region (a channel formation region) of a semiconductor substrate where a channel is formed, and a conductive film which is surrounded by an insulating film and is in an electrically floating state ( A floating gate FG), a second potential barrier layer, and a gate electrode (control gate) are stacked.
In the MONOS memory transistor, a plurality of stacked films between a channel formation region and a gate electrode have a so-called ONO (Oxide-Nitride-Oxide) structure. In the ONO film, bulk traps in the nitride film or interface traps near the interface between the nitride film and the oxide film function as discretized charge storage means, and charges are stored in these traps.
[0005]
Writing is performed by injecting charges from the substrate side into a plurality of stacked films (ONO films) including a charge trap or the floating gate FG. In the erasing, the accumulated charge is extracted to the substrate side, or a charge of the opposite polarity for canceling the accumulated charge is injected into the plurality of stacked films including the charge trap.
As a method of injecting electric charge, there is a method utilizing a tunnel phenomenon of electric charge (FN tunneling, direct tunneling) in the laminated film. In addition, a degree that can overcome the energy barrier height of the oxide film at the bottom of the ONO film or the oxide film (the first potential barrier layer) under the floating gate FG, such as a so-called CHE (Channel-Hot-Electron) implantation method. There is a method using hot carriers that have excited the charge energetically.
The charge injection method using the tunnel phenomenon has an advantage that a current value required for writing or erasing data is small, and damage to an oxide film (a tunnel oxide film) through which charges tunnel is small. On the other hand, the charge injection method using the tunnel phenomenon requires a high voltage, which is disadvantageous for lowering the voltage.
In the charge injection method using hot carriers, an applied voltage required for writing or erasing data can be lower than the applied voltage in the charge injection method using a tunnel phenomenon. In the charge injection method using hot carriers, the oxide film thickness of the lowermost layer of the ONO film or the oxide film thickness under the floating gate FG (thickness of the first potential barrier layer) can be made larger than that of the tunnel oxide film. There is an advantage. If the lowermost layer can be made thicker, the memory retention characteristics are greatly improved. On the other hand, it is known that when hot carriers, particularly hot holes, are injected into an oxide film, the oxide film is deteriorated. For this reason, the charge injection method using hot carriers is disadvantageous in repetition characteristics of data rewriting and erasing as compared with the charge injection method using a tunnel phenomenon.
[0006]
A transistor and a logic transistor in a memory peripheral circuit are insulated gate transistors in which charge does not move in a gate insulating film formed between a semiconductor substrate and a gate electrode. Generally, an insulated gate transistor is a MOS transistor in which a gate insulating film is formed of a single-layer silicon oxide film.
[0007]
Since the manufacturing process becomes complicated and the number of manufacturing steps increases in the manufacture of the nonvolatile memory device of the logic mixed type, how to increase the commonality between the manufacturing process of the logic circuit block and the manufacturing process of the memory block including the memory peripheral circuit is improved. Is important.
[0008]
[Problems to be solved by the invention]
When writing or erasing data in a conventional FG type or MONOS type nonvolatile memory transistor, a voltage higher than a voltage required in a logic circuit is required. This voltage has a different voltage value depending on the above-described charge injection method, but is higher than a power supply voltage given from the outside. In a memory peripheral circuit of a nonvolatile memory device, a booster circuit for generating a particularly high voltage and a circuit for applying the generated high voltage to a memory cell are required.
These circuits that handle high voltages include high-withstand-voltage transistors that have higher withstand voltages than logic transistors on the assumption that a power supply voltage is applied. The high breakdown voltage transistor is designed such that the gate oxide film is thicker than the logic transistor, and the impurity concentration distribution particularly on the drain side can reduce the electric field. For this reason, the photomask required for forming the logic embedded nonvolatile memory IC is two to four photomasks for forming the nonvolatile memory transistor in addition to the photomask required for forming the logic IC. Further, three to seven photomasks are added for forming a high breakdown voltage transistor. In addition to the cost increase due to the additional photomask, the number of steps increases almost in proportion to the number of photomasks. In general, the yield decreases as the number of steps increases. For this reason, the manufacturing cost of the embedded nonvolatile memory IC is high, and this is a major obstacle in spreading the embedded nonvolatile memory technology.
[0009]
A first object of the present invention is to provide a memory transistor having discrete charge storage means between a semiconductor substrate and a gate electrode, and a memory peripheral circuit for controlling the operation of the memory transistor. An object of the present invention is to provide a nonvolatile semiconductor memory device whose circuit has high commonality in structure.
A second object of the present invention is to increase the commonality in the manufacturing process of the nonvolatile memory device, reduce the number of photomasks required in the manufacturing, reduce the number of manufacturing processes, improve the yield, and thereby reduce the manufacturing cost. It is to reduce.
[0010]
[Means for Solving the Problems]
A non-volatile semiconductor memory device according to the present invention achieves the first object described above, and includes a non-volatile memory transistor and a memory peripheral that controls operation by applying a predetermined voltage to the memory transistor. A plurality of insulated gate transistors and the memory transistor constituting the memory peripheral circuit are formed on the same semiconductor substrate, and the memory transistor is formed between the semiconductor substrate and a gate electrode. A plurality of laminated films including therein a discretized charge storage means into which charges are injected when information is stored or erased, and at least one of the plurality of insulated gate transistors is provided in the memory peripheral circuit. The highest withstand voltage of the high withstand voltage transistor, the gate insulating film formed between the semiconductor substrate and the gate electrode, It has the same structure as the laminate film number.
[0011]
In this nonvolatile semiconductor memory device, the gate insulating film of the high withstand voltage transistor having the highest withstand voltage in the memory peripheral circuit is laminated between the semiconductor substrate and the gate electrode of the memory transistor, and the charge storage means is discretized inside. Has the same structure as a plurality of stacked films including.
When the memory peripheral circuit applies a voltage to the memory transistor, charges are injected into the plurality of stacked films according to the logic of the stored data. However, in the high breakdown voltage transistor in the memory peripheral circuit having the same structure, no charge is injected into the gate insulating film. Therefore, the threshold value of the memory transistor changes, but the threshold value of the high breakdown voltage transistor does not change.
[0012]
A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of: forming a plurality of stacked films including discrete charge storage means into which charges are injected when information is stored or erased; A non-volatile memory transistor between the memory transistor and a high withstand voltage transistor having the highest withstand voltage in a memory peripheral circuit for controlling the operation by applying a predetermined voltage to the memory transistor is formed on the same semiconductor substrate. A non-volatile semiconductor memory device manufacturing method, wherein the semiconductor substrate is formed in a region where the memory transistor is formed, and in a region where the memory peripheral circuit is formed, at least in a region where the high breakdown voltage transistor is formed. Forming a plurality of the stacked films including the charge storage means therein; and forming the insulated gate transistor on the plurality of the stacked films. Comprising a gate electrode of at least the high-voltage transistor of the gate electrodes of the capacitor, and forming simultaneously a gate electrode, the said memory transistor.
[0013]
In this manufacturing method, in forming a memory transistor and a high breakdown voltage transistor, a plurality of laminated films including discrete charge storage means are formed on a semiconductor substrate. A gate electrode of a high breakdown voltage transistor and a gate electrode of a memory transistor are simultaneously formed on the formed stacked films. Thus, in the memory transistor, a stacked body of a plurality of stacked films having a charge storage ability and a gate electrode is formed on the semiconductor substrate. At the same time, in the high-breakdown-voltage transistor, a gate insulating film having the same structure as a plurality of the laminated films on the same semiconductor substrate as the memory transistor but having the charge storage capability itself but not actually storing charges. And a gate electrode laminate is formed.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram of a logic-mixed nonvolatile memory device according to the first embodiment.
The illustrated nonvolatile memory device 1 includes a memory block 2 and a logic circuit block 3.
The memory block 2 includes a memory cell array 4, a column operation circuit 5, a row decoder 6, a control circuit 7, and a booster circuit 8. The column operation circuit 5 includes a column decoder, a sense amplifier, and a data latch circuit. The “memory peripheral circuit” of the present invention is constituted by the column operation circuit 5, the row decoder 6, the control circuit 7, and the booster circuit 8.
[0015]
The memory cell array 4 includes a plurality of nonvolatile memory cells arranged in a matrix. Here, the memory cell includes, for example, one memory transistor. The cross-sectional structure of the memory transistor will be described later.
Although not specifically illustrated, in the memory cell array 4, the gates of a plurality of memory transistors arranged in the same row are connected to the same word line, and the memory cells can be selected for each row by activating the word line. State. Write data is supplied to the plurality of memory transistors arranged in the same column by the same bit line, and stored data is read from the same bit line. A plurality of word lines are connected to the row decoder 6, and a plurality of bit lines are connected to a column decoder in the column operation circuit 5.
[0016]
The operation of the memory peripheral circuit is briefly described as follows.
The column decoder selects one or a plurality of bit lines according to a column address input from the control circuit 7. At the time of data reading, the selected bit line is connected to a sense amplifier in the column operation circuit 5. The sense amplifier is connected to the selected bit line to read data stored in the memory cell selected according to the column address. When writing data, the selected bit line is connected to a data latch in the column operation circuit 5. The data latch sets the voltage of the selected bit line using the write data latched in advance according to the column address, and writes the write data to the selected memory cell. At the time of verify reading (verify) for verifying written data, the sense amplifier operates in the same manner as at the time of reading, detects the potential of the selected bit line, and stores the data stored in the selected memory cell according to the detected potential. read out.
The row decoder 6 selects one or a plurality of word lines according to a row address input from the control circuit. The row decoder has a function of a word line driving circuit, and applies a predetermined voltage to a word line selected according to a row address at the time of data writing, reading, or erasing operation.
The control circuit 7 controls each configuration of the memory block 2 in accordance with a control signal input from the outside, and causes data write, read, and erase operations to be performed according to a predetermined sequence.
The booster circuit 8 generates a voltage higher than the input power supply voltage Vdd (hereinafter, referred to as a high voltage) under the control of the control circuit 7. The high voltage is supplied to the word line via the row decoder 6. The booster circuit 8 supplies a high voltage having a predetermined voltage value and polarity to the column operation circuit 5 or a well charge / discharge circuit (not shown) as necessary.
[0017]
The logic circuit block 3 is connected so that data can be exchanged with the control circuit 7 via a bus (not shown). The logic circuit block 3 has a function of a circuit for performing predetermined signal processing according to the use of the embedded nonvolatile memory device, or a microcomputer. The logic circuit block 3 has a large number of logic transistors that operate at high speed by the power supply voltage Vdd. Since the withstand voltage of the logic transistor is based on the use of the power supply voltage Vdd (for example, 2.5 V, 3.3 V, 5 V, etc.), it is sufficient to add a predetermined margin to the power supply voltage.
[0018]
The maximum value of the voltage value required for the operation of the nonvolatile memory transistor is generally 8 V or more, which is considerably higher than the power supply voltage Vdd. For this reason, a transistor (hereinafter referred to as a high breakdown voltage transistor) having a withstand voltage sufficiently higher than that of the logic transistor is provided in the booster circuit 8 and the word line drive circuit of the column decoder and the like. The high breakdown voltage transistor is required in the row decoder 6 or in a well charge / discharge circuit (not shown) as necessary.
[0019]
Assuming that the number of masks required to make a logic transistor is usually about 25, about 2 to 4 photomasks are generally added to make a MONOS memory transistor. If a high breakdown voltage transistor is required, three to seven more photomasks are added. In order to manufacture a high breakdown voltage transistor, (1) formation of a thick gate insulating film that can withstand a high voltage, and (2) source / drain junction where an electric field is hardly concentrated are required.
In the first embodiment, the number of photomasks is reduced by reducing the number of photomasks by reducing the thickness of the gate insulating film of (1) to have the same structure as the charge storage film (ONO film) used in the MONOS memory transistor.
[0020]
FIG. 2A is a cross-sectional view of a nonvolatile memory device in which a logic transistor, a high breakdown voltage transistor, and a memory transistor are formed over the same substrate. In FIG. 2A, P-type and N-type transistors are shown in the logic transistor formation region 10a and the high breakdown voltage transistor formation region 10b, respectively. One N-channel memory transistor is shown in the memory transistor formation region 10c.
In the logic transistor formation region 10a of the semiconductor substrate 10, a well having a P-type conductivity (hereinafter, referred to as a P-well) 16 and a well having an N-type conductivity (hereinafter, referred to as an N-well) 17 are formed. Similarly, a P well 18 and an N well 19 are formed in the high breakdown voltage transistor formation region 10b. P well 13 is formed in memory transistor formation region 10c. An element isolation insulating layer 11 is formed in a surface region in each well. In a well region between the element isolation insulating layers 11, a logic transistor, a high breakdown voltage transistor, or a memory transistor is formed.
[0021]
In the P well 16, an N-channel type logic transistor is formed. More specifically, a gate insulating film 20 made of silicon oxide is formed on P well 16, and a gate electrode 21 made of doped polycrystalline silicon doped with an N-type impurity is formed on gate insulating film 20. Have been. Source / drain regions 26 having LDD regions 26a having lower concentrations of N-type impurities than other regions are formed in the well surface regions on both sides of the gate electrode 21. On the side surface of the gate electrode 21, a side wall insulating layer 32 having a cross section of substantially a quarter circle is formed. A refractory metal silicide layer 33 is formed on the upper surface of the gate electrode 21 and the surface of the source / drain region 26.
In the N well 17, a P-channel type logic transistor is formed. The P-type logic transistor has the same structure as the above-described N-type logic transistor. However, the gate electrode 22, the source / drain region 27, and the LDD region 27a have conductivity types opposite to those of the gate electrode 21, the source / drain region 26, and the LDD region 26a.
[0022]
An N-channel type high withstand voltage transistor is formed in the P well 18. More specifically, a gate insulating film 14 made of a three-layered film is formed on P well 18, and a gate electrode made of doped polycrystalline silicon doped with an N-type impurity is formed on gate insulating film 14. 23 are formed. Source / drain regions 28 having LDD regions 28a having lower concentrations of N-type impurities than other regions are formed in the well surface regions on both sides of the gate electrode 23. The source / drain region 28 corresponds to a “first impurity region” in the present invention, and the LDD region 28a corresponds to a “second impurity region” in the present invention. On the side surface of the gate electrode 23, a side wall insulating layer 32 having a substantially quarter-circular cross section is formed. A refractory metal silicide layer 33 is formed on the upper surface of the gate electrode 23 and the surface of the source / drain region 28. In the N well 19, a P-channel type high breakdown voltage transistor is formed. The P-type high breakdown voltage transistor has a structure similar to that of the above-described N-type high breakdown voltage transistor. However, the gate electrode 24, the source / drain region 29, and the LDD region 29a have conductivity types opposite to those of the gate electrode 23, the source / drain region 28, and the LDD region 28a.
[0023]
In the P well 13, an N-channel type memory transistor is formed. More specifically, a charge storage film 14m composed of a three-layered film and having a charge storage capability is formed on the P well 13, and a doped polycrystal doped with an N-type impurity is formed on the charge storage film 14m. A memory gate electrode 25 made of silicon is formed.
A high-concentration channel region 31 having a P-type conductivity and a higher P-type impurity concentration than other well regions is formed in the well surface regions on both sides of the memory gate electrode 25. Source / drain regions 30 having N-type conductivity are formed in a well surface region between the memory gate electrode 25 and the element isolation insulating layer 11. The high concentration channel region 31 has a higher concentration than the other well surface regions. Therefore, a voltage drop in the boundary region between the source / drain region 30 and the high-concentration channel region 31 during operation increases. The high-concentration channel region 31 has a function of increasing the concentration of an electric field in a boundary region between the source / drain region 30 and the high-concentration channel region 31 during operation. On the side surface of the memory gate electrode 25, a side wall insulating layer 32 having a substantially 円 circular cross section is formed. A refractory metal silicide layer 33 is formed on the upper surface of the memory gate electrode 25 and the surface of the source / drain region 30.
[0024]
FIG. 2C is an enlarged cross-sectional view of a part of the memory transistor.
The charge storage film 14m of the memory transistor includes a first potential barrier layer 14a, a main charge storage layer 14b, and a second potential barrier layer 14c in order from the P well 13. When the charge storage film 14m has an ONO film structure, the first and second potential barrier layers 14a and 14c are made of silicon oxide or silicon oxynitride, and the main charge storage layer 14b is made of silicon nitride or silicon oxynitride. Become. The charge storage film 14m includes a charge trap (bulk trap) in the bulk of the main charge storage layer 14b and a deep charge trap (interface trap) formed near the interface between the main charge storage layer 14b and the second potential barrier layer 14c. It has a function of retaining electric charges. The well surface region immediately below the charge storage film 14m is a “channel formation region” in which a channel is formed during operation.
[0025]
FIG. 2B is an enlarged cross-sectional view of a part of the high withstand voltage transistor.
The gate insulating film 14 of the high breakdown voltage transistor has the same laminated film structure as the charge storage film 14m illustrated in FIG. That is, in the gate insulating film 14 of the high breakdown voltage transistor illustrated in FIG. 2B and the charge storage film 14m illustrated in FIG. 2C, the three layers 14a, 14b, and 14c have the same material and thickness. It is. However, no charge is injected into the gate insulating film 14 of the high breakdown voltage transistor. The reason will be described in the next operation.
[0026]
Although the method of writing, erasing, and reading data is arbitrary, the following method can be adopted in this example.
A hot carrier is used in at least one of data writing and erasing. In the case of a MONOS memory transistor, for example, channel hot electron injection is used for writing data. To erase data, hot holes are generated by avalanche breakdown triggered by an interband tunnel at the drain end, and the generated hot holes are injected. In order to efficiently generate a tunnel current between bands, it is necessary to apply a negative voltage to the gate.
In order to perform channel hot electron injection efficiently, a structure for concentrating a high electric field at the drain end is required. To this end, a channel impurity structure having a high channel impurity concentration, a channel impurity near the drain end called halo, and a locally high channel impurity concentration, and a steep source / drain impurity distribution structure are required. This is achieved by optimizing the impurity concentration distribution of the high-concentration channel region 31 in FIG.
[0027]
In the high breakdown voltage transistor, charge injection does not occur for the following reasons.
(1) A halo structure or a high-concentration channel region 31 does not exist in a channel region, and a source / drain structure adopts an LDD structure widely used to prevent hot carrier injection. As a result, the concentration of the electric field at the drain end is reduced, the hotning of the channel electrons is suppressed, and almost no electrons are injected into the gate insulating film 14.
(2) In a circuit operation handling a high voltage, a negative voltage is not normally applied to the gate. Therefore, there is no need to worry about hot holes being injected into the gate insulating film 14.
(3) The charge storage film 14m of the MONOS memory transistor using hot carriers is designed so as not to be written by the FN tunnel current. Therefore, in the gate insulating film 14 having the same laminated structure as the charge storage film 14m, charge injection does not easily occur simply by applying a high voltage in the film thickness direction. In order to prevent the FN tunnel current from flowing easily, it is desirable that the first potential barrier layer 14a has a thickness of 2 nm or more.
For the above reasons, it is possible to make the laminated structure of the charge storage film 14m of the memory transistor and the laminated structure of the gate insulating film 14 of the high breakdown voltage transistor the same.
[0028]
In the case of a MONOS memory transistor, when writing is performed again by switching the applied voltage between the drain and the source, charges can be locally injected into the drain and the source, respectively. Therefore, data can be stored at 2 bits / cell.
In data reading, data reading is performed by either a forward read method in which the magnitude relationship between the source and drain voltages is the same as that in data writing or a reverse read method in which the relationship is reversed in data writing. Do.
[0029]
FIGS. 3A to 7B are cross-sectional views of the nonvolatile memory device according to the first embodiment during manufacturing.
As shown in FIG. 3A, an element isolation insulating layer 11 made of silicon oxide is formed in a surface region of a semiconductor substrate 10 such as a P-type silicon wafer by, for example, an STI (shallow trench isolation) method. The element isolation insulating layer 11 is formed in each of the logic transistor formation region 10a, the high breakdown voltage transistor formation region 10b, and the memory transistor formation region 10c. In each region, the well region sandwiched between the element isolation insulating layers 11 becomes an active region of the transistor.
[0030]
A protective film 12 such as silicon oxide is formed on a semiconductor substrate 10. A resist opening in the memory transistor formation region 10c is formed, and P-type impurity ions are selectively implanted into the memory transistor formation region 10c using the resist as a mask. If necessary, ion implantation for adjusting the threshold voltage of the memory transistor is performed. The resist is removed and activation annealing is performed. After annealing, a resist opening in the high breakdown voltage transistor formation region 10b and the memory transistor formation region 10c is formed, and the silicon oxide is etched using the resist as a mask.
Thus, as shown in FIG. 3B, the protective film 12 is partially removed in the high breakdown voltage transistor formation region 10b and the memory transistor formation region 10c, and the P well 13 is formed in the memory transistor formation region 10c.
[0031]
As shown in FIG. 4A, a charge storage film (hereinafter, also referred to as an ONO film) 14 is formed in three regions 10a to 10c. The following method is suitable as a method for forming the ONO film 14.
As the first potential barrier layer 14a, the surface region of the semiconductor substrate 10 or the P well 13 is thermally oxidized by a thermal oxidation method to form a silicon oxide film. On the first potential barrier layer 14a, a silicon nitride film is deposited as a main charge storage layer 14b by a chemical vapor deposition (CVD) method. A silicon oxide film is formed as a second potential barrier layer 14c on the main charge storage layer 14b. In forming the silicon oxide film, the surface of the main charge storage layer 14b is thermally oxidized. During thermal oxidation, a deep charge trap is formed near the interface between the main charge storage layer 14b and the second potential barrier layer 14c. The second potential barrier layer 14c can also be formed by depositing an oxide film by a CVD method. As described above, when data writing using charge injection by channel hot electrons is premised, the thickness of the first potential barrier layer 14a is desirably 2 nm or more.
[0032]
A resist opening in the logic transistor formation region 10a is formed, and etching is performed using the resist as a mask. Thus, as shown in FIG. 4B, in the logic transistor formation region 10a, the ONO film 14 and the protective film 12 thereunder are selectively removed.
[0033]
After removing the resist, the exposed silicon surface is thermally oxidized to form a protective film 15 in the logic transistor formation region, which protects the substrate surface from contamination during ion implantation, as shown in FIG.
In this state, a P well 16 and an N well 17 in which a logic transistor is formed, and a P well 18 and an N well 19 in which a high breakdown voltage transistor is formed are sequentially formed. The formation order of the wells is arbitrary. In each well formation, a resist having an opening in a well formation portion is formed, and N-type or P-type impurity ions are implanted into the semiconductor substrate 10 under conditions (energy and dose) according to the specifications of the well to be formed. After that, the resist is removed. This resist formation, ion implantation, and resist removal are repeated four times while changing the opening of the resist and the ion conditions.
[0034]
A resist opening in the logic transistor formation region 10a is formed, and etching is performed using the resist as a mask. Thereby, as shown in FIG. 5B, the protective film 15 at the time of ion implantation is removed.
[0035]
The substrate surface from which the protective film 15 was removed at the time of ion implantation is again thermally oxidized to form a gate insulating film 20 of a logic transistor as shown in FIG.
[0036]
Polysilicon is deposited on the gate insulating film 20 and the ONO film 14 by a CVD method. If necessary, an N-type impurity and a P-type impurity are separately introduced into polysilicon by a selective ion implantation technique using a resist as a mask, and a work function difference of the polysilicon with respect to the substrate is changed at a necessary portion. Improve the conductivity of polysilicon.
A resist having a gate pattern is formed on polysilicon, and the polysilicon is etched using the resist as a mask. Thereby, as shown in FIG. 6B, the gate electrodes 21 and 22 of the logic transistor, the gate electrodes 23 and 24 of the high breakdown voltage transistor, and the memory gate electrode 25 are simultaneously formed. The memory gate electrode 25 may have a word line pattern.
[0037]
A selective ion implantation technique using a resist that opens one type of well as a mask is applied at most, depending on the type of well, for example, five times in FIG. 7A. A resist having an open well is formed, and a low concentration impurity portion (LDD region) of a source / drain region to be formed, a high concentration channel region 31 or a source / drain region 30 of a memory transistor. N-type or P-type impurity ions are implanted at a dose. At the time of ion implantation, the already formed gate electrodes 21 to 25 and the element isolation insulating layer 11 function as a self-aligned mask layer for preventing introduction of impurity ions. As a result, impurities are selectively introduced into the well surface portion between the gate electrode and the element isolation insulating layer. After that, the resist is removed. This resist formation, ion implantation, and resist removal are repeated at most five times while changing the opening of the resist and the ion conditions.
Thereby, as shown in FIG. 7A, LDD regions 26a and 27a are formed in logic transistor formation region 10a, and LDD regions 28a and 29a are formed in high breakdown voltage transistor formation region 10b. These LDD regions have a conductivity type opposite to that of the well. It is desirable to optimize the high breakdown voltage LDD regions 28a and 29a so as to suppress generation of hot carriers.
In the memory transistor formation region 10c, a high-concentration channel region 31 having the same conductivity type as the well and a higher concentration than the well and the source / drain region 30 are formed. The high-concentration channel region 31 is formed from the end of the source / drain region 30 to a position near the center of the channel. Such an impurity distribution can be achieved by utilizing the difference in the diffusion rate of the impurity or by adjusting the angle at the time of ion implantation.
[0038]
An insulating film, for example, a silicon oxide film is thickly deposited so as to completely cover the gate electrode, and is subjected to anisotropic etching. At this time, the insulating film is etched back, and as shown in FIG. 7B, a side wall insulating layer 32 having a substantially 略 circular cross section is formed on each side surface of the gate electrode.
A selective ion implantation technique using a resist opening one type of well as a mask is applied, for example, four times in FIG. 7B. For example, a resist having the same pattern as when the well is opened is formed, and N-type or P-type impurity ions are implanted under conditions (energy and dose) corresponding to the source / drain regions to be formed. At the time of ion implantation, the element isolation insulating layer 11, the gate electrodes 21 to 25, and the sidewall insulating layer 32 which have already been formed function as a self-aligned mask layer for preventing introduction of impurity ions. As a result, an impurity having a higher concentration than that of the LDD region is selectively introduced into the well surface portion between the sidewall insulating layer 32 and the element isolation insulating layer 11. After that, the resist is removed. This resist formation, ion implantation, and resist removal are repeated four times while changing the opening of the resist and the ion conditions. As a result, as shown in FIG. 7B, the source / drain regions 26 and 27 are formed in the logic transistor formation region 10a, and the source / drain regions 28 and 29 are formed in the high breakdown voltage transistor formation region 10b. In the memory transistor formation region 10c, ion implantation at the time of forming the source / drain region 28 may be added to the source / drain region 30.
In each of the above-described selective ion implantation processes, the gate insulating film 20, the high breakdown voltage transistor formation region 10b, or the ONO film of the memory transistor formation region 10c in the logic transistor formation region 10a while leaving the resist used for the ion implantation. 14 may be removed. Alternatively, the unnecessary portions may be removed at once by the ONO films 14 and 14m, and the unnecessary portions of the gate insulating film 20 may be removed separately. Unnecessary portions of the ONO films 14 and 14m and the gate insulating film 20 can be left to the end.
[0039]
Then, using a well-known salicide method, a high-melting-point metal silicide is collectively formed on the upper surfaces of the gate electrodes 21 to 25 and the surfaces of the source / drain regions 26 to 29, as shown in FIG. The formation of the structure is completed.
[0040]
FIGS. 8A to 13B are cross-sectional views of the non-volatile memory device according to the first embodiment in the process of being manufactured by a conventional method. In these figures, a configuration in which there is no change in the pattern and the material is indicated using the reference numerals shown in FIGS. 3 (A) to 7 (B).
8A, the element isolation insulating layer 11 is formed in the surface region of the semiconductor substrate 10 as in the step of FIG. A protective film 40 such as silicon oxide is formed on the semiconductor substrate 10. As in the step of FIG. 3B, a well is formed in the memory transistor formation region 10c by using a selective ion implantation technique using a resist, and ion implantation for adjusting the threshold voltage of the memory transistor is performed. The silicon oxide is etched using the resist used for the ion implantation as a mask. The resist is removed and activation annealing is performed.
As a result, as shown in FIG. 8B, the protective film 40 is partially removed in the memory transistor formation region 10c, and the P well 13 is formed in the region 10c.
[0041]
9A, an ONO film 14 is formed in three regions 10a to 10c by a method similar to the process of FIG. 4A.
A resist opening in the logic transistor formation region 10a and the high breakdown voltage transistor formation region 10b is formed, and etching is performed using the resist as a mask. Thus, as shown in FIG. 9B, in the logic transistor formation region 10a and the high breakdown voltage transistor formation region 10b, the ONO film 14 and the protective film 40 thereunder are selectively removed. The ONO film remaining in the memory transistor formation region 10c is denoted by reference numeral 14 '.
[0042]
After removing the resist, the exposed silicon surface is thermally oxidized to protect the substrate surface from contamination during ion implantation into the logic transistor formation region 10a and the high breakdown voltage transistor formation region 10b as shown in FIG. A film 41 is formed. In this state, a P well 16 and an N well 17 in which a logic transistor is formed, and a P well 18 and an N well 19 in which a high breakdown voltage transistor is formed are sequentially formed by using a method similar to that of FIG. I do.
A resist opening in the logic transistor formation region 10a and the high breakdown voltage transistor formation region 10b is formed, and etching is performed using the resist as a mask. Thus, as shown in FIG. 10B, the protective film 41 at the time of ion implantation is removed.
[0043]
After removing the resist, the surface of the substrate from which the protective film 41 at the time of ion implantation has been removed is thermally oxidized again to form a relatively thick gate insulating film (hereinafter referred to as a high withstand voltage gate insulating film) 42 made of silicon oxide for a high withstand voltage transistor. Form.
A resist opening in the logic transistor formation region 10a is formed on the high withstand voltage gate insulating film 42, and silicon oxide is etched using the resist as a mask. Thereby, as shown in FIG. 11A, the high withstand voltage gate insulating film 42 is selectively removed in the logic transistor formation region 10a. After removing the resist, as shown in FIG. 11B, the surface of the substrate from which the high-breakdown-voltage gate insulating film 42 has been removed is thinly thermally oxidized to form a relatively thin gate insulating film 20 made of silicon oxide for a logic transistor. .
[0044]
Gate electrodes 21 to 25 are formed by the same method as in the step of FIG. 6B (FIG. 12A), and LDD regions 26a to 29a and the high concentration channel region are formed by the same method as in the step of FIG. 31 are formed (FIG. 12B). However, the LDD regions 28b and 29b formed in the high breakdown voltage transistor forming region 10b of FIG. 12B are LDD regions in which the impurity concentration distribution is optimized in relation to the ONO film 14 in the process of FIG. 28a and 29a have different density profiles.
Thereafter, in FIGS. 13A and 13B, through the same steps as in FIGS. 7B and 2, the basic structure of the nonvolatile memory device is completed.
[0045]
In the case where the nonvolatile memory device according to the present embodiment is manufactured by a conventional method, in the process of FIG. 11A, a high breakdown voltage gate insulating film 42 is formed, and the high breakdown voltage gate insulating film 42 is partially formed in the logic transistor formation region 10a. A step of removing it is required.
On the other hand, in the manufacturing method according to the present embodiment, the ONO film 14 is used instead of the high-breakdown-voltage gate insulating film as shown in FIG. There are few steps, photolithography steps, and etching steps. Also, one photomask is required. The production cost can be reduced accordingly.
[0046]
[Second embodiment]
FIGS. 14A to 15B are cross-sectional views of the nonvolatile semiconductor memory device according to the second embodiment in the process of being manufactured. In these figures, configurations in which there is no change in the pattern and the material are indicated using the reference numerals shown in FIGS. 3A to 7B of the first embodiment.
The second embodiment is different from the first embodiment in that the well is formed in a step earlier than the well forming step in the manufacturing method of the first embodiment.
[0047]
As shown in FIG. 14A, an element isolation insulating layer 11 is formed in a surface region of a semiconductor substrate 10, and a protective film (not shown) is formed. Subsequently, a selective ion implantation technique using a resist is repeated at most five times while optimally changing ion implantation conditions for each well. Thus, a P well 13 for a memory, a P well 16 and an N well 17 for a logic transistor, and a P well 18 and an N well 19 for a high breakdown voltage transistor are sequentially formed. This forming method itself is the same as the method described in the description of FIG. 5A of the first embodiment.
[0048]
In FIG. 14B, a protective film 12 is formed on a semiconductor substrate 10. A resist opening in the high breakdown voltage transistor formation region 10b and the memory transistor formation region 10c is formed, and silicon oxide is etched using the resist as a mask. After that, the resist is removed.
[0049]
In FIG. 15A, an ONO film 14 is formed in three regions 10a to 10c by a method similar to the process of FIG. 4A.
[0050]
A resist opening in the logic transistor formation region 10a is formed, and etching is performed using the resist as a mask. Thus, as shown in FIG. 15B, the ONO film 14 and the protective film 12 thereunder are selectively removed in the logic transistor formation region 10a.
[0051]
After that, through the same steps as in the first embodiment, the basic configuration of the nonvolatile memory device is completed.
Specifically, a gate insulating film 20 of a logic transistor is formed (FIG. 6A), gate electrodes 21 to 25 made of doped polycrystalline silicon are formed (FIG. 6B), and LDD regions 26a to 29a are formed. Then, a high concentration channel region 31 and a source / drain region 30 are formed (FIG. 7A). 7B, the formation of the sidewall insulating layer 32, the partial removal of the gate insulating film 20 and the ONO film 14, and the formation of the source / drain regions 26 to 29 are sequentially performed. Finally, the refractory metal silicide layer 33 is formed to complete the same basic structure as in FIG.
[0052]
In the manufacturing method of the second embodiment, a well is formed first, and an ONO film is formed after the formation of the well. Therefore, the manufacturing method of the second embodiment has an advantage that the damage of the ion implantation at the time of forming the well does not remain in the ONO film as compared with the manufacturing method of the first embodiment. On the other hand, the manufacturing method of the first embodiment has an advantage that the channel concentration, which has a large effect on the characteristics of the transistor, is unlikely to fluctuate due to the thermal history because the well is formed in a later process.
[0053]
In the manufacturing method of the second embodiment, a thermal oxidation step, a photolithography step, and an etching step are performed as compared with a conventional manufacturing method in which a thick gate insulating film of a high breakdown voltage transistor is formed from a single-layer silicon film formed by thermal oxidation. There are few processes. Also, one photomask is required. The production cost can be reduced accordingly.
[0054]
【The invention's effect】
According to the non-volatile semiconductor memory device according to the present invention, it is possible to provide a non-volatile semiconductor memory device which has high commonality in structure between a memory transistor and a memory peripheral circuit and is suitable for logic embedding.
According to the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, in the manufacturing process of the nonvolatile memory device, the commonality between the manufacturing process of the memory transistor and the manufacturing process of the peripheral circuit is increased, and the number of photomasks required in the manufacturing is reduced. Reduction, reducing the number of manufacturing steps, and improving yield, resulting in reduced manufacturing costs.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embedded nonvolatile memory device according to a first embodiment.
FIG. 2A is a cross-sectional view of the nonvolatile memory device according to the first embodiment, in which a logic transistor, a high breakdown voltage transistor, and a memory transistor are formed on the same substrate. FIG. 2B is an enlarged cross-sectional view of a part of the high breakdown voltage transistor. (C) is an enlarged cross-sectional view of a part of the memory transistor.
FIGS. 3A and 3B are cross-sectional views showing up to the step of partially removing a protective film when forming a memory well in the manufacture of the nonvolatile memory device according to the first embodiment;
FIGS. 4A and 4B are cross-sectional views of a step following FIG. 3B, and show steps up to a step of removing an ONO film and a protective film in a logic transistor formation region.
FIGS. 5A and 5B are cross-sectional views of a step following FIG. 4B, and show steps up to a step of removing another protective film in a logic transistor formation region.
FIGS. 6A and 6B are cross-sectional views of a step following FIG. 5B, which show steps up to the step of forming a gate electrode.
FIGS. 7A and 7B are cross-sectional views of a step following FIG. 6B, showing steps up to the step of forming source / drain regions.
FIGS. 8A and 8B are cross-sectional views showing steps up to the step of partially removing a protective film when forming a memory well when the nonvolatile memory device according to the first embodiment is manufactured by a conventional method. FIG.
FIGS. 9A and 9B are cross-sectional views of a step following FIG. 8B, and show up to a step of removing an ONO film and a protective film in a formation region of a logic transistor and a high breakdown voltage transistor.
FIGS. 10A and 10B are cross-sectional views of a step following FIG. 9B, and show steps up to a step of removing another protective film in a formation region of a logic transistor and a high breakdown voltage transistor.
FIGS. 11A and 11B are cross-sectional views of a step following FIG. 10B, up to the step of forming a gate insulating film for a logic transistor.
FIGS. 12A and 12B are cross-sectional views of a step following FIG. 11B, showing steps up to the step of forming an LDD region and a high-concentration channel region;
13 (A) and 13 (B) are cross-sectional views of a step following FIG. 12 (B), up to a step of forming a refractory metal silicide layer.
FIGS. 14A and 14B are cross-sectional views showing up to a step of partially removing a protective film in the manufacture of the nonvolatile semiconductor memory device according to the second embodiment.
FIGS. 15A and 15B are cross-sectional views of a step following FIG. 14B, and show steps up to the step of removing the ONO film and the protective film in the logic transistor formation region.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Non-volatile memory device, 2 ... Memory block, 3 ... Logic circuit block, 4 ... Memory cell array, 5 ... Column operation circuit, 6 ... Row decoder, 7 ... Control circuit, 8 ... Boost circuit, 10 ... Semiconductor substrate, 10a ... Logic transistor formation region, 10b... High withstand voltage transistor formation region, 10c... Memory transistor formation region, 11... Element isolation insulating layer, 12... Protective film, 13. Accumulation layer, 14a: first potential barrier layer, 14c: second potential barrier layer, 14m: charge storage film, 15: protective film, 16: logic P well, 17: logic N well, 18: high breakdown voltage P well, 19: N well for high breakdown voltage, 20: Gate insulating film for logic, 21 to 24: Gate electrode, 25: Memory gate electrode, 26 to 30 Source and drain regions, 26A～29b ... LDD region, 31 ... high-concentration channel region, 32 ... side wall insulating layer, 33 ... refractory metal silicide layer, 40, 41 ... protective film, 42 ... high-voltage gate insulating film

Claims (6)

A non-volatile memory transistor;
A memory peripheral circuit that controls operation by applying a predetermined voltage to the memory transistor,
A plurality of insulated gate transistors and the memory transistor that constitute the memory peripheral circuit are formed on the same semiconductor substrate,
The memory transistor is formed between the semiconductor substrate and a gate electrode, and has a plurality of laminated films including therein discrete charge storage means into which charges are injected when storing or erasing information,
Of the plurality of insulated gate transistors, at least a gate insulating film formed between the semiconductor substrate and a gate electrode of the high withstand voltage transistor having the highest withstand voltage in the memory peripheral circuit has a plurality of stacked layers. A nonvolatile semiconductor memory device having the same structure as a film. The memory peripheral circuit applies a voltage to each of a drain and a gate on the basis of a source potential of the memory transistor, accelerates electrons in a formed channel to generate hot electrons, and generates the generated hot electrons on a drain side. 2. The non-volatile semiconductor memory device according to claim 1, wherein the charge is injected into the charge storage film. The film on the semiconductor substrate side of the plurality of stacked films in the memory transistor and the film on the semiconductor substrate side of the gate insulating film in the insulated gate transistor have a thickness of 2 nm or more. The nonvolatile semiconductor memory device according to claim 1. The high breakdown voltage transistor,
A channel formation region made of a first conductivity type semiconductor;
A first source / drain region made of a second conductivity type semiconductor in contact with one side of the channel formation region;
A second source / drain region made of a second conductivity type semiconductor in contact with the other side of the channel formation region;
At least one source / drain region of the first and second source / drain regions is:
A first impurity region;
The non-volatile semiconductor memory device according to claim 1, further comprising a second impurity region located between the first impurity region and the channel formation region and having a lower concentration than the first impurity region. A memory block,
And a logic circuit block,
The memory block has a memory cell array in which a plurality of memory cells including at least one of the memory transistors are arranged in a matrix.
2. The non-volatile semiconductor memory device according to claim 1, wherein the logic circuit block includes a logic transistor having a lower withstand voltage than the high withstand voltage transistor. A non-volatile memory transistor having a plurality of stacked films between a semiconductor substrate and a gate electrode including therein a discretized charge storage means into which charges are injected when storing or erasing information; A method for manufacturing a nonvolatile semiconductor memory device, wherein a high withstand voltage transistor having the highest withstand voltage in a memory peripheral circuit for controlling operation by applying a predetermined voltage to a memory transistor is formed on the same semiconductor substrate,
A plurality of the stacked films including the discretized charge storage means at least in the formation region of the memory transistor and the formation region of the high breakdown voltage transistor in the formation region of the memory peripheral circuit in the semiconductor substrate; Forming a;
Simultaneously forming at least a gate electrode of the high-breakdown-voltage transistor among the gate electrodes of the insulated gate transistor and a gate electrode of the memory transistor on a plurality of the stacked films;
A method for manufacturing a nonvolatile semiconductor memory device including:

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