JP2004040854A - Switching power source - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power source which can effectively suppress power loss occurring in the process of the switching of a main switch. <P>SOLUTION: A chopper type switching power source is equipped with a plurality of MOS transistors Q1 and Q2 connected in parallel with each other on a power path as a main switching element. A switching controller CNT switches MOS transistors Q1 and Q2 in roughly the same phase, and in the process of switching these MOS transistors q1 and Q2, it switches off the MOS transistor Q2 small in current capacity to delay it behind the MOS transistor Q1 large in current capacity. As a result, in the process of switching, this power source keeps the potential difference between the source and the drain of the MOS transistor zero, and suppresses the power loss in the switching element. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a switching power supply, and relates to a technique for reducing a loss at the time of switching.
[0002]
[Prior art]
Conventionally, switching power supplies have been widely used as DC-DC converters. FIG. 4 shows a basic configuration of the switching power supply. As shown in the figure, an input voltage Vi is applied to the input terminal T1 with reference to the ground terminal T3. The input terminal T1 is connected to a drain of an n-type MOS transistor Q as a main switching element, and a diode D is connected between the drain and the ground terminal T3. Reactor L is connected between the source of MOS transistor Q and output terminal T2, and capacitor C is connected between output terminal T2 and ground terminal T3. The switching control unit CTL outputs a voltage signal Vc for controlling the switching of the MOS transistor Q.
[0003]
According to this switching power supply, the switching control unit CTL adjusts the duty of the voltage signal Vc so that the output voltage Vo appearing at the output terminal T2 becomes a desired value with reference to the ground terminal T3. As a result, a square wave having the amplitude of the input voltage Vi appears on the source side of the MOS transistor Q, and this square wave is smoothed by the filter circuit including the reactor L and the capacitor C and output to the output terminal T2. At this time, the output voltage Vo appearing at the output terminal T2 is determined by the product of the duty of the voltage signal Vc and the input voltage Vi. The diode D is for releasing the energy stored in the reactor L to the load connected to the output terminal T2 when the MOS transistor T switches to the off state.
[0004]
[Problems to be solved by the invention]
By the way, according to the switching power supply according to the related art described above, when the current capacity of the MOS transistor Q as the main switching element is increased, power loss occurs when the MOS transistor Q switches from the on state to the off state. In addition, there is a problem that the efficiency as a DC-DC converter is reduced.
This problem will be described in detail with reference to the waveform diagram of FIG. Now, it is assumed that the voltage signal Vs is at the high level, the MOS transistor Q is turned on, and the switching current Is flows. In this state, the on-resistance of the MOS transistor Q is extremely small, so that the potential difference Vds between the source and the drain thereof is almost zero. At this time, the power loss in the MOS transistor T is represented by the product of the potential difference Vds and the switching current Ids. In this case, since the potential difference Vds is almost zero, the power loss in the MOS transistor Q is extremely small. It is in.
[0005]
From this state, when the voltage signal Vs becomes low level and the MOS transistor Q is turned off, the on-resistance of the MOS transistor Q becomes apparently infinite. As a result, the switching current Ids converges to zero. Here, when the current capacity of the MOS transistor Q is large, the gate capacity tends to increase due to its characteristics. Therefore, the response of the gate voltage of the MOS transistor Q to the voltage signal Vc becomes slow, and the on-resistance of the MOS transistor Q becomes an intermediate value during the switching process. As a result, as shown in FIG. 5, a potential difference Vs occurs in the switching period P, the product of the switching current Is and the potential difference Vs is not zero, and power loss occurs.
[0006]
The present invention has been made in view of the above problems, and has as its object to provide a switching power supply that can effectively suppress power loss that occurs in a switching process.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configurations.
That is, in the chopper type switching power supply, a plurality of MOS transistors (for example, corresponding to MOS transistors Q1 and Q2 to be described later) connected in parallel on a power path are used as main switching elements in the chopper type switching power supply. The switching control of the plurality of MOS transistors is performed in substantially the same phase, and in the process of switching the plurality of MOS transistors, the MOS transistor having a small current capacity is delayed with respect to the MOS transistor having a large current capacity. It is characterized in that it is configured to be controlled to the off state.
[0008]
According to a second aspect of the present invention, in the insulation type switching power supply, as a main switching element, a plurality of MOS transistors connected in parallel to each other on an exciting current path of a winding forming a primary side of an insulation transformer (for example, described later) Components corresponding to the MOS transistors Q21 and Q22 that perform switching control of the plurality of MOS transistors in substantially the same phase, and in the process of switching the plurality of MOS transistors, a current is supplied to a MOS transistor having a large current capacity. A small-capacity MOS transistor is controlled to be turned off by delaying.
[0009]
A third aspect of the present invention provides a semiconductor device, comprising: a plurality of MOS transistors (for example, constituent elements corresponding to MOS transistors Q1 and Q2 described later) connected in parallel between an input terminal side and an output terminal side; A filter circuit interposed between the MOS transistor and the output terminal, and a switching control of the plurality of MOS transistors in substantially the same phase, and a process of switching the plurality of MOS transistors to a MOS transistor having a large current capacity. On the other hand, a switching control unit (for example, a component corresponding to a switching control unit CNT described later) that controls a MOS transistor having a small current capacity to be turned off by delaying the MOS transistor is provided.
[0010]
According to a fourth aspect of the present invention, there are provided a plurality of MOS transistors which are interposed in parallel on a current path of a transformer having a primary side connected to an input terminal side and a winding forming the primary side of the transformer. (E.g., components corresponding to MOS transistors Q21 and Q22 described later), a rectifier circuit connected to the secondary side of the transformer, and rectifying power induced in the secondary-side winding; A filter circuit inserted between the output terminal and the plurality of MOS transistors, the switching control of the plurality of MOS transistors being performed in substantially the same phase; A switching control unit (for example, a switching control unit C to be described later) that controls a small MOS transistor to be turned off by delaying it. It includes a considerable component of) the T, the.
[0011]
To summarize the configuration of the invention described in claims 1 to 4, for example, a first MOS transistor having a large current capacity and a second MOS transistor having a small current capacity are connected in parallel on a power path. In the process of switching the first and second MOS transistors, the second MOS transistor is controlled to be off by delaying the first MOS transistor with respect to the first MOS transistor.
According to the configuration of the present invention, in the process of switching the MOS transistor from the ON state to the OFF state, the MOS transistor having the small current capacity keeps the ON state, and thereby the MOS transistor having the large current capacity is maintained. The terminal voltage (potential difference) of the transistor is reduced. Therefore, even if a current flows through a MOS transistor having a large current capacity, the current does not become apparent as a power loss, and the power loss generated in the switching process is effectively suppressed.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a configuration of a chopper type switching power supply according to Embodiment 1 of the present invention. In the figure, the same reference numerals are given to the elements common to the elements shown in FIG. As shown in the figure, the switching power supply according to the first embodiment has the configuration of the switching power supply according to the prior art shown in FIG. 4 and is connected in parallel with each other on a power path instead of MOS transistor Q. A plurality of MOS transistors Q1 and Q2 (main switching elements), and a switching control unit CNT for controlling switching of the plurality of MOS transistors Q1 and Q2 instead of the switching control unit CTL. Other configurations are the same as those shown in FIG.
[0013]
Further, the configuration will be specifically described. A DC power supply is connected between the input terminal T1 and the ground terminal T3, and an input voltage Vi is applied to the input terminal T1 with reference to the ground terminal T3. The drains of the n-type MOS transistors Q1 and Q2 connected in parallel to each other are commonly connected to the input terminal T1. In the first embodiment, the sum of the current capacities of the MOS transistors Q1 and Q2 is assumed to correspond to the current capacity of the MOS transistor Q according to the related art described above. The current capacity of the MOS transistor Q2 is sufficiently smaller than that of the MOS transistor Q1 as long as the potential difference Vs between the source and the drain can be kept small.
[0014]
A diode D is connected between each source of the MOS transistors Q1 and Q2 and the ground terminal T3. The anode of the diode D is connected to the ground terminal T3, and the cathode is connected to the source side of the MOS transistors Q1 and Q2. Reactor (inductor) L is connected between the sources of MOS transistors Q1 and Q2 and output terminal T2, and capacitor C is connected between output terminal T2 and ground terminal T3. These reactor L and capacitor C constitute a smoothing filter circuit. The switching control unit CTL outputs voltage signals Vc1 and Vc2 for controlling switching of the MOS transistors Q1 and Q2 according to the output voltage Vo.
[0015]
Next, the operation of the first embodiment will be described focusing on switching control of the MOS transistors Q1 and Q2.
First, a basic voltage conversion operation will be described. Under the control of the switching control unit CNT, the MOS transistors Q1 and Q2 are switching-controlled in substantially the same phase by the voltage signals Vc1 and Vc2. That is, when the MOS transistor Q1 is controlled to be on, the MOS transistor Q2 is also controlled to be on, and when the MOS transistor Q1 is controlled to be off, the MOS transistor Q2 is also controlled to be off. At this time, the switching control unit CNT adjusts each duty of the voltage signals Vc1 and Vc2 so that the output voltage Vo appearing at the output terminal T2 with respect to the ground terminal T3 becomes a desired output voltage.
[0016]
As a result, a square wave having a duty corresponding to the voltage signals Vc1 and Vc2 with the input voltage Vi as an amplitude appears on the source side of the MOS transistor T. This square wave is smoothed by a filter circuit including the reactor L and the capacitor C, and the output voltage Vo is output to the output terminal T2. Diode D releases the energy stored in reactor L to the load side connected between output terminal T2 and the ground terminal when MOS transistors Q1 and Q2 switch to the off state.
[0017]
Next, switching control of the MOS transistors Q1 and Q2 will be described in detail. When controlling the MOS transistors Q1 and Q2 from the off state to the on state, the voltage signals Vc1 and Vc2 transition from the low level to the high level at substantially the same timing, and the MOS transistors Q1 and Q2 are simultaneously turned on. As a result, the switching currents Ids1, Ids2 flow through the MOS transistors Q1, Q2. In this case, the gate voltages of the MOS transistors Q1 and Q2 rise in response to the voltage signals Vc1 and Vc2, and in this process, the on-resistances of the MOS transistors Q1 and Q2 become intermediate values, and the potential difference Vds between the source and the drain becomes apparent. Become However, since the initial values of the switching currents Ids1 and Ids2 are zero, the power loss generated in this case is extremely small.
[0018]
When the switching control unit CNT controls the MOS transistors Q1 and Q2 from the on state to the off state, as shown in FIG. 2, the voltage signal Vc1 changes from the high level to the low level at the time t1, and the voltage signal Vc1 , The voltage signal Vc2 is changed from a high level to a low level with a delay of a predetermined time tD. For this reason, in the switching period P in which the MOS transistor Q1 shifts from the ON state to the OFF state, the MOS transistor Q2 maintains the ON state in the fixed section P1 immediately after the switching in which the switching current Ids1 is still large, and the MOS transistor Q1 The potential difference Vds between the source and the drain is kept almost zero. Therefore, even if the on-resistance of the MOS transistor Q1 has an intermediate value during switching, power loss (amount given as a product of the switching current Ids1 and the potential difference Vds) in the MOS transistor Q1 is effectively suppressed.
[0019]
On the other hand, in the MOS transistor Q2, power loss occurs due to the switching current Ids2 and the potential difference Vds. However, since the current capacity of the MOS transistor Q2 is small, the switching response to the voltage signal Vc2 is fast due to its characteristics, and the period during which the on-resistance has an intermediate value is extremely short. Moreover, since the current capacity of the MOS transistor Q2 is small, the power loss itself in the MOS transistor Q2 is small in the first place. Therefore, the power loss generated in the MOS transistor Q2 during the switching process is small. Therefore, as a whole, the power loss generated in the MOS transistors Q1 and Q2 during the switching process can be effectively suppressed.
[0020]
As described above, according to the first embodiment, of the plurality of MOS transistors Q1 and Q2 forming the main switching element, the MOS transistor Q1 having a small current capacity is delayed by a certain time with respect to the MOS transistor Q1 having a large current capacity. Q2 is turned off. In other words, while the MOS transistor Q1 having the large current capacity is switched to the OFF state, the MOS transistor Q2 having the small current capacity is maintained in the ON state. Thus, the potential difference Vds between the source and the drain of the MOS transistor Q1 having a large current capacity is suppressed to a small value, and even if the switching current Ids1 flows, it does not appear as a power loss. Further, since it is only necessary to delay the MOS transistor having a small current capacity by a certain time with respect to the MOS transistor having a large current capacity, control of each MOS transistor is easy.
[0021]
(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described.
FIG. 3 shows a configuration of the insulated switching power supply according to the third embodiment. This switching power supply includes a plurality of MOS transistors Q21 and Q22 (main switching elements) connected in parallel on an exciting current path of a winding forming a primary side of an insulating transformer. The control is the same as in the first embodiment.
[0022]
The configuration will be specifically described. In the figure, TR is a transformer, the primary side of which is connected to the input terminals T11 and T12. Here, the input terminal T12 is a ground terminal, and an input voltage Vi based on the input terminal T12 is applied to the input terminal T11 from the outside. One end of the primary winding of the transformer TR is connected to the input terminal T11. MOS transistors Q21 and Q22 connected in parallel with each other are provided between the other end of the primary winding and the input terminal T12. It is connected. The MOS transistor Q21 corresponds to the above-described large current capacity MOS transistor Q1, and the MOS transistor Q22 corresponds to the above-described small current capacity MOS transistor Q2. On the other hand, a diode D1 is connected to the secondary side of the transformer TR as a rectifier circuit for rectifying the electric power induced in the secondary winding, and the diode D1 is connected between the rectifier circuit and the output terminals T21 and T22. A filter circuit including a capacitor C is interposed therebetween. The diode D2 is for discharging the energy stored in the secondary winding of the transformer TR to the load side. The switching control unit CNT is the same as in the first embodiment.
[0023]
According to the second embodiment, the exciting current of the primary winding of transformer TR is generated as the switching current of MOS transistors Q21 and Q22. In the process of controlling MOS transistor Q21 to be in the off state, MOS transistor Q22 is turned off. Maintain the ON state for a certain period of time, and maintain the potential difference Vds between its source and drain at almost zero. Therefore, even if the on-resistance of the MOS transistor Q21 having a large current capacity becomes an intermediate value and a switching current flows, the potential difference Vds between the source and the drain is almost zero, so that the power loss generated in the MOS transistor Q21 is suppressed. You. On the other hand, with respect to the MOS transistor Q22 having a small current capacity, since the switching speed is high and the current capacity is small in the first place, the power loss generated in the MOS transistor Q22 is small. Therefore, as a whole, power loss generated in the MOS transistors Q21 and Q22 during switching is effectively suppressed.
[0024]
Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and includes any design change or the like within a range not departing from the gist of the present invention. For example, in the first embodiment described above, the sum of the current capacities of the plurality of MOS transistors Q1 and Q2 corresponds to the current capacity of the MOS transistor Q according to the related art. However, the present invention is not limited to this. And a switching element having a small current capacity. In other words, a combination of a switching element having a large current capacity and a switching element having a fast switching speed may be used. An element having a large current capacity and a slow switching speed, and a switching element having a small current capacity and a fast switching speed may be used. May be combined. In the above-described embodiment, the potential difference Vds between the source and the drain of the MOS transistor having a large current capacity is made substantially zero by the MOS transistor having a small current capacity. However, the occurrence of power loss is substantially suppressed. It is sufficient that the potential difference Vds is as small as possible, and the potential difference Vds does not necessarily have to be zero.
[0025]
【The invention's effect】
As described above, according to the switching power supply of the present invention, the main switching element having a large current capacity and the main switching element having a small current capacity are connected in parallel to each other on the power path, and the main switching element having a large current capacity is connected. Since the main switching element having a small current capacity is controlled to be turned off by delaying the element with respect to the element, it is possible to effectively suppress the power loss generated during the switching process.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a chopper type switching power supply according to Embodiment 1 of the present invention.
FIG. 2 is a waveform chart for explaining an operation of the chopper type switching power supply according to Embodiment 1 of the present invention;
FIG. 3 is a circuit diagram showing a configuration of an insulated switching power supply according to Embodiment 2 of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a chopper type switching power supply according to the related art.
FIG. 5 is a waveform diagram for explaining a problem of a switching power supply according to the related art.
[Explanation of symbols]
T1: input terminal, T2: output terminal, T3: ground terminal, Q1, Q2, Q21, Q22: MOS transistor (main switching element), D, D1, D2: diode, L: reactor, C: capacitor, TR: transformer .

Claims (4)

In a chopper type switching power supply,
A plurality of MOS transistors connected in parallel to each other on a power path as a main switching element,
The switching control is performed on the plurality of MOS transistors in substantially the same phase, and in the process of switching the plurality of MOS transistors, the MOS transistor having a small current capacity is controlled to be turned off by delaying the MOS transistor having a small current capacity with respect to the MOS transistor having a large current capacity. A switching power supply characterized in that: In an isolated switching power supply,
A plurality of MOS transistors connected in parallel with each other on an exciting current path of a winding forming a primary side of an insulating transformer, as a main switching element;
The switching control is performed on the plurality of MOS transistors in substantially the same phase, and in the process of switching the plurality of MOS transistors, the MOS transistor having a small current capacity is controlled to be turned off by delaying the MOS transistor having a small current capacity with respect to the MOS transistor having a large current capacity. A switching power supply characterized in that: A plurality of MOS transistors mutually connected in parallel between the input terminal side and the output terminal side;
A filter circuit interposed between the plurality of MOS transistors and the output terminal;
A switching control unit that controls switching of the plurality of MOS transistors in substantially the same phase, and delays a MOS transistor with a small current capacity to an MOS transistor with a large current capacity in a process of switching the plurality of MOS transistors so as to control an OFF state; ,
Switching power supply with. A transformer whose primary side is connected to the input terminal side,
A plurality of MOS transistors interposed on a current path of a winding constituting a primary side of the transformer and connected in parallel with each other;
A rectifier circuit connected to the secondary side of the transformer and rectifying power induced in the secondary side winding;
A filter circuit interposed between the rectifier circuit and the output terminal,
A switching control unit that controls switching of the plurality of MOS transistors in substantially the same phase, and delays a MOS transistor with a small current capacity to an MOS transistor with a large current capacity in a process of switching the plurality of MOS transistors so as to control an OFF state; ,
Switching power supply with.

Images