JP2003511920A - Time-delay integration imaging with active pixel sensors - Google Patents

Abstract

(57) An image forming technique and an image forming apparatus (100) used to perform time delay integration based on an active pixel sensor (110). An on-chip integrator (120) with an active pixel sensor (110) for performing correlated double sampling and a switching capacitor bank based on the sum of signals.

Description

Detailed Description of the Invention

[0001] The present application is entitled "LOW POWER ACCURACY TIME-DELAYED-INTERGRATION IMA".
GER IMPLEMENTATION USING CMOS IMAGING AP PROACH ", October 5, 1999
It claims the benefits of a US provisional patent application filed on a date.

[0002]

[Origin of Invention]

Since the invention described in this application was made by research conducted under the contract with NASA, public law 96- when the contractor chooses to retain his rights.
517 (35 USC 202).

[0003]

[Prior Art and Problems to be Solved by the Invention]

The present application relates to an image forming apparatus and an image forming method, and more specifically, to an image forming apparatus and an image forming method based on a semiconductor sensor.

Image sensors are widely used in many applications to create images of various objects. Imaging circuits often include a two-dimensional array of photosensors designed to produce an output signal in response to photons. Each photosensor can be used to create part or all of one picture element (pixel) of the image. Individual photosensors can be scanned to read and process output signals for use in various image forming operations.

One class of solid-state image sensor is an active pixel sensor (A) formed on a semiconductor substrate.
PS) array. The APS is a photodetector having a detection circuit system in each pixel. Each active pixel comprises a detection element formed in the semiconductor substrate and capable of converting an optical signal into an electronic signal. When photons hit the surface of the photoactive area in each active pixel, free charge carriers are generated and collected. Once collected, the charge carriers are converted into electrical signals within each pixel. Therefore, the charge-coupled device (
Clearly different from CCD) or metal oxide semiconductor (MOS) diode arrays,
APS devices do not transfer charge from one pixel to another for reading. The APS can convert the photo charge into an electronic signal and then transfer the signal to a common conductor leading to an output node.

APS devices can be assembled in a manner compatible with complementary metal oxide semiconductor (CMOS) processes. Being compatible with the CMOS process, devices that control many signal processing functions and operations can be incorporated into a single APS chip at a relatively low cost. Also, CMOS circuitry can use a simple power supply to reduce power consumption. In addition, the active pixels of the APS device are capable of non-destructive readout, simplified digital interface and random access.

[0007]

[Means for Solving the Problems]

The present invention includes an image forming apparatus including a light detection array and an integrator array. The photodetection array comprises detection pixels arranged in rows and columns. Each pixel includes a photodetector element that generates an electric charge in response to an incident photon from an object and an in-pixel circuit (in-pixel c
ircuit) and. The integrating array has as many rows and columns of integrators as there are photodetector arrays. The integrator of each column is coupled to receive an electrical pixel signal from only one designated column of detection pixels of the photodetection array, and each detection pixel is sampled to provide a row of rows in the photodetection array. After being read by the number,
It is operable to generate a time-delayed integrated signal representative of the object.

[0008]

DETAILED DESCRIPTION OF THE INVENTION

Utilizing the time-delayed integration of the present invention, a series of active detection pixels in a CMOS APS array accumulate subsequent electrical output signals to produce a sum signal. The electrical signals that make up this summed signal are obtained by their respective pixels at different times lagging one another with a fixed length of delay time due to the scanning operation, so that the summed signal is a "time-delayed integration". ) ”Signal.

An example of an application of this time delay integration is an application of forming an image of a moving object with respect to an image forming apparatus. In a typical "snapshot" imaging operation, the detection pixels are controlled to collect photons from the object at a given exposure time. The signals output from different pixels are independent of each other and represent different pixels in the output image. When the object and the imager are relatively stationary, the exposure time can be increased to increase the signal / noise ratio by collecting more photons if the object is not bright enough. Alternatively, in a situation in which an image is formed while it is relatively stationary, a large number (several) of snapshots can be taken for one scene. The multiple snapshots or multiple frames can simply be summed to create a final image with an improved signal / noise ratio.

However, when the object moves with respect to the image forming apparatus, it is impossible to form an image with a long exposure time. This is because if the exposure time is too long, the image "smears" when it is captured, and photons from one location on the object are collected by two or more adjacent pixels along the direction of relative motion. Because. Smearing issues are encountered when simply summing multiple frames. This is because different frames were taken at different times and during that time the image of the object moved from one position to another on the detection array.

The time-delayed partial integration of the present invention is, in part, a modification of the multi-frame integration method described above to add the proper pixel signals from different detected pixels in different frames corresponding to the same image. Generate an integrated image. From another perspective, a large number of frames are also acquired in this case. However, the different frames are shifted relative to each other along the direction of relative movement, taking into account their movement, and then the shifted frames are summed. As a result, image formation smearing due to the relative motion is reduced and the final integrated image signal / noise ratio is at a desired value.

FIG. 1A illustrates a situation where an image of a ground scene is taken by the time delay integration method described above using an imaging array device on board an aircraft. Seven consecutive frames taken by the image forming apparatus are shown. Because the aircraft is in motion, its surface scenes project at different locations in the imaging array along the direction of motion. However, when the frame is spatially shifted by one pixel between any two consecutive frames, the detected pixels of different frames with the same ground scene are aligned and, as a result, summed, A proper integral image without smearing is generated.

FIG. 1B illustrates a representative example 100 of an APS image forming device having an on-chip time delay integrated circuit system of one embodiment. The APS image forming apparatus 100 includes an APS array 110 having APS detection pixels arranged in m columns and n rows and an analog integration array 120, both of which are assembled on a common substrate. In operation, the image forming device 100 is oriented such that the columns are substantially parallel to the direction of movement of the object to be imaged with respect to the image forming device 100. Integration array 1
20 is designed to perform the time delay integration and APS array 110.
(Interface) with.

The APS array 100 can be made with a suitable APS design. A
The detection pixels of the PS each include a photoactive device such as a photogate or a photodiode to collect photons and generate a charge in response to the collected photons. The charge is then transferred to an in-pixel circuit, where it converts the charge into a pixel electrical signal. In one embodiment, the intra-pixel circuit includes a separate diffusion region and a transfer gate disposed between the photoactive device and the diffusion region.
Is equipped with. The diffusion region receives the charge and then sends a corresponding electrical signal to the pixel amplifier for further processing.

The APS array 110 is formed of CMOS-compatible active pixel sensors incorporated on a semiconductor substrate. The integrator is also integrated with the APS array 110 on the same substrate by utilizing CMOS technology to perform the time delay integration. Thus, such a CMOS imager can combine the time delay integration mechanism with the various advantages of the CMOS APS technique and on-chip processing capabilities. Each APS pixel internally converts the photon-induced charge into an electrical signal, thus avoiding charge transfer from one pixel to another.

An example of an optical gate based APS is shown in Fossum et al. US Pat. No. 5,471,515.
No. This patent is incorporated herein by reference. One feature of this APS array is that it has a correlated double sampling mechanism.
hanism). Fossum discloses a readout circuit assembled on the sensor substrate but outside the APS sensor. In the readout circuit, the potential of the floating diffusion region at the end of each integration period is sampled using the signal sample holding circuit, and the total signal from the pixel is obtained. Another reset sample holding circuit is used to reset the floating diffusion region and then the potential of the floating diffusion region is sampled again to obtain the value of the reset potential. The differential circuit
It is coupled to both sample and hold circuits to produce an output indicative of the difference between the sum signal and the reset signal. This double sampling significantly reduces read noise, such as KTC noise. This double sampling is performed in the device 100 of the present invention in a different manner by using an integrating array 120.

The integration array 120 includes m × n analog integrators arranged in m columns and n rows. The integrating array 120 is connected to the APS array 110 in a column parallel arrangement in which one column of integrators is coupled to receive signals from only one column of APS detection pixels. Each integrator is designed so as to be able to perform n-step time-delayed integration from n APS detection pixels and n integrators in the same column by utilizing this column parallel arrangement configuration. As a result, n output signals from n different APS detection pixels in the same column, which are generated at different time points, are integrated to generate a one-pixel signal of an output image showing an image of one location of the object. . Cross-track coverage is provided by the m APS detection pixels in each row. The column parallel design allows signal processing in different columns to proceed concurrently in parallel.

Analog / digital conversion can also be performed by the APS image forming apparatus 100. An ADC array 130 of m ADCs is assembled on the same substrate in a column-parallel arrangement, such that each ADC is designated to transform a time-delayed signal from one column of the integrating array 120. . Alternatively, a single ADC may be used to transform the signals from the entire integrating array 120, or an ADC array of m · n ADSs may be used to convert all the m · n integrators. The output signal can be digitized in parallel.

Next, the circuit system and operation of the integration array 120 will be described in detail. In this column parallel arrangement, the signal level of the APS detection pixel in a given row can be applied to any one of the integrators in the column corresponding to that detection pixel. A row of different integrators stores pixel values at successive positions of the object, which are collected by different APS detection pixels and accumulated over n frame times. The frame time is defined as the time required to read the entire APS array 110. With this arrangement, the frame time is
It is also the integration time of each pixel and the readout time of one line of the image of the object at the final output.

When performing n stages of time-delayed integration, the APS array 110 is controlled to form multiple consecutive frames at different times, as shown in FIG. 1A. But,
The pixel signals for each frame are copied to the integrating array 120 by shifting one row at a time along the column direction. This is shown in FIG. 1A.

FIG. 1C shows the mapping of APS detection pixels in one column to the integrator in the same column in three consecutive frames. APS detection pixels and integrators in the same column have a one-to-one mapping relationship in any given frame. For a given integrator, the mapping changes between two consecutive frames. Especially the integration array 120 and the AP
The connection between the S arrays 110 is such that each successive APS detection pixel in a given column is
It is controlled to be connected to a specified integrator in successive frames. Therefore, this designated integrator produces one time-delayed integration signal for one pixel of the last output image. This scheme allows a given point on the object to be mapped to the selected integrator, thus reducing image forming smear due to relative motion.

Thus, the above mapping causes the signal from the pixel in a given row k to be added to the integrator contents of a given row j in the same column during a given frame time. Since the integrator integrates n times to produce a one line image of the object, the pixel values are sampled at a sampling rate as high as n times the frame rate to provide a one line image per frame. There must be. Thus, during a given frame time, a row of integrators has accumulated the signal from all n previous frames and is ready to read.

The integrating array 120 is also controlled to read the APS array 110 twice during each frame to correct the offset effect. After all the detected pixels of the APS array have been reset, the integrating array 120 samples each reset value for that pixel. Then, after the photo-evoked signal is dumped from the photo-detector and then converted to an electrical pixel signal, the integrating array 120 is activated by each second AP.
S signals are sampled to obtain each signal. Each integrator in the integration array 120 then operates to subtract the two values and hold the differential value. This completes one integration of one frame. This double sampling and differentiation is repeated for each frame. A typical implementation based on a switched capacitor design is described below.

The time delay integration image forming apparatus 100 requires the integration array 120 to have a high processing speed. For example, assuming the line scan speed is L, the integration and readout are n
In order to perform a time delay integration of stages, it is necessary to proceed at a speed of nxL.
Moreover, each integrator typically requires two clock cycles to complete a single integration, one clock cycle for reset and another clock cycle for storage. Also, each pixel requires multiple clock cycles to complete the sampling operation. Pixel actuation in one embodiment of a light gate-based APS array includes at least four clock cycles: pixel reset (RST), reset sampling (SHR), light gate dump (PG).
) And signal sampling (SHS). Therefore, a total of 6n clock cycles are required to complete the time delay integration for one line. If the line speed is L = 50 klines / sec and n is 32, the clock speed is about 10 MHz. The read noise characteristic is weakened at such high clock rates. Further, the column parallel design limits the physical size of each integrator in the array 120 to the size of the APS detection pixels (eg, about 10 micron pitch). This physical limitation makes it difficult to implement a low noise but fast integrator.

One feature of device 100 is the placement of a special integrating array 120 such that the signal processing of one pixel in one column temporarily overlaps the signal processing of an adjacent pixel. Such temporary pipeline operations in different rows within a column, in combination with the column parallel processing, reduce the above requirement for high clock rates while maintaining the overall operating speed of the image forming apparatus 100. be able to.

Another feature of device 100 is to reduce noise such as offsets and parasitic effects during signal processing. The correlated double sampling mechanism of APS array 110 significantly reduces noise from APS array 110. However, the time-delayed integration operation, and the presence of the integration array 130, introduces additional noise problems inherent in these integrators, such as offset and parasitic effects.

These and other issues are addressed in the design of integrating array 130. In particular,
Implement a specific switched capacitor integrator to reduce additional noise. Described below are a number of representative designs for integrating array 120.

FIG. 2A illustrates one embodiment of a differential switched capacitor integrator array 200 as a building block for each array of integrators in the integration array 120. FIG. 2B shows a timing diagram for operating an integrator 200 connected to a column of APS detection pixels by an optical gate design. The sequence of integrators 200 has n
Contains all integrators. Only a single differential operational amplifier 210 is used for all n integrators in that column. An operational amplifier 210 is connected to receive two different input signals, a first input signal from each pixel and a second input signal from a reference (reference), so that whenever the pixel is sampled the reference Levels are also sampled to ensure differential sampling and integration. 1
During the frame time, each pixel outputs a reset level and a signal level to the operational amplifier 210.
Is sampled twice to send to the first input at two different times. In particular,
Each input of the operational amplifier 210, that is, a noninverting input 211a.
And the inverting input 211b are two alternative sampling capacitors (C + s
1, C + s2 and C-s1, C-s2), and pipeline processing can be performed. A total of n pairs of integration capacitors (C-1 and C + 1, C-2 and C)
+2, ..., C-n and C + n) are coupled to the two differential outputs 212a and 212b to form an array of integrators for that column. Using switches 1 and 2,
The sampling capacitor has the APS array 110, the reference signal and the common potential Vc.
connected to m. Switches R1 and S1, R2 and S2, ..., Rn and Sn are used to properly couple the n pairs of integrating capacitors.

In operation, when a set of sampling capacitors (eg C + s1 and C−s1) is switched to sample the reset level from the pixel in row k, the corresponding pixel in the previous row (k−1) is Dump levels are added to the switched capacitor integrator. Thus, the desired high processing speed is achieved by simultaneously sampling one pixel and summing on adjacent pixels without the high clock speeds otherwise required.

Switched-capacitor integrators are used in a fully differential form to allow common-mode noise, including clock coupling, ground noise and charge-through.
-feed through) is excluded. However, the alternating use of the two sets of sampling capacitors prevents sampling of the input signal to the input of the operational amplifier. This hinders automatic offset correction. The bottom plate potential for each sampling capacitor is no longer the same potential in both the sample and integration phases. Instead, the potential of the bottom plate is
Transition from V _cm to V _cm ⁺ V _{off '} . Note that V _off is an offset induced by the input. In a typical time-delay integrated imaging environment, the signal level from individual pixels is typically small, even smaller than typical operational amplifier offsets. Therefore, it is desirable to achieve offset-free integration without sacrificing speed or power.

[0031]   The image forming apparatus 200 maintains a desired offset while maintaining high-speed pixel integration.
Partly designed to achieve revocation. The signal from the pixel is
After being dumped on the pixel, the reset potential is changed from the sense node potential (dump potential).
It is generated by subtracting. This will sample the reset potential of a given pixel.
Achieved by ringing, integrating, and then sampling and integrating the dump potential
. The timing diagram shown in Figure 2B shows that a high-speed operation will make all pixels the same.
Sometimes it is shown to be achieved by resetting. Then from a continuous line
The reset potential of each column capacitor (C1⁺And C1 ⁻ , C2⁺And C2⁻, ...) are continuously integrated. This is R1, R2 ... and
This is done by continuously pulsing Rn.

When all reset values are stored in the capacitors, photo-charges from all pixels are dumped onto their respective sense nodes simultaneously. Following this, the sense node potential (dump potential) is continuously integrated into the same set of capacitors. The offset charge accumulated during the sampling and integration of the reset potential switches S1, S2, ..., And Sn as shown in the figure to invert the electrode plate (plate) of the feedback capacitor and connect the feed capacitor. By doing so, the dump potential is sampled and erased during integration. As a result, the scheme achieves integration without offset.

FIG. 3A shows another embodiment 300 of a bank of differential switched capacitor integrators.
In that design, design 200 shown in FIG. 2A is improved by reducing parasitic capacitance effects. In a typical VLSI capacitor implementation, the bottom plate parasitic capacitance is sometimes significant, eg, about 25% pf of the total capacitance. Therefore, the reversal of the capacitor plate between the two phases causes a differential charging of the parasitic capacitance to different potentials determined by the signal level. Since continuous integration is performed in continuous pixels, the presence of voltage-dependent charges in the parasitic capacitance causes non-linearity of integration and (pixel-to-pixel)
-pixel) smear may occur. Therefore, it is desirable to reduce the effect of parasitic capacitance.

The design 300 shown in FIG. 3A can be used to achieve the above goals without introducing significant offsets or significantly slowing operating speed.
The technique involves reversing the polarities of both the sampling capacitor and the integrating capacitor. As a result, the parasitic capacitance connected to the operational amplifier input is due to either the feedback capacitor or the sampling capacitor, but not both. Therefore, the charge of the parasitic capacitance is compensated in every other phase. This allows most of the associated parasitic effects to be eliminated. An additional switch connected to V _cm is utilized to prevent pixel-to-pixel smearing. This makes it possible to charge the parasitic capacitance to V _cm and prevent signal-dependent charge injection from the parasitic capacitor, regardless of the output potential of the previous phase.

FIG. 3B shows a timing diagram when operating the switches of the device 300.

The operation of the device 300 can be understood from the simplified circuits shown in FIGS. 4A and 4B. Each integration cycle includes two phases: a first phase (R phase) that samples and integrates a reset level (V _m ) and a second phase (D phase) that samples and integrates a dump level (V _dn ). Is included. In case of R phase of nth cycle,
After sampling the reset signal, the charge storage before and after closing the switch is expressed by the following equation.

[0037]

[Equation 1]

In the above equation, V _cm is the common mode voltage,

[0039]

[Equation 2]

[0040]   Is the potential of the sampling capacitor after being short-circuited in the nth phase,

[0041]

[Equation 3]

Is an input-referred offset for a non-inverted (inverted) input
And

[0043]

[Equation 4]

Is the non-inverting (inverting) output for the nth cycle or R phase, and α
Is the ratio between the parasitic capacitance and the actual capacitance.

In the next phase, when the polarities of both the sampling capacitor and the feedback capacitor are reversed, a parasitic capacitance location swap occurs. The swap ensures that the total parasitic capacitance at the input of the operational amplifier remains the same. The charge conservation in the D phase is represented by the following formula.

[0046]

[Equation 5]

Therefore, after the D phase has passed, the feedback capacitor stores (stores,
The stored charge becomes the integrated value of all the previous n cycles, each cycle representing the signal value from successive pixels, and the effects of operational amplifier offset and parasitic capacitance are completely eliminated. At the end of the cycle, the output end of the capacitor is briefly connected to V _cm to remove the signal dependency. The output is represented by the following formula.

[0048]

[Equation 6]

The remaining offset is due to the reset phase of the integrator, in which case the input and output of the operational amplifier are connected to provide the initial level (V _o ⁺ and V _o ⁺ ).
The charge stored in the feedback capacitor is completely removed in this process. The offset can be easily removed by performing an integrator reset with one end of the feedback capacitor connected to the input of the operational amplifier and the other end connected to V _cm . This ensures that the offset is stored in the capacitor and is canceled exactly in the following phase. Each feed capacitor is connected to V _cm through one switch, anyway, so no more switches are needed.

FIG. 5A shows another design 500 as an alternative design to the design 300 shown in FIG. 3A. In this method, the position of the feedback capacitor is swapped every ½ cycle between the inverting and non-inverting side of the amplifier, as the timing diagram shown in FIG. 5B shows. Therefore, the offset charge accumulated in the R phase is
During the D phase, it is exactly compensated by an equal amount of charges of opposite polarity. The capacitors are arranged in such a way that their bottom plate (shown schematically curved) is always connected to the low impedance line and never to the input of the operational amplifier. This ensures that the parasitic capacitance does not introduce non-linearities or other errors. These capacitors are connected between the inverting input and the non-inverting output or between the non-inverting input and the inverting output. The circuit is
Reverse connection of the capacitors works equally well. This design is simple due to the small number of switches compared to the embodiment 300 shown in FIG. 3A,
And it is simple because the timing is simple.
Crosstalk is low as it is never switched from one side of the fully differential amplifier to the other.

The devices shown in FIGS. 3A and 5A still have a residual offset, even though the offset of the operational amplifier can be canceled during the summation operation. This residual offset is introduced in the reset phase of the integrator when the inputs and outputs of the operational amplifier are connected to provide the initial levels (V _o ⁺ and V _o ⁺ ). The charge stored in the feedback capacitor is completely removed by the above process. This offset can also be reduced by performing an integrator reset with one end of the feedback capacitor connected to the input of the operational amplifier and the other end connected to V _cm . This allows the offset to be stored in the capacitor (store, store
And is guaranteed to be canceled exactly in the next phase. Anyway, no more switches are needed since each feedback capacitor is connected to V _cm through one switch.

The differential operational amplifier 210 used in the above design to perform common mode correction is used to drive the capacitors in the integrator capacitor bank. Amplifier 210 is referred to as fully differential because it has both out + and out- outputs.

FIG. 6 shows one embodiment of amplifier 210. The two outputs move symmetrically from the common mode voltage as expressed by the following equation.

[0054]

[Equation 7]

The amplifier 210 is designed completely symmetrical to reject common mode noise. The design is based on a single stage telescopic cascade amplifier (single
le stage telescopic cascade amplifier).

The key to the amplifier 210 is the NFET M whose sources are connected together.
It is a differential pair formed by 1 and M2. The common source current is the load FE7 M3
And its gate is biased by a voltage bias N. The differential pair is also connected to a set of PFET load transistors M4 and M5, which are connected as a current mirror and biased by a voltage bias P. The voltage bias N determines the load current of M3. The sum of the currents in M1 and M2 must equal this fixed load current, but that current is divided between M1 and M2 based on the input voltages in + and in-. M
The current through 1 and M2 determines the current across the left or right branch of the circuit.
The impedances of M4 and M5 convert the branch current into the respective voltages out + and o.
Convert to ut- to create the function of an amplifier.

NFET transistors M6 and M7 and PFET transistors M0 and M9 are cascade transistors. These transistors hold the drain of each of the NFET differential pair and the PFET load transistor to a substantially constant voltage so that the FET current does not change as the output voltage swings. This increases the effective impedance of the FET and thus the gain increases correspondingly. PFE
The bias voltage for the T cascade is generated directly from the bias CasP. NFE
The voltage of the T cascade is biased by coupling M10 and M11 to the bias P (bi
asP).

The amplifier 210 has a common mode feedback circuit that maintains a fixed common mode voltage, that is, the feedback mechanism is V _common.
Hold _mode constant. The operational amplifier comprises two common mode feedback circuit blocks, each block connected to each output (out + and out−). One end of the primary capacitor of each block is connected to its respective output and the other ends of the capacitors are connected together. This common node averages the output voltage and provides the value of the actual common mode voltage in ac.
This common node, labeled "cmfb" in the schematic, is connected to the gate of transistor M12 and provides common mode feedback. When the actual common mode voltage drifts and increases, the gate voltage of M12 increases and the currents in both the right and left branches of the amplifier increase, so the common mode voltage decreases again ( back down). Conversely, if the actual common mode voltage drifts and drops, the current through M12 drops, causing the common mold voltage to back up again. In this way, the common mode voltage is stabilized.

D. c. At, the switched capacitor sets a fixed offset between the common mode voltage and the cmfb voltage at the gate of M12. This is done by cycling the switch voltages labeled phi_CMpull and phi_CMpush.

The phi_CMpull phase connects the flying capacitor to VcmO and to bias N, the bias on load FET M3. This causes the flying capacitor to be charged to these potential differences. The phi_CMpush phase “pushes” this voltage onto the primary capacitor.

Since the charge between capacitors is shared in a given phase, its coupling voltage divides the difference between the previous primary capacitor voltage and the desired push voltage when they are connected. . However, every cycle moves the coupling voltage closer to the push value, and after a few cycles the voltage is specifically set to this value.

It is considered that the integrating array 120 of the image forming apparatus 100 shown in FIG. 1 can be implemented by using a single-ended operational amplifier in order to reduce the physical size of the integrating array 210. To be The differential integrator requires common mode feedback in order to keep the fully differentiated operational amplifier in the biased state. Such feedback circuits occupy a considerable amount of chip area. 7A and 7B show one embodiment of a switched capacitor integrator 700 by using a single output operational amplifier 710. FIG. 7C shows a timing diagram of the operation of these switches. The integrator 700 may perform correlated double sampling to reduce the offset. In particular, the integrated difference between the reset level and the signal level (integrated d
Only the ifference is stored in the integrating capacitor.

A number of specific embodiments are disclosed herein. However, various modifications can be made without departing from the scope of the claims of the present application. Like reference symbols in the various drawings indicate like elements.

[Brief description of drawings]

FIG. 1A shows an example of a time delay integration.

FIG. 1B shows an embodiment of an active pixel detection device having a time delay integration circuit system.

FIG. 1C is a table showing the mapping of the detector array to the integrating array in three consecutive frames of the apparatus shown in FIG. 1B.

2A illustrates one implementation of a differential switched capacitor integrator as a building block of the integrating array shown in FIG.

FIG. 2B shows a timing diagram in operating the integrator shown in FIG. 2A.

FIG. 3A shows an embodiment of a switched capacitor integrator based on a fully differential amplifier.

FIG. 3B shows a timing diagram for operating the switches of a switched capacitor integrator based on a fully differential amplifier.

FIG. 4A shows an example of a switched capacitor integrator based on a fully differential amplifier.

FIG. 4B shows an example of a switched capacitor integrator based on a fully differential amplifier.

FIG. 5A shows an example of a switched capacitor integrator based on a fully differential amplifier.

FIG. 5B shows a timing diagram for operating the switches of a switched capacitor integrator based on a fully differential amplifier.

FIG. 6 illustrates one implementation of a fully differential amplifier.

FIG. 7A shows a switched capacitor integrator based on a single output amplifier.

FIG. 7B shows a switched capacitor integrator based on a single output amplifier.

7C shows a timing diagram for operating the switches of the device shown in FIGS. 7A and 7B. FIG.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW (72) Inventor Pain Bedabrata             United States California             91109 Pasadena Email code 300−             315 Oak Grove Drive 4800               Jet Propulsion Laboratory             ー California Institute               Of technology (72) Inventor Cunningham Thomas             United States California             91109 Pasadena Email code 300−             315 Oak Grove Drive 4800               Jet Propulsion Laboratory             ー California Institute               Of technology (72) Inventor Yang Gang             United States California             91109 Pasadena Email code 300−             315 Oak Grove Drive 4800               Jet Propulsion Laboratory             ー California Institute               Of technology (72) Inventor Ortiz Monico             United States California             91109 Pasadena Email code 300−             315 Oak Grove Drive 4800               Jet Propulsion Laboratory             ー California Institute               Of technology F-term (reference) 5C024 AX19 CX07 CX13 DX04 GX03                       GX18 GY38 HX02 HX03 HX13                       HX23 HX29 HX31

Claims (19)

[Claims] 1. A photodetection array comprising a plurality of detection pixels arranged in rows and columns, wherein each pixel produces a charge in response to a photon incident from an object, and the charge. A photodetection array having an intra-pixel circuit for converting it into an electric pixel signal representing the charge; and an integration comprising a plurality of integrators arranged in rows and columns equal to the rows and columns of the photodetection array, respectively. An image forming apparatus comprising: an array; an integrator in each row is coupled to receive an electrical pixel signal from a designated single row of detection pixels in the photodetection array, and An imaging device, wherein the detection pixels are operable to generate a time-delayed integrated signal representative of an object after being sampled and read a number of times equal to the number of rows in the photodetection array. 2. The apparatus of claim 1, wherein each integrator in the integrator array comprises a capacitor switched integrator. 3. The actuation of one integrator for a signal from one detection pixel is another actuation of an adjacent integrator for another signal from its corresponding adjacent detection pixel. The device of claim 2, wherein the device temporarily overlaps. 4. A single input terminal of the capacitor switched integrator has a first sampling capacitor storing a first signal from a first detection pixel and a second detection pixel from a second detection pixel adjacent to the first detection pixel. 3. The apparatus of claim 2 coupled to a second sampling capacitor that stores two signals, the first and second signals being emitted at different times. 5. The apparatus according to claim 2, wherein the capacitor switched integrator is a differential integrator having a first input terminal for receiving an electrical pixel signal and a second input terminal for receiving a reference signal. . 6. The capacitor switched integrator comprises a single output amplifier whose output is coupled to a circuit having a reset sampling capacitor, an integrating capacitor and a plurality of switches, wherein the switch comprises the reset sampling capacitor. 3. The device of claim 2, wherein the device is arranged in the circuit to connect the integration capacitor and store only the difference between the reset potential and the potential of the signal from the pixel to the integration capacitor. 7. The device of claim 1, wherein the in-pixel circuit comprises an amplifier. 8. The apparatus according to claim 1, wherein the photodetector element comprises a photogate or a photodiode. 9. The apparatus according to claim 1, wherein the detection pixels are reset at the same time. 10. The apparatus of claim 1, further comprising at least one ADC coupled to digitize the output from the integrating array. 11. The detection pixel is first sampled to produce a reset value, and then a second sampling is performed after the photo-evoked signal is generated to produce a signal value for each readout. The device according to. 12. A semiconductor substrate; comprising n rows and m columns of active pixel sensors assembled on a first region of the substrate and operable to generate electrical pixel signals in response to photons. A detector array; and an integrating array assembled on a second region of the substrate adjacent to the first region, the amplifiers electrically coupled to each of the m columns of active pixel sensors. An image forming apparatus comprising: an integrating array having; each amplifier connected to n pairs of capacitors, such that each pair of capacitors has:
Electrical pixel signals generated at different times from n different active pixel sensors in each column are accumulated to generate a total signal; an image forming device. 13. The amplifier according to claim 12, wherein each amplifier samples each detection pixel twice during each readout to obtain a differential pixel signal between the reset value and the photon evoked signal value of each detection pixel. The described device. 14. A capacitor according to claim 13, wherein each pair of capacitors is coupled to a respective amplifier in such a manner that one capacitor receives the reset value and the other capacitor receives the photo-induced signal value. The described device. 15. The apparatus of claim 14, wherein each amplifier is a differential amplifier having a first input coupled to a designated column of active pixel sensors and a second input coupled to a reference. 16. A method of forming an image of an object; using a linear detection array of pixels along a predetermined direction, the radiation from the object moving relative to the detection array along said direction. Converting the radiation-induced charge of each pixel of the array into an electrical pixel signal internally; connecting a linear integration array of integrators to a detection array to obtain a plurality of images of the object produced by the detection array. Of frames; then, when sampling different frames along a predetermined direction, the mapping is shifted from the detector array to the integrating array to correspond to different frames corresponding to a common image from positions on the object. Generating a sum signal that sums the pixel signals from different pixel positions in the method; 17. The method of claim 16, further comprising sampling each pixel in each frame twice to obtain a value of the difference between the reset level and the signal level of each pixel. 18. The method of claim 17, further comprising temporarily overlapping the reset level sampling of the first pixel and the signal level sampling of the second adjacent pixel. 19. The method of claim 16 wherein each integrator comprises a switched capacitor integrator.