JP2003338718A - Digital amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a digital amplifier which is free from producing shock sound, when performing gain adjustment. <P>SOLUTION: When a gain adjustment curve is stored in a gain adjustment curve table portion 54 of a gain adjustment portion 50, and gain is changed from a present gain value to a new gain value, an intermediate gain value calculation portion 55 calculates an intermediate gain value, based on gain curve characteristics in synchronism with a clock, sets to an intermediate gain value register and finally sets at the new gain value. The gain curve characteristics stored in the gain adjustment curve table portion 54 has a gentle curve, at the beginning and end of the gain value change, wherein an affection of gain value change is notable and a sharp curve in the middle of a gain adjustment period. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio digital amplifier, and more particularly to a digital amplifier having a gain adjusting function.

[0002]

2. Description of the Related Art Notebook computers and portable CDs
(Compact Disk) Player and DVD (Digital Versat)
Devices such as players and car audios that operate on batteries and have built-in speakers are becoming popular.
These devices are required to have not only sound quality but also miniaturization and low power consumption. From such a background, digital amplifiers are attracting attention. Among them, PWM (Pulse Width) used for audio preamplifiers
The Modulation type digital amplifier is capable of digitally processing all audio signals by configuring all the circuits from input to output with digital circuits. In the PWM method, the voltage amplitude of the sound information can be converted into a digital pulse width and the speaker can be directly driven, and there is no need for analog processing. Therefore, it is possible to realize a small amplifier with low power consumption and a small amount of heat generation.

[0003]

However, since all are digital processing, there is a problem that noise is generated when the amount of change is large when the gain is adjusted. That is, when the amount of change between the currently set gain value and the newly set gain value is large, the gain changes abruptly, so a shock noise may occur when the gain changes and speaker damage may occur. In particular, this phenomenon is due to the BTL driving the load with two outputs of positive polarity and negative polarity.
In the (Bridge-Tied Load) connection, large noise occurs when the output of the PWM output device changes from zero output to absolute zero output.

The present invention has been made in view of the above,
The purpose is to obtain a digital amplifier that does not generate a shock noise when adjusting the gain.

[0005]

In order to achieve the above object, a digital amplifier according to the present invention is a digital amplifier having a gain adjusting function, and a new gain value register section for holding a newly set gain value, and A gain adjusting unit that calculates one or more intermediate gain values between the new gain value held in the new gain value register unit and the currently set gain value, and an intermediate gain value calculated by the gain adjusting unit. And a gain setting unit that sets the gain of the input audio signal based on the above and outputs the output audio signal.

According to the present invention, when the output voice signal is changed from the currently set gain value to the new gain value with respect to the input voice signal, it is between the currently set gain value and the new gain value. One to a plurality of intermediate gain values are calculated, and the gain values are changed up to the new gain value while sequentially setting the intermediate gain values.

In the digital amplifier according to the next invention, in the above invention, the gain adjusting section has a gain adjusting curve table section for storing a gain adjusting curve, and a value stored in the gain adjusting curve table section. The currently set gain value and the difference between the newly set gain value are multiplied, the currently set gain value is added to the multiplication result, and the currently set gain value and the newly set gain value are newly set. An intermediate gain value calculation unit that calculates an intermediate gain value with respect to the gain value is provided, and the intermediate gain value is set according to a gain curve characteristic stored in the gain adjustment curve table unit.

According to the present invention, when the gain value is changed from the current gain value to the new gain value, the value of the gain adjustment curve stored in the gain adjustment curve table section and the currently set gain value are set. The intermediate gain value is calculated by multiplying the difference between the newly set gain value and the result, and adding the currently set gain value to the new gain value from the current gain setting value according to the gain adjustment curve. The gain value is sequentially changed up to the value.

In the digital amplifier according to the next invention, in the above invention, the gain adjustment data stored in the gain adjustment curve table section has a gentle curve at the beginning and the end of the gain adjustment period, Is characterized by having a gain curve characteristic having a steep curve.

According to the present invention, the gain adjustment data stored in the gain adjustment curve table section has a gentle curve at the beginning and end of the gain adjustment period and a steep curve at the middle of the gain adjustment period. There is.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a digital amplifier according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the digital amplifier of this embodiment. The digital amplifier according to the present embodiment includes a serial / parallel conversion unit 10, a gain setting unit 20, a delta sigma conversion unit 30, and a PWM output unit 4.
0, the gain adjusting unit 50, and the new gain value register unit 6
It has 0.

The serial / parallel conversion unit 10 includes a linear P
CM (Pulse Code Modulation) signals and DSD (Direct
Converts 1-bit audio signals such as Stream Digital signals into parallel data.

The gain setting section 20 multiplies the audio signal converted into parallel data by the serial / parallel conversion section 10 by the gain value set by the gain adjusting section 50 to set the gain of the audio signal.

The delta-sigma conversion unit 30 performs delta-sigma modulation on the audio signal for which the gain is set, and moves the quantization noise outside the audible band.

The PWM output section 40 performs PWM modulation on the audio signal obtained by moving the quantization noise outside the audible band in the delta-sigma conversion section 30.

The new gain value register section 60 holds the new gain setting value input from the outside.

The gain adjusting section 50 calculates an intermediate gain value for changing the current gain value to the gain value set in the new gain value register section 60.

FIG. 2 is a block diagram showing the configuration of the gain adjusting section 50. The gain adjusting unit 50 includes a current gain value register 51, a comparing unit 52, and an address calculating unit 53.
A gain adjustment curve table unit 54, an intermediate gain value calculation unit 55, and an intermediate gain value register 56.

The current gain value register 51 holds the currently set gain value and is reset when the gain value has been changed.

The comparison unit 52 uses the current gain value register 5
The gain value held in 1 is compared with the newly set gain value, the value of the current gain value register 51 is compared with the newly set gain value, and the difference between the two gain values is calculated. .

The address calculation unit 53 determines the initial address of the gain adjustment curve table unit 54 when the gain value is changed based on the result of the comparison unit 52, until the gain value is changed to the newly set gain value. The address of the gain adjustment curve table unit 54 is updated in synchronization with the clock.

The gain adjustment curve table section 54 has an RA
M (Random Access Memory) or ROM (Read Only)
Memory) and stores the value of the gain adjustment curve. Specifically, the time axis of the gain adjustment curve having the gain curve characteristic shown in FIG.
Divide evenly by the number of M or ROM addresses x, and time t
The gain value at ₁ is stored in the start address 00h, the gain value at time t ₂ is stored in the address 01h, and the gain values of the gain adjustment curve are sequentially stored from the start address to the final address up to the value at time t _x .

The gain adjustment curve shows the coefficient when changing from the currently set gain value to the newly set gain value, and the gain is always changed according to this gain adjustment curve. When decreasing the gain value, the gain value at the time t ₁ is followed by the gain value at the time t ₂ in the order up to the gain value at the time t _{x, and} when increasing the gain value, at the time t _x . The gain value is changed by tracing the gain value at time t ₁ , the gain value at time t _x−1 , and so on up to the gain value at time t ₁ .

The gain curve characteristic of the gain adjustment curve has a plurality of slopes. In the case of FIG. 3, with n different slopes from the slope (1) to the slope (n), the beginning and the end when the gain value changes are gentle slopes, and the intermediate level of the change is steep. .

The intermediate gain value calculation unit 55 calculates the difference between the value of the current gain value register 51 calculated by the comparison unit 52 and the newly set gain value and the gain adjustment curve output from the gain adjustment curve table unit 54. The value is multiplied and the gain value currently held in the gain value register 51 is added to the result to calculate an intermediate gain value.

The intermediate gain value register 56 holds the intermediate gain value until the next intermediate gain value is calculated.

Next, the operation of the digital amplifier of this embodiment will be described. The serial-parallel conversion unit 10 includes a linear PCM (Pulse Code Modulation) signal and a DSD (Dir
ectStream Digital) signal such as a 1-bit input audio signal is converted into parallel data and output to the gain setting unit 20. When the 1-bit input audio signal is converted into parallel data, the gain setting unit 20 multiplies the audio signal converted into parallel data by the gain value set by the gain adjusting unit 50 to obtain the gain of the audio signal. To decide. When the gain is determined, the gain setting unit 20 outputs the audio signal to the delta-sigma conversion unit 30. When the audio signal is input, the delta sigma conversion unit 30 performs delta sigma modulation on the audio signal for which the gain is set, and moves the quantization noise to outside the audible band. The PWM output unit 40 performs PWM modulation on the audio signal from which the quantization noise has been removed by the delta-sigma conversion unit 30 and outputs an output audio signal.

Here, it is assumed that a new gain value is set in the new gain value register section 60 in order to change the gain value of the output audio signal. When the new gain value is set in the new gain value register unit 60, the comparing unit 52 of the gain adjusting unit 50 compares the current gain value held in the current gain value register 51 with the input new gain value. And outputs the result to the address calculator 53. Also,
The comparison unit 52 calculates the difference between the current gain value held in the current gain value register 51 and the input new gain value, and outputs it to the intermediate gain value calculation unit 55.

The address calculation unit 53 of the gain adjustment curve table unit 54 is based on the comparison result of the current gain value held in the current gain value register 51 input from the comparison unit 52 and the new gain value input. Determine the initial address to read. When the comparison result of the comparison unit 52 shows that the current gain value is larger than the new gain value (when the gain value of the output audio signal is lowered), the start address (younger address) of the gain adjustment curve table unit 54 is set as the initial address. To do. Conversely, when the current address gain value is smaller than the new gain value (when increasing the gain value of the output audio signal), the final address of the gain adjustment curve table unit 54 is set as the initial address. Address calculator 53
Outputs the determined initial address to the gain adjustment curve table unit 54.

When an address is input from the address calculation unit 53, the gain adjustment curve table unit 54 reads the data of the input address and the intermediate gain value calculation unit 5
Output to 5.

When data is input from the gain adjustment curve table unit 54, the intermediate gain value calculation unit 55 outputs the difference between the current gain value and the new gain value input from the comparison unit 52 and the gain adjustment curve table unit 54. The input data is multiplied to calculate the gain change amount. When the gain change amount is calculated, the intermediate gain value calculation unit 55 adds the calculated gain change amount to the current gain value held in the current gain value register 51. This value is the intermediate gain value, and the intermediate gain value calculation unit 55 outputs the calculated intermediate gain value to the intermediate gain value register 56.

When the intermediate gain value is input from the intermediate gain value calculation section 55, the intermediate gain value register 56 holds the intermediate gain value and outputs it to the gain setting section 20.

The gain setting section 20 multiplies the audio signal converted into parallel data by the gain value set by the gain adjusting section 50 to determine the gain of the output audio signal. When the gain is determined, the gain setting unit 20 outputs the audio signal to the delta-sigma conversion unit 30. When the audio signal is input, the delta sigma conversion unit 30 performs delta sigma modulation on the audio signal for which the gain is set, moves the quantization noise to outside the audible band, and the PWM output unit 40
The delta-sigma conversion unit 30 performs PWM modulation on the audio signal from which the quantization noise has been removed, and outputs an output audio signal.

Address calculation section 53 of gain adjustment section 50
Is synchronized with the clock, the current address is incremented when the comparison result of the comparison unit 52 is larger than the new gain value, and when the current gain value is smaller than the new gain value, The address of the gain adjustment curve table unit 54 is updated by decrementing with the current address.

When the address of the gain adjustment curve table section 54 is updated, as described above, the gain adjustment curve table section 54 reads out the data indicated by the address,
The intermediate gain value calculation unit 55 calculates the intermediate gain value based on the data of the gain adjustment curve table unit 54, the difference between the current gain value and the new gain value, and the current gain value,
Output to the intermediate gain value register 56.

When the current gain value is larger than the new gain value, the above operation is performed up to the final address of the gain adjustment curve table section 54, and when the current gain value is smaller than the new gain value, the gain adjustment curve table is displayed. Part 5
The gain is changed from the current gain value to the new gain value by repeating up to the start address of 4. When the output audio signal is changed to the new gain value, the current gain value register 5
1 is changed to a new gain value.

As described above, in the present embodiment,
When the gain adjustment curve is stored in the gain adjustment curve table unit 54 of the gain adjustment unit 50 and the gain is changed from the current gain value to the new gain value, the intermediate gain value calculation unit 55 synchronizes the gain curve with the clock. An intermediate gain value is calculated based on the characteristics, set in the intermediate gain value register, and finally set as a new gain value. The gain curve characteristics stored in the gain adjustment curve table unit 54 are
It has a gentle curve at the beginning and end of the gain value change that is easily affected by the gain value change, and has a steep curve in the middle of the gain adjustment period. The gain can be adjusted in a short time without generating a shock noise.

[0039]

As described above, according to the present invention, when changing the output audio signal with respect to the input audio signal from the currently set gain value to the new gain value, the currently set gain value 1 to a plurality of intermediate gain values are calculated between the new gain value and the new gain value, and the gain value is changed up to the new gain value while sequentially setting the intermediate gain value, so no shock noise is generated. The gain can be adjusted.

According to the next invention, when the gain value is changed from the current gain value to the new gain value, the value of the gain adjustment curve stored in the gain adjustment curve table section and the gain value currently set. Is multiplied by the difference between the newly set gain value and the gain value currently set is added to the result to calculate the intermediate gain value, and the new gain value is calculated from the current gain setting value according to the gain adjustment curve Since the gain value is sequentially changed to the value of, the gain can be adjusted without generating a shock noise.

According to the next invention, the gain adjustment data stored in the gain adjustment curve table portion has a gentle curve at the beginning and end of the gain adjustment period and a steep curve at the middle of the gain adjustment period. Therefore, it is possible to adjust the gain in a shorter time than when the gain adjustment period is changed linearly and without generating a shock noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital amplifier according to the present embodiment.

FIG. 2 is a block diagram showing a configuration of a gain adjusting unit shown in FIG.

FIG. 3 is a diagram showing a gain curve characteristic of a gain adjustment curve stored in a gain adjustment curve table section shown in FIG.

[Explanation of symbols]

10 serial-parallel conversion unit, 20 gain setting unit,
30 delta-sigma conversion unit, 40 PWM output unit, 50
Gain adjuster, 51 current gain value register, 52
Comparing section, 53 address calculating section, 54 gain adjustment curve table section, 55 intermediate gain value calculating section, 56 intermediate gain value register, 60 new gain value register section.

Claims (3)

[Claims] 1. A digital amplifier having a gain adjusting function, a new gain value register section for holding a newly set gain value, a new gain value held in the new gain value register section, and a currently set gain value. Between 1 and a plurality of intermediate gain values, and a gain setting section that sets the gain of the input audio signal based on the intermediate gain value calculated by the gain adjusting section and outputs the output audio signal. A digital amplifier characterized by comprising: 2. The gain adjusting section, a gain adjusting curve table section for storing a gain adjusting curve, a value stored in the gain adjusting curve table section, a currently set gain value and a newly set value. Intermediate gain for multiplying the difference between gain values and adding the currently set gain value to the multiplication result to calculate an intermediate gain value between the currently set gain value and the newly set gain value The digital amplifier according to claim 1, further comprising: a value calculator, wherein the intermediate gain value is set according to a gain curve characteristic stored in the gain adjustment curve table unit. 3. The gain adjustment data stored in the gain adjustment curve table section has gain curve characteristics having a gentle curve at the beginning and end of the gain adjustment period and a steep curve at the middle of the gain adjustment period. The digital amplifier according to claim 2, further comprising: