JP2003332538A - Ferroelectric memory device and method of manufacturing the same - Google Patents
Ferroelectric memory device and method of manufacturing the sameInfo
- Publication number
- JP2003332538A JP2003332538A JP2002141814A JP2002141814A JP2003332538A JP 2003332538 A JP2003332538 A JP 2003332538A JP 2002141814 A JP2002141814 A JP 2002141814A JP 2002141814 A JP2002141814 A JP 2002141814A JP 2003332538 A JP2003332538 A JP 2003332538A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- film
- memory device
- ferroelectric film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
(57)【要約】
【課題】 製造が容易で、且つ情報の非破壊読み出しが
可能で、情報の再度の書き込みが必要なく、分極疲労や
メモリ保持劣化等の問題点も解消でき、メモリセルも小
さくできる強誘電体メモリ素子を提供する。
【解決手段】 ゲート電極と絶縁体との間に強誘電体膜
を配置し、前記強誘電体膜を用いてソース電極とドレイ
ン電極とを相互に接続した強誘電体メモリ素子とする。
また、基板の上に導電膜と絶縁膜とを形成した後、前記
絶縁膜の上に強誘電体膜と、ソース電極と、ドレイン電
極とを形成し、その後、前記強誘電体膜の上にゲート電
極を形成する強誘電体メモリ素子の製造方法とする。
PROBLEM TO BE SOLVED: To provide a non-destructive readout of information that is easy to manufacture, does not require rewriting of information, can solve problems such as polarization fatigue and memory retention deterioration, and can also use a memory cell. Provided is a ferroelectric memory element that can be reduced in size. SOLUTION: A ferroelectric memory element is provided in which a ferroelectric film is disposed between a gate electrode and an insulator, and a source electrode and a drain electrode are connected to each other using the ferroelectric film.
Further, after forming a conductive film and an insulating film on the substrate, a ferroelectric film, a source electrode, and a drain electrode are formed on the insulating film, and then, on the ferroelectric film. A method of manufacturing a ferroelectric memory element for forming a gate electrode.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、強誘電体膜をゲー
ト絶縁膜として用いた強誘電体メモリ素子及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device using a ferroelectric film as a gate insulating film and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】最近、強誘電体を用いた不揮発性メモリ
が注目を浴びている。強誘電体を用いた不揮発性メモリ
には、キャパシタ型とＭＦＳＦＥＴ（Metal-Ferroelect
ric-Semiconductor Field Effect Transistor）型との
２種類がある。2. Description of the Related Art Recently, a non-volatile memory using a ferroelectric has been attracting attention. Nonvolatile memories using ferroelectrics include capacitor type and MFSFET (Metal-Ferroelect)
There are two types: ric-Semiconductor Field Effect Transistor type.
【０００３】キャパシタ型は、強誘電体薄膜キャパシタ
にパルス電流を印加して分極反転電流の有無を検出し
て、情報の読み出しを行うものである。このキャパシタ
型では、情報を読み出す際に記憶されていた情報を破壊
してしまうので、再び情報を書き込む動作が必要であ
り、また読み出すごとに分極反転させることになり、分
極疲労等の問題もある。The capacitor type is one in which a pulse current is applied to a ferroelectric thin film capacitor to detect the presence / absence of a polarization reversal current to read information. This capacitor type destroys the stored information when reading the information, so that the operation of writing the information again is required, and the polarization is inverted every time the information is read, and there is a problem such as polarization fatigue. .
【０００４】一方、ＭＦＳＦＥＴ型は、通常のＭＯＳＦ
ＥＴ（Metal-Oxide-SemiconductorFET）のゲート絶縁膜
をシリコン酸化膜から強誘電体膜に置き換えたものであ
る。図２に従来のＭＦＳＦＥＴ型強誘電体メモリ素子の
断面図を示す。図２において、シリコン基板２０の表面
にソース領域２１とドレイン領域２２が形成され、ソー
ス領域２１の上にはソース電極２３が形成され、ドレイ
ン領域２２の上にはドレイン電極２４が形成されてい
る。また、ソース電極２３とドレイン電極２４との間の
シリコン基板２０の上には強誘電体膜２５が形成され、
その強誘電体膜２５の上にはゲート電極２６が形成され
ている。On the other hand, the MFSFET type is a normal MOSF.
The gate insulating film of ET (Metal-Oxide-Semiconductor FET) is replaced with a silicon oxide film by a ferroelectric film. FIG. 2 shows a cross-sectional view of a conventional MFSFET type ferroelectric memory device. In FIG. 2, a source region 21 and a drain region 22 are formed on the surface of a silicon substrate 20, a source electrode 23 is formed on the source region 21, and a drain electrode 24 is formed on the drain region 22. . Further, a ferroelectric film 25 is formed on the silicon substrate 20 between the source electrode 23 and the drain electrode 24,
A gate electrode 26 is formed on the ferroelectric film 25.
【０００５】このＭＦＳＦＥＴ型では、情報の書き込み
は、ゲート電極とシリコン基板との間に電圧を印加し
て、強誘電体膜の分極方向を定めることにより行い、情
報の読み出しは、強誘電体膜の分極の向きによってチャ
ネルの導通状態が変わるので、これを検出することによ
り非破壊で情報を読み出すものである。In the MFSFET type, information is written by applying a voltage between the gate electrode and the silicon substrate to determine the polarization direction of the ferroelectric film, and the information is read out from the ferroelectric film. Since the conduction state of the channel changes depending on the polarization direction of, the information is read out nondestructively by detecting this.
【０００６】[0006]
【発明が解決しようとする課題】このように、ＭＦＳＦ
ＥＴ型は、非破壊読み出しが可能で、キャパシタ型のよ
うに再び情報を書き込む動作が必要なく、分極疲労等の
問題点も解消できる。また、メモリセルもキャパシタ型
に比べて小さくでき、超高集積化半導体メモリとしても
注目される。[Problems to be Solved by the Invention]
The ET type allows non-destructive reading, does not require the operation of writing information again like the capacitor type, and can solve problems such as polarization fatigue. In addition, the memory cell can be made smaller than that of the capacitor type, and is attracting attention as an ultra-high integration semiconductor memory.
【０００７】しかし、ＭＦＳＦＥＴ型は、シリコン基板
の上に強誘電体膜を形成する必要があるが、シリコン基
板上に強誘電体膜を形成することは容易ではなく、強誘
電体膜を形成する際に下部のシリコン基板がダメージを
受けやすいという問題がある。また、シリコン基板と強
誘電体膜とが直に触れ合うため、シリコン基板表面での
トラップ準位などの制御ができずトランジスタの安定動
作上多くの問題がある。However, in the MFSFET type, it is necessary to form the ferroelectric film on the silicon substrate, but it is not easy to form the ferroelectric film on the silicon substrate, and the ferroelectric film is formed. At that time, there is a problem that the lower silicon substrate is easily damaged. Further, since the silicon substrate and the ferroelectric film are in direct contact with each other, the trap level on the surface of the silicon substrate cannot be controlled, and there are many problems in the stable operation of the transistor.
【０００８】上記ダメージを防ぐために強誘電体膜とシ
リコン基板の間に薄い絶縁膜を配置したＭＦＩＳＦＥＴ
も提案されているが、まだフラットバンドシフトやメモ
リ保持に問題がある。MFISFET in which a thin insulating film is arranged between the ferroelectric film and the silicon substrate in order to prevent the above damage.
Has been proposed, but there are still problems with flat band shift and memory retention.
【０００９】本発明は前記従来の問題を解決するために
なされたものであり、シリコン基板等の半導体基板を電
流路として用いない新規な構造の強誘電体メモリ素子を
提供することを目的とする。The present invention has been made to solve the above conventional problems, and an object of the present invention is to provide a ferroelectric memory device having a novel structure in which a semiconductor substrate such as a silicon substrate is not used as a current path. .
【００１０】[0010]
【課題を解決するための手段】前記目的を達成するた
め、本発明の強誘電体メモリ素子は、ゲート電極と絶縁
膜との間に強誘電体膜を配置し、前記強誘電体膜を用い
てソース電極とドレイン電極とを相互に接続したことを
特徴とする。In order to achieve the above object, a ferroelectric memory device of the present invention uses a ferroelectric film by disposing a ferroelectric film between a gate electrode and an insulating film. The source electrode and the drain electrode are connected to each other.
【００１１】本発明では、情報の読み出しは強誘電体膜
と絶縁膜との間に流れる界面電流を利用するため、強誘
電体膜を形成する際に下部の基板がダメージを受けて
も、メモリ素子の動作機能に影響は少ない。さらに、情
報の非破壊読み出しが可能で、情報の再度の書き込みが
必要なく、分極疲労やメモリ保持劣化等の問題点も解消
でき、メモリセルも小さくできるという従来のＭＦＳＦ
ＥＴ型強誘電体メモリの特徴をも維持することができ
る。In the present invention, the information is read out by utilizing the interface current flowing between the ferroelectric film and the insulating film. Therefore, even if the lower substrate is damaged when the ferroelectric film is formed, The operation function of the element is not affected. Furthermore, non-destructive reading of information is possible, rewriting of information is not necessary, problems such as polarization fatigue and deterioration of memory retention can be solved, and the memory cell can be made smaller.
The characteristics of the ET type ferroelectric memory can be maintained.
【００１２】また、本発明の強誘電体メモリ素子の製造
方法は、基板の上に導電膜と絶縁膜とを形成した後、前
記絶縁膜の上に強誘電体膜と、ソース電極と、ドレイン
電極とを形成し、その後、前記強誘電体膜の上にゲート
電極を形成することを特徴とする。According to the method of manufacturing a ferroelectric memory device of the present invention, after forming a conductive film and an insulating film on a substrate, the ferroelectric film, the source electrode and the drain are formed on the insulating film. An electrode is formed, and then a gate electrode is formed on the ferroelectric film.
【００１３】本発明では、基板の上に形成された絶縁膜
の上に強誘電体膜を設け、情報の読み出しは強誘電体膜
と絶縁膜との間に流れる界面電流を利用するため、強誘
電体膜を形成する際に下部の基板がダメージを受けて
も、メモリ素子の動作機能に影響は少ない。さらに、情
報の非破壊読み出しが可能で、情報の再度の書き込みが
必要なく、分極疲労やメモリ保持劣化等の問題点も解消
でき、メモリセルも小さくできるという従来のＭＦＳＦ
ＥＴ型強誘電体メモリの特徴をも維持することができ
る。In the present invention, the ferroelectric film is provided on the insulating film formed on the substrate, and the readout of information utilizes the interface current flowing between the ferroelectric film and the insulating film. Even if the lower substrate is damaged when forming the dielectric film, the operation function of the memory element is not significantly affected. Furthermore, non-destructive reading of information is possible, rewriting of information is not necessary, problems such as polarization fatigue and deterioration of memory retention can be solved, and the memory cell can be made smaller.
The characteristics of the ET type ferroelectric memory can be maintained.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面に基づき説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１５】（実施形態１）図１は、本発明の実施形態
１の強誘電体メモリ素子の断面図である。本発明の強誘
電体メモリ素子１０は、基板１１の上に導電膜１７と絶
縁膜１６とを備え、絶縁膜１６の上に強誘電体膜１２
と、ソース電極１３と、ドレイン電極１４とが配置さ
れ、強誘電体膜１２はソース電極１３とドレイン電極１
４との間に位置し、強誘電体膜１２の上にはゲート電極
１５が配置されている。即ち、ゲート電極１５と絶縁膜
１６との間に強誘電体膜１２を配置し、前記強誘電体膜
１２を用いてソース電極１３とドレイン電極１４とを相
互に接続している。(First Embodiment) FIG. 1 is a sectional view of a ferroelectric memory device according to a first embodiment of the present invention. The ferroelectric memory device 10 of the present invention includes a conductive film 17 and an insulating film 16 on a substrate 11, and a ferroelectric film 12 on the insulating film 16.
, The source electrode 13 and the drain electrode 14 are arranged, and the ferroelectric film 12 includes the source electrode 13 and the drain electrode 1.
4, the gate electrode 15 is arranged on the ferroelectric film 12. That is, the ferroelectric film 12 is placed between the gate electrode 15 and the insulating film 16, and the ferroelectric film 12 is used to connect the source electrode 13 and the drain electrode 14 to each other.
【００１６】本発明に用いる基板１１の材質としては特
に限定されないが、例えば、半導体基板としてはシリコ
ン等、絶縁体基板としては石英、ポリイミド、ガラス等
を用いることができ、この中で特にシリコンを用いた半
導体基板が高集積回路を実現できる点で好ましい。The material of the substrate 11 used in the present invention is not particularly limited. For example, silicon or the like can be used as the semiconductor substrate, and quartz, polyimide, glass, or the like can be used as the insulating substrate. Of these, silicon is particularly preferable. The semiconductor substrate used is preferable in that a highly integrated circuit can be realized.
【００１７】本発明に用いる導電膜１７の材質としては
特に限定されないが、例えば、Ｐｔ、Ａｌ、Ｉｒ、Ｉｒ
Ｏ2、ＳｒＲｕＯ3、ＲｕＯ4等を用いることができ、こ
の中で特にＰｔ、Ｉｒは、導電性、強誘電体膜の結晶性
向上の点で好ましい。The material of the conductive film 17 used in the present invention is not particularly limited, but for example, Pt, Al, Ir, Ir.
O 2 , SrRuO 3 , RuO 4 and the like can be used, and among these, Pt and Ir are particularly preferable in terms of conductivity and improvement of crystallinity of the ferroelectric film.
【００１８】本発明に用いる絶縁膜１６の材質としては
特に限定されないが、例えば、ＳｉＯ2、ＳｉＯxＮy、
ＰＧＳ（Phospho-Silicate-Glass）、ＢＰＳＧ（Boro-P
hospho-Silicate-Glass）等を用いることができ、この
中で特にＳｉＯ2は、高絶縁性、高被覆性の点で好まし
い。The material of the insulating film 16 used in the present invention is not particularly limited, but for example, SiO 2 , SiO x N y ,
PGS (Phospho-Silicate-Glass), BPSG (Boro-P
hospho-Silicate-Glass) or the like can be used. Among them, SiO 2 is particularly preferable in terms of high insulation and high coverage.
【００１９】本発明に用いる強誘電体膜１２の材質とし
ては、例えば、ＰｂＴｉＯ3、ＰＺＴ（Ｐｂ（ＺｒxＴｉ
1-x）Ｏ3）、ＰＬＺＴ（（ＰｂxＬａ1-x）（ＺｒyＴｉ
1-y）Ｏ3）、ＢａＴｉＯ3、ＬｉＮｂＯ3、ＳｒＴｉ
Ｏ3、ＳｒＢｉ2Ｔａ2Ｏ9、ＢａＭｇＦ4等を用いること
ができ、この中で特にＰＺＴは、残留分極量が大きく、
電流のオン（ＯＮ）／オフ（ＯＦＦ）比を大きくできる
点で好ましい。The material of the ferroelectric film 12 used in the present invention is, for example, PbTiO 3 , PZT (Pb (Zr x Ti
1-x ) O 3 ), PLZT ((Pb x La 1-x ) (Zr y Ti
1-y ) O 3 ), BaTiO 3 , LiNbO 3 , SrTi
O 3 , SrBi 2 Ta 2 O 9 , BaMgF 4 or the like can be used. Of these, PZT has a large remanent polarization amount,
It is preferable in that the on / off ratio of the current can be increased.
【００２０】また、本発明に用いるソース電極、ドレイ
ン電極、ゲート電極の材質としても特に限定されない
が、白金、金、銀、銅、アルミニウム等の金属が使用で
きる。The material of the source electrode, the drain electrode and the gate electrode used in the present invention is not particularly limited, but metals such as platinum, gold, silver, copper and aluminum can be used.
【００２１】次に、本発明の強誘電体メモリ素子の製造
方法を説明する。先ず、基板１１の上に導電膜１７と絶
縁膜１６とをスパッタリング等により形成する。さら
に、絶縁膜１６の上にソース電極１３とドレイン電極１
４とをスパッタリング等により形成する。その後、ソー
ス電極１３とドレイン電極１４との間に強誘電体膜１２
を成膜する。強誘電体膜１２の成膜方法は、スパッタリ
ング法、ＭＯＣＶＤ法、ゾルゲル法、レーザアブレーシ
ョン法等を用いることができるが、中でも特にＭＯＣＶ
Ｄ法が、表面平滑性及び量産性の点で好ましい。続い
て、強誘電体膜１２の上にゲート電極１５をスパッタリ
ング等により形成する。これにより、本発明の強誘電体
メモリ素子１０を得ることができる。Next, a method of manufacturing the ferroelectric memory device of the present invention will be described. First, the conductive film 17 and the insulating film 16 are formed on the substrate 11 by sputtering or the like. Further, the source electrode 13 and the drain electrode 1 are formed on the insulating film 16.
4 and 4 are formed by sputtering or the like. After that, the ferroelectric film 12 is formed between the source electrode 13 and the drain electrode 14.
To form a film. As a method for forming the ferroelectric film 12, a sputtering method, a MOCVD method, a sol-gel method, a laser ablation method or the like can be used, and among them, the MOCV is particularly preferable.
Method D is preferable in terms of surface smoothness and mass productivity. Then, the gate electrode 15 is formed on the ferroelectric film 12 by sputtering or the like. Thereby, the ferroelectric memory device 10 of the present invention can be obtained.
【００２２】ここで、本発明の強誘電体メモリ素子の動
作について説明する。先ず、情報の書き込みは、ゲート
電極１５と導電膜１７との間に正又は負の電圧を印加し
て、強誘電体膜１２の分極方向を定めることにより行
う。The operation of the ferroelectric memory device of the present invention will be described below. First, writing of information is performed by applying a positive or negative voltage between the gate electrode 15 and the conductive film 17 to determine the polarization direction of the ferroelectric film 12.
【００２３】次に、情報の読み出しは、強誘電体膜１２
の分極の向きによってチャネルの導通状態が変わるの
で、これを検出することにより非破壊で情報を読み出す
ことができる。即ち、強誘電体膜１２が分極されたとき
（情報が入力されたとき）、強誘電体膜１２と絶縁膜１
６との界面には電子又は正孔の自由電荷が発生する。そ
の自由電荷は強誘電体膜１２の分極の向きにより大きく
変化する。分極が上を向いているときは、強誘電体膜１
２と絶縁膜１６との界面には電子は少ないので、チャネ
ルの電気伝導度は小さくなる。逆に、分極が下を向いて
いるときは、強誘電体膜１２と絶縁膜１６との界面には
電子は多いので、チャネルの電気伝導度は大きくなり、
絶縁膜１６と強誘電体膜１２との間に界面電流が流れ
る。このように、この界面電流の有無を検出することに
より情報を読み出すことができる。Next, information is read out from the ferroelectric film 12
Since the conduction state of the channel changes depending on the polarization direction of, the information can be read out nondestructively by detecting this. That is, when the ferroelectric film 12 is polarized (when information is input), the ferroelectric film 12 and the insulating film 1
Free charges of electrons or holes are generated at the interface with 6. The free charge largely changes depending on the polarization direction of the ferroelectric film 12. When the polarization is upward, the ferroelectric film 1
Since there are few electrons at the interface between 2 and the insulating film 16, the electrical conductivity of the channel becomes small. On the contrary, when the polarization is downward, there are many electrons at the interface between the ferroelectric film 12 and the insulating film 16, so that the electric conductivity of the channel increases,
An interface current flows between the insulating film 16 and the ferroelectric film 12. Thus, information can be read by detecting the presence or absence of this interface current.
【００２４】（実施形態２）図３は、本発明の実施形態
２の強誘電体メモリ素子の断面図である。図３に示すよ
うに、Ｓｉからなる基板３１の上にＳｉＯ2からなる絶
縁膜３９、Ｔｉからなる膜３８、Ｐｔからなる導電膜
（ゲート電極）３５、ＰＺＴからなる強誘電体膜３２を
ＭＯＣＶＤ法で積層する。続いて、強誘電体膜３２の上
にＰｔからなるソース電極３３と、Ｐｔからなるドレイ
ン電極３４をスパッタリングにより形成する。さらに、
ソース電極３３とドレイン電極３４との上及びその間に
ＺｒＯ2からなる絶縁膜３６をスパッタリングにより形
成して、パターニングする。最後に、絶縁膜３６の上に
Ａｕからなる導電膜（電極）３７をスパッタリングによ
り形成する。以上により、本発明の強誘電体メモリ素子
３０が完成する。(Second Embodiment) FIG. 3 is a sectional view of a ferroelectric memory device according to a second embodiment of the present invention. As shown in FIG. 3, an insulating film 39 made of SiO 2 , a film 38 made of Ti, a conductive film (gate electrode) 35 made of Pt, and a ferroelectric film 32 made of PZT are formed on the substrate 31 made of Si by MOCVD. Stack by method. Subsequently, a source electrode 33 made of Pt and a drain electrode 34 made of Pt are formed on the ferroelectric film 32 by sputtering. further,
An insulating film 36 made of ZrO 2 is formed by sputtering on and between the source electrode 33 and the drain electrode 34 and patterned. Finally, a conductive film (electrode) 37 made of Au is formed on the insulating film 36 by sputtering. As described above, the ferroelectric memory device 30 of the present invention is completed.
【００２５】図４は、本実施形態の強誘電体メモリ素子
のゲート電圧（ＶG）を変化させた場合のドレイン電流
（ＩD）の変化を示した図である。図４から明らかなよ
うに、１つのゲート電圧（ＶG）に対して、２つのドレ
イン電流（ＩD）を示すことが分かる。これが強誘電体
膜に正又は負の電圧を印加した履歴によって異なるメモ
リ効果であり、これを利用してメモリ素子として機能す
る。FIG. 4 is a view showing a change in drain current (I D) in the case where the gate voltage of the ferroelectric memory device of this embodiment the (V G) was varied. As apparent from FIG. 4, for one of the gate voltage (V G), it is seen that the two drain current (I D). This is a memory effect that varies depending on the history of applying a positive or negative voltage to the ferroelectric film, and it is utilized to function as a memory element.
【００２６】[0026]
【発明の効果】以上説明したように、本発明では、絶縁
体基板の上に強誘電体膜を設け、情報の読み出しは強誘
電体膜と絶縁体基板との間に流れる界面電流を利用する
ため、強誘電体膜を形成する際に下部の絶縁体基板がダ
メージを受けても問題はない。さらに、情報の非破壊読
み出しが可能で、情報の再度の書き込みが必要なく、分
極疲労やメモリ保持劣化等の問題点も解消でき、メモリ
セルも小さくできるという従来のＭＦＳＦＥＴ型強誘電
体メモリの特徴をも維持することができる。As described above, according to the present invention, the ferroelectric film is provided on the insulating substrate, and the reading of information utilizes the interface current flowing between the ferroelectric film and the insulating substrate. Therefore, there is no problem even if the lower insulating substrate is damaged when forming the ferroelectric film. Further, the characteristic of the conventional MFSFET type ferroelectric memory is that nondestructive reading of information is possible, rewriting of information is not necessary, problems such as polarization fatigue and memory retention deterioration can be solved, and the memory cell can be made smaller. Can also be maintained.
【図１】本発明の実施形態１の強誘電体メモリ素子の断
面図である。FIG. 1 is a sectional view of a ferroelectric memory device according to a first embodiment of the present invention.
【図２】従来の強誘電体メモリ素子の断面図である。FIG. 2 is a sectional view of a conventional ferroelectric memory device.
【図３】本発明の実施形態２の強誘電体メモリ素子の断
面図である。FIG. 3 is a sectional view of a ferroelectric memory device according to a second embodiment of the present invention.
【図４】本発明の実施形態２で用いた強誘電体メモリ素
子のゲート電圧とドレイン電流との関係を示す図であ
る。FIG. 4 is a diagram showing a relationship between a gate voltage and a drain current of the ferroelectric memory element used in the second embodiment of the present invention.
【符号の説明】 １０ 本発明の強誘電体メモリ素子 １１ 基板 １２ 強誘電体膜 １３ ソース電極 １４ ドレイン電極 １５ ゲート電極 １６ 絶縁膜 １７ 導電膜 ２０ シリコン基板 ２１ ソース領域 ２２ ドレイン領域 ２３ ソース電極 ２４ ドレイン電極 ２５ 強誘電体膜 ２６ ゲート電極 ３０ 強誘電体メモリ素子 ３１ 基板 ３２ 強誘電体膜 ３３ ソース電極 ３４ ドレイン電極 ３５ 導電膜（ゲート電極） ３６ 絶縁膜 ３７ 導電膜（電極） ３８ Ｔｉ膜 ３９ 絶縁膜[Explanation of symbols] 10 Ferroelectric memory device of the present invention 11 board 12 Ferroelectric film 13 Source electrode 14 drain electrode 15 Gate electrode 16 Insulating film 17 Conductive film 20 Silicon substrate 21 Source Area 22 Drain region 23 Source electrode 24 drain electrode 25 Ferroelectric film 26 Gate electrode 30 Ferroelectric memory device 31 substrate 32 Ferroelectric film 33 source electrode 34 drain electrode 35 Conductive film (gate electrode) 36 Insulating film 37 Conductive film (electrode) 38 Ti film 39 Insulating film
Claims (5)
を配置し、前記強誘電体膜を用いてソース電極とドレイ
ン電極とを相互に接続したことを特徴とする強誘電体メ
モリ素子。1. A ferroelectric memory in which a ferroelectric film is disposed between a gate electrode and an insulating film, and a source electrode and a drain electrode are connected to each other by using the ferroelectric film. element.
コニウム、酸化タンタル及びチタン酸バリウムストロン
チウムからなる群より選択される１つからなる請求項１
に記載の強誘電体メモリ素子。2. The insulating film is made of one selected from the group consisting of silicon oxide, zirconium oxide, tantalum oxide, and barium strontium titanate.
A ferroelectric memory device according to item 1.
鉛（Ｐｂ（ＺｒxＴｉ1 -x）Ｏ3）からなる請求項１に記
載の強誘電体メモリ素子。3. The ferroelectric film is zirconate titanate
Lead (Pb (ZrxTi1 -x) O3) Is included in claim 1.
Built-in ferroelectric memory device.
後、前記絶縁膜の上に強誘電体膜と、ソース電極と、ド
レイン電極とを形成し、その後、前記強誘電体膜の上に
ゲート電極を形成することを特徴とする強誘電体メモリ
素子の製造方法。4. A conductive film and an insulating film are formed on a substrate, a ferroelectric film, a source electrode and a drain electrode are formed on the insulating film, and then the ferroelectric film is formed. A method of manufacturing a ferroelectric memory device, which comprises forming a gate electrode on the substrate.
請求項４に記載の強誘電体メモリ素子の製造方法。5. The method of manufacturing a ferroelectric memory device according to claim 4, wherein the substrate is made of an insulator or a semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002141814A JP4100958B2 (en) | 2002-05-16 | 2002-05-16 | Ferroelectric memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002141814A JP4100958B2 (en) | 2002-05-16 | 2002-05-16 | Ferroelectric memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003332538A true JP2003332538A (en) | 2003-11-21 |
| JP4100958B2 JP4100958B2 (en) | 2008-06-11 |
Family
ID=29702295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002141814A Expired - Lifetime JP4100958B2 (en) | 2002-05-16 | 2002-05-16 | Ferroelectric memory device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4100958B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7629635B2 (en) | 2005-09-14 | 2009-12-08 | Panasonic Corporation | Semiconductor memory and driving method for the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326683A (en) * | 1994-06-01 | 1995-12-12 | Fujitsu Ltd | Ferroelectric memory |
| JPH09129839A (en) * | 1995-11-01 | 1997-05-16 | Toshiba Corp | Switching element |
| JP2001135143A (en) * | 1999-08-20 | 2001-05-18 | Matsushita Electric Ind Co Ltd | Dielectric film and method of manufacturing the same |
-
2002
- 2002-05-16 JP JP2002141814A patent/JP4100958B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326683A (en) * | 1994-06-01 | 1995-12-12 | Fujitsu Ltd | Ferroelectric memory |
| JPH09129839A (en) * | 1995-11-01 | 1997-05-16 | Toshiba Corp | Switching element |
| JP2001135143A (en) * | 1999-08-20 | 2001-05-18 | Matsushita Electric Ind Co Ltd | Dielectric film and method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7629635B2 (en) | 2005-09-14 | 2009-12-08 | Panasonic Corporation | Semiconductor memory and driving method for the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4100958B2 (en) | 2008-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100258751B1 (en) | Nonvolatile memory based on metal-ferroelectric-metal-insulator semiconductor structure | |
| JP3460095B2 (en) | Ferroelectric memory | |
| US5541807A (en) | Ferroelectric based capacitor for use in memory systems and method for fabricating the same | |
| EP0490240B1 (en) | Ferroelectric capacitor and method for forming local interconnection | |
| TWI742284B (en) | Semiconductor device and manufacturing method thereof | |
| WO2010131311A1 (en) | Semiconductor memory cell and method for manufacturing same | |
| US5977577A (en) | Ferroelectric based memory devices utilizing low curie point ferroelectrics and encapsulation | |
| US6194751B1 (en) | Ferroelectric based memory devices utilizing low Curie point ferroelectrics and encapsulation | |
| US7151289B2 (en) | Ferroelectric capacitor and semiconductor device having a ferroelectric capacitor | |
| CN1192438C (en) | Ferroelectric transistor and use thereof in a memory cell arrangement | |
| JP3131340B2 (en) | Ferroelectric memory element | |
| JP3160324B2 (en) | Semiconductor storage element | |
| JP4100958B2 (en) | Ferroelectric memory device and manufacturing method thereof | |
| JP3160325B2 (en) | Semiconductor storage element | |
| JP2000349251A (en) | Semiconductor device | |
| JP3169406B2 (en) | Nonvolatile semiconductor memory device | |
| JP2000323669A (en) | Semiconductor nonvolatile memory device | |
| WO1992002956A1 (en) | Semiconductor device and its manufacturing method | |
| JP3606367B2 (en) | MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE | |
| JPH113976A (en) | Dielectric element, ferroelectric memory and its operation method | |
| JP2002141479A (en) | Capacitively coupled ferroelectric random access memory cell and method of manufacturing the same | |
| JP4827316B2 (en) | Method for driving ferroelectric transistor type nonvolatile memory element | |
| JP3559486B2 (en) | Semiconductor storage element | |
| JPH09321237A (en) | Nonvolatile semiconductor memory device having ferroelectric film, capacitor having ferroelectric film, and manufacturing method thereof | |
| JP2001118941A (en) | Ferroelectric transistor type nonvolatile memory element and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20050106 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20050106 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050412 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071121 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071127 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080125 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080226 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080318 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110328 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4100958 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110328 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120328 Year of fee payment: 4 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130328 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130328 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |