JP2003332340A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a buried wiring without chipping an upper end corner part of a wiring groove. <P>SOLUTION: Insulation films 28, 29 and 30 and a photoresist pattern are formed on an insulation film 27. The insulation film 30 is removed, by using the photoresist pattern as an etching mask and an opening part 32 is formed. The photoresist pattern is removed, an insulation film 29 exposed from the opening part 32 is removed by using the insulation film 30 as an etching mask and insulation films 33, 34, 35 and 36 and a photoresist pattern are formed. The insulation films 34, 35 and 36 are selectively removed, by using the photoresist pattern as an etching mask and an opening part 38 is formed. The insulation film 33, exposed from the opening part 38, is etched and the photoresist pattern is removed, while etching the insulation film 28 exposed from the opening part 32 in a bottom part of the opening part 38. After the insulation film 36 and the insulation film 27 exposed from the opening part 32 are removed, copper wiring is formed inside the opening parts 32 and 38. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effectively applied to a semiconductor device manufacturing method having a buried wiring including a main conductor film containing copper as a main component.

[0002]

2. Description of the Related Art In recent years, a wiring forming technique called, for example, damascene has been studied. This damascene method can be roughly classified into a single damascene method and a dual damascene method. In the single damascene method, for example, after forming a wiring groove in an insulating film, a main conductive layer for forming a wiring is deposited on the insulating film and in the wiring groove, and the main conductive layer is further polished by, for example, chemical mechanical polishing. Method (CMP; Chemical Mechanical Polishin
This is a method of forming an embedded wiring in the wiring groove by polishing so that it is left only in the wiring groove by g). Further, the dual damascene method, after forming a wiring groove and a hole for connection with the lower layer wiring in the insulating film, deposit a main conductive layer for forming a wiring on the insulating film, in the wiring groove and the hole, Further, the main conductive layer is polished by CMP or the like so as to be left only in the wiring groove and the hole, thereby forming a buried wiring in the wiring groove and the hole. In either method, a low-resistance material such as copper is used as the main conductor material of the wiring from the viewpoint of improving the performance of the semiconductor device. Copper has an advantage that it has a lower resistance than aluminum and an allowable current in reliability is larger by two digits or more. Since the film can be thinned to obtain the same wiring resistance, the capacitance between adjacent wirings can be reduced. However, it is said that copper is more likely to diffuse into the insulating film than a metal such as aluminum. For this reason, when copper is used as a wiring material, a thin conductive layer is formed on the surface (bottom surface and side surface) of the main conductor layer made of copper, that is, on the inner wall surface (side surface and bottom surface) of the wiring groove to prevent copper diffusion. It is said that it is necessary to form a barrier film. Further, by forming a barrier insulating film made of, for example, a silicon nitride film on the entire upper surface of the insulating film in which the wiring trench is formed so as to cover the upper surface of the embedded wiring, copper in the embedded wiring is There is a technique for preventing diffusion from the upper surface of the buried wiring into the insulating film.

[0003]

However, according to the results of studies by the present inventors, in the above-mentioned embedded wiring technique,
We found the following issues.

In recent years, the distance between such buried wirings has been decreasing with the high integration of semiconductor devices. As a result, the parasitic capacitance between the wirings increases and signal delay occurs, causing crosstalk with the adjacent wirings. Therefore, it is desired to reduce the parasitic capacitance between wirings. In order to reduce the parasitic capacitance between the wirings, a low dielectric constant material is used as the inter-wiring insulating film.

A low dielectric constant material such as an organic polymer is used for the insulating film.
-When using low-dielectric constant material, oxygen plasma is used
If it is present, the low-dielectric-constant insulating film will be damaged and its thickness will decrease.
It may get a little bit. Therefore, the low dielectric constant insulating film
When exposed, remove the photoresist pattern.
Oxygen-based ashing process cannot be performed. Therefore, low dielectric
When etching the insulating film, the photoresist
It is desirable to eliminate turns. Conclusion by the inventors
According to the results, NH₃Plasma treatment or N₂/ H ₂Plas
While etching the low dielectric constant insulating film
Ashing and removing the photoresist pattern
You can As a result, the low dielectric constant insulating film becomes oxygen plasma.
To prevent damage due to
Of Wiring Groove by Etching and Photoresist Pattern
It becomes possible to simultaneously remove the cords. Also low
A cap film (silicon oxide film) is previously formed on the dielectric constant insulating film.
By forming it, a low dielectric constant insulating film by CMP processing
Can prevent damage.

However, in the step of removing the photoresist pattern while etching the low dielectric constant insulating film, the photoresist is removed by over-etching for completely opening the low dielectric constant insulating film and completely removing the photoresist pattern. The cap film of the low-dielectric-constant insulating film under the resist pattern may be etched by the sputter etch component, and the upper end corners (shoulders) of the wiring groove (opening) may be scraped and rounded, that is, shoulder scraping may occur. .

Also in the subsequent etching process, the cap film of the low dielectric constant insulating film is etched, and the upper corners of the wiring groove are abraded (shouldered).

When such shoulder scraping occurs, when the conductor film is embedded in the wiring groove, the vicinity of the upper end portion of the wiring groove (shoulder scraping portion)
The conductor is also embedded in. The conductor embedded in the shoulder scraping portion may remain without being removed by the CMP process. This shortens the substantial distance between the adjacent wirings of the same layer wiring and lowers the dielectric breakdown resistance between the wirings.

In particular, when copper is used as a wiring material, TDD
There is a problem that the B (Time Dependence on Dielectric Breakdown) life is significantly shorter than that of other metal materials (for example, aluminum and tungsten). Moreover, as the wiring pitch becomes finer and the effective electric field strength tends to increase, an insulating film having a low dielectric constant generally has a low withstand voltage as well, so that it becomes more and more difficult to secure the TDDB life. There is a situation. Moreover, the copper diffusion path, which is considered to be the cause of the deterioration of the TDDB life, is the CMP between the adjacent wirings.
The surface (the surface polished by CMP) is dominant, and the CMP surface acts as a leak path and causes deterioration of the TDDB life. For this reason, if the shoulder scraping occurs in the formation of copper wiring, the TDDB life or the dielectric breakdown resistance is adversely affected. Regarding the cause of deterioration of TDDB life, Japanese Patent Application No. 11-226876 and Japanese Patent Application No. 2000-10 filed by the present inventor
No. 4015 or Japanese Patent Application No. 2000-300453.

Japanese Patent Laid-Open No. 2000-3961 discloses a technique of forming a wiring by a dual damascene method using a dielectric layer made of an organic polymer having a low relative dielectric constant.

However, the above-mentioned Japanese Patent Laid-Open No. 2000-396.
Even in the technique disclosed in Japanese Patent Laid-Open No. 1-58, when the etching (wiring groove formation) of the low dielectric constant dielectric layer and the removal of the mask (photoresist pattern) are performed simultaneously, the low dielectric constant dielectric exposed by the removal of the mask Since the cap film (third stop layer) of the body layer is also etched, it is difficult to avoid the occurrence of shoulder scraping at the upper corners of the wiring groove. Therefore, when the conductor film is embedded in the wiring groove, the conductor may be embedded in the shoulder scraping portion and may remain without being removed by the CMP process. This substantially shortens the distance between adjacent wirings of the same layer wiring, and lowers the dielectric breakdown resistance between the wirings.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving dielectric breakdown resistance.

Another object of the present invention is to provide a method of manufacturing a semiconductor device in which a buried wiring can be formed without scraping the upper corners of the wiring groove.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The method of manufacturing a semiconductor device according to the present invention comprises a step of preparing a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate, and a second step of forming a low dielectric constant material on the first insulating film. Step of forming insulating film, step of forming third insulating film on second insulating film, step of forming fourth insulating film on third insulating film, mask pattern on fourth insulating film Forming the first insulating film, selectively removing the fourth insulating film using the mask pattern as an etching mask to form the first opening, and removing the third insulating film exposed from the first opening And a step of removing the second insulating film and the mask pattern exposed from the first opening, and a step of forming a wiring in the first opening.

The semiconductor device manufacturing method of the present invention is
A step of preparing a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate, a step of forming a second insulating film made of a low dielectric constant material on the first insulating film, a step of forming the second insulating film Forming a third insulating film, forming a fourth insulating film on the third insulating film, forming a first mask pattern on the fourth insulating film, first mask pattern Forming a first opening by selectively removing the fourth insulating film by using as an etching mask, a step of removing the first mask pattern, a third insulating film exposed from the first opening A step of removing the film, a step of forming a fifth insulating film made of a low dielectric constant material on the fourth insulating film so as to fill the first opening, and a step of forming a sixth insulating film on the fifth insulating film. Forming step, forming a seventh insulating film on the sixth insulating film, forming a second insulating film on the seventh insulating film Forming a mask pattern,
A step of selectively removing the seventh insulating film by using the second mask pattern as an etching mask to form a second opening, and a step of removing the sixth insulating film exposed from the second opening. Removing the fifth insulating film exposed from the second opening and removing the second insulating film exposed from the first opening at the bottom of the second opening and removing the second mask pattern And the step of forming wiring in the first opening and the second opening.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(First Embodiment) A semiconductor device and a manufacturing process thereof according to the present embodiment will be described with reference to the drawings. Figure 1
Is a semiconductor device according to an embodiment of the present invention, for example, C
MISFET (Complementary Metal Insulator Semico)
nductor Field Effect Transistor), and FIG. 2 is a sectional view taken along the line AA of FIG. 1.

As shown in FIGS. 1 and 2, for example, 1-1.
An element isolation region 2 is formed on the main surface of a wafer or semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 0 Ωcm. The element isolation region 2 is made of silicon oxide or the like, and is, for example, STI (Shallow Trench
Isolation) method or LOCOS (Local Oxidization)
of Silicon) method or the like.

A p-type well 3 and an n-type well 4 are formed on the semiconductor substrate 1 over a predetermined depth from the main surface thereof. The p-type well 3 is formed, for example, by ion-implanting impurities such as boron, and the n-type well 4 is formed, for example, by ion-implanting impurities such as phosphorus.

In the region of the p-type well 3, the element isolation region 2
In the active region surrounded by, n-channel type MISFET5
Are formed. In the region of the n-type well 4, a p-channel type M is formed in the active region surrounded by the element isolation region 2.
ISFET 6 is formed. The gate insulating film 7 of the n-type MISFET 5 and the p-type MISFET 6 is made of, for example, a thin silicon oxide film, and is formed by, for example, a thermal oxidation method.

N-type MISFET 5 and p-type MISFE
The gate electrode 8 of T6 is formed, for example, by stacking a titanium silicide (TiSi _x ) layer or a cobalt silicide (CoSi _x ) layer on a low resistance polycrystalline silicon film. Sidewall spacers or sidewalls 9 made of, for example, silicon oxide are formed on the sidewalls of the gate electrode 8.

The source and drain regions of the n ^- type MISFET 5 are LDs each having an n ^-- type semiconductor region 10a and an n ⁺ -type semiconductor region 10b having a higher impurity concentration.
It has a D (Lightly Doped Drain) structure. The n ⁻ type semiconductor region 10 a is formed, for example, by ion-implanting impurities such as phosphorus into regions of the p type well 3 on both sides of the gate electrode 8 before forming the sidewall 9.
The n ⁺ type semiconductor region 10b is formed, for example, by ion-implanting impurities such as phosphorus into regions on both sides of the gate electrode 8 and the sidewall 9 of the p-type well 3 after forming the sidewall 9.

The source and drain regions of the p-type MISFET 6 are LDs each having a p ⁻ type semiconductor region 11a and ap ⁺ type semiconductor region 11b having a higher impurity concentration.
It has a D structure. The p ⁻ type semiconductor region 11a is formed, for example, by ion-implanting impurities such as boron into regions on both sides of the gate electrode 8 of the n-type well 4 before forming the sidewall 9. p ⁺ type semiconductor region 1
1b is formed, for example, by ion-implanting impurities such as boron into regions of the n-type well 4 on both sides of the gate electrode 8 and the sidewall 9 after the sidewall 9 is formed. Further, a silicide layer such as a titanium silicide layer or a cobalt silicide layer is formed on a part of the upper surfaces of the n ⁺ type semiconductor region 10b and the p ⁺ type semiconductor region 11b.

An insulating film 12 is formed on the semiconductor substrate 1 so as to cover the gate electrode 8 and the sidewall 9.
Are formed. The insulating film 12 is a highly reflowable insulating film that can fill a narrow space between the gate electrodes 8.
For example, BPSG (Boron-doped Phospho Silicate Glas
s) Consists of a film. A contact hole 13 is formed in the insulating film 12. At the bottom of the contact hole 13, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor region 10b and a part of the p ⁺ type semiconductor region 11b,
Part of the gate electrode 8 and the like are exposed.

A plug 14 made of tungsten (W) or the like is formed in the contact hole 13. For the plug 14, for example, after forming a titanium nitride film 14a as a barrier film on the insulating film 12 including the inside of the contact hole 13, a tungsten film is formed by CVD (Ch
Titanium nitride film 1 by emical vapor deposition method
4a is formed so as to fill the contact hole 13,
It is formed by removing the unnecessary tungsten film and titanium nitride film 14a on the insulating film 12 by the CMP method or the etch back method.

A first layer wiring 15 made of, for example, tungsten is formed on the insulating film 12 in which the plug 14 is embedded. The first layer wiring 15 is electrically connected via the plug 14 to the source / drain semiconductor regions 10b and 11b of the n-type MISFET 5 and the p-type MISFET 6 and the gate electrode 8. First layer wiring 15
Is not limited to tungsten, but can be variously changed. For example, titanium (Ti), titanium nitride (TiN), etc. can be used as a simple substance film of aluminum (Al) or an aluminum alloy or at least one of upper and lower layers of these simple substance films. It may be a laminated metal film having a different metal film formed thereon.

The first layer wiring 15 is formed on the insulating film 12.
An insulating film 16 is formed so as to cover the. Insulation film 1
6 is a low dielectric constant material such as organic polymer or organic silica glass (so-called Low-K insulating film, L
ow-K material). In addition, a low dielectric constant insulating film (L
An ow-K insulating film is a silicon oxide film (for example, TEOS (Tetraethoxysilan) included in the passivation film.
e) An insulating film having a dielectric constant lower than that of (oxide film) can be exemplified. In general, a TEOS oxide film having a relative dielectric constant ε of about 4.1 to 4.2 or less is called a low dielectric constant insulating film.

The organic polymer as the low dielectric constant material includes, for example, SiLK (manufactured by The Dow Chemical Co., USA, relative permittivity = 2.7, heat resistance temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0 to 5). .0 MV / Vm) or polyallyl ether (PAE) based material FLARE (Honeywell Electr
Made by onic Materials, relative permittivity = 2.8, heat resistant temperature = 40
0 ° C or higher). This PAE-based material is characterized by high basic performance and excellent mechanical strength, thermal stability, and low cost. The organic silica glass (SiOC-based material) as the low dielectric constant material is, for example, HSG.
-R7 (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.8, heat resistance temperature = 650 ° C.), Black Diamond (Applied in the US)
Materials, Inc., relative permittivity = 3.0 to 2.4, heat resistance temperature = 450 ° C.) or p-MTES (Hitachi development, relative permittivity = 3.2). Other SiOC materials include, for example, CORAL (manufactured by Novellus Systems, Inc.,
Relative permittivity = 2.7 to 2.4, heat resistant temperature = 500 ° C.), A
urora 2.7 (manufactured by Japan ASM Ltd., relative dielectric constant = 2.7, heat resistance temperature = 450 ° C.).

The low dielectric constant material of the insulating film 16 is, for example, FSG (SiOF based material) or HSQ (hydrogen silc).
sesquioxane) material, MSQ (methyl silsesquioxan)
An e) -based material, a porous HSQ-based material, a porous MSQ-based material, or a porous organic-based material can also be used. Examples of the HSQ-based material include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 3.4 to 2.9, heat resistance temperature = 45).
0 ° C.), FOx (manufactured by Dow Corning Corp., US, relative permittivity =
2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.5, heat resistant temperature = 450 ° C.). Examples of the MSQ-based material include OCD T-9 (manufactured by Tokyo Ohka Kogyo, relative dielectric constant = 2.7, heat resistance temperature = 600 ° C.), L
KD-T200 (manufactured by JSR, relative dielectric constant = 2.7 to 2.
5, heat-resistant temperature = 450 ℃, HOSP (Honeywell El
Made by ectronic Materials, relative permittivity = 2.5, heat resistance =
550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.5, heat resistance temperature = 650 ° C.), OCL T-3
1 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.3, heat resistance temperature = 5)
00 ° C.) or LKD-T400 (manufactured by JSR, relative dielectric constant = 2.2 to 2, heat resistant temperature = 450 ° C.) and the like. Examples of the porous HSQ materials include XLK (US Dow Corn
ing Corp. Made, relative permittivity = 2.5 to 2), OCLT-7
2 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.2 to 1.9, heat resistance temperature = 450 ° C.), Nanoglass (Honeywell, USA)
Made by Electronic Materials, relative permittivity = 2.2-1.8,
Heat-resistant temperature = 500 ° C or higher) or MesoELK (US Ai)
r Productsand Chemicals, Inc., dielectric constant = 2 or less). For the porous MSQ-based material, for example, H
SG-6211X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.
4, heat resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Corporation, relative dielectric constant = 2.3 to 1.8, heat resistant temperature = 450
° C), OCL T-77 (manufactured by Tokyo Ohka Kogyo, dielectric constant =
2.2-1.9, heat resistant temperature = 600 ° C.), HSG-62
10X (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.1, heat resistance temperature = 650 ° C.) or silica aerogel (manufactured by Kobe Steel, relative permittivity 1.4 to 1.1). Examples of the porous organic material include PolyELK (rice
Manufactured by Air Productsand Chemicals, Inc., dielectric constant = 2 or less, heat resistance temperature = 490 ° C.). The SiOC-based material and the SiOF-based material are formed by, for example, the CVD method. For example, the above BlackDiamond
It is formed by a CVD method using a mixed gas of trimethylsilane and oxygen. Further, the p-MTES is
For example, it is formed by a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

An insulating film 17 for a Low-K cap is formed on the insulating film 16 made of such a Low-K material. The insulating film 17 is made of, for example, a silicon oxide (SiO _x ) film typified by silicon dioxide (SiO ₂ ). For example, the mechanical strength of the insulating film 16 during CMP processing, surface protection, and moisture resistance are ensured. It has the following functions. The thickness of the insulating film 17 is
It is relatively thinner than the above, for example, about 25 nm to 100 nm. However, the insulating film 17 is not limited to the silicon oxide film and can be variously modified. As the insulating film 17, for example, a silicon nitride (Si _x N _y ) film, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film may be used. These silicon nitride film, silicon carbide film or silicon carbonitride film can be formed by, for example, a plasma CVD method. The silicon carbide film formed by the plasma CVD method is, for example, BLOk (AM
There is a dielectric constant = 4.3) manufactured by AT company. At the time of formation, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used, for example. Vias or through holes 18 through which a part of the first layer wiring 15 is exposed are formed in such insulating films 16 and 17. A plug 19 made of, for example, tungsten is embedded in the through hole 18.

3 to 5 are sectional views showing the main part of the semiconductor device during the manufacturing process following FIG. Note that, for easy understanding, in FIGS. 3 to 5, portions corresponding to the structure below the insulating film 17 in FIG. 2 are not shown.

First, in this embodiment, as shown in FIG. 3, the insulating film 20 is formed on the insulating film 17 in which the plug 19 is embedded. The insulating film 20 is, for example, L
It can be formed using an ow-K material.

Next, a thin insulating film 21 is formed on the insulating film 20. The insulating film 21 is formed by a CVD method, for example, plasma CVD.
It can be formed by using the method. Insulating film 21
Has a thickness of, for example, about 10 to 20 nm. The insulating film 21 is preferably an insulating film formed without using oxidizing plasma such as oxygen (O ₂ ) plasma,
For example, it is made of a silicon nitride (Si _x N _y ) film. Insulation film 2
For example, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film may be used as the other material.
As the silicon carbide film formed by the plasma CVD method, for example, BLOk (manufactured by AMAT, relative permittivity = 4.
There is 3). At the time of formation, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used, for example. Further, in forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ) and trimethylsilane (3MS) is used. The plasma in an oxidizing atmosphere is, for example, a plasma environment in which reactive species such as radicals, ions, atoms, and molecules having an oxidizing action are predominantly present.

Next, an insulating film 22 is formed on the insulating film 21 by CVD.
It is formed by using the method. The thickness of the insulating film 22 is relatively smaller than that of the insulating film 20, and is, for example, 25 nm to 100 nm.
It is a degree. The insulating film 22 is made of, for example, a silicon oxide film typified by silicon dioxide. The insulating film 22 is preferably made of a material having a dielectric constant lower than that of silicon nitride in order to reduce the parasitic capacitance between the adjacent wirings of the second layer wiring 26 formed later, and the material having a relative dielectric constant of 5 or less. More preferably, Silicon oxide is preferable as the material of the insulating film 22, but other materials such as Si can be used.
An OC film (silicon oxycarbide film, organic silica glass film) may be used. Alternatively, as another material of the insulating film 22,
A SiON film having a nitrogen content of less than 10% can also be used.

The insulating film 21 can function to improve the adhesion between the insulating film 20 and the insulating film 22. For example, when a silicon oxide film is directly formed on the insulating film 20, the surface of the insulating film 20 made of the Low-K material is damaged by the plasma of N ₂ O or O ₂ gas component at the time of forming the silicon oxide film. There is a risk of receiving it. By forming the insulating film 21 between the insulating film 20 and the insulating film 22, such a defect can be prevented. Further, since the insulating film 21 is thin, the parasitic capacitance between adjacent wirings of the second layer wiring 26 formed later is hardly increased by the insulating film 21. The formation of the insulating film 21 may be omitted. Further, the insulating film 22 has functions such as securing mechanical strength of the insulating film 20 during CMP processing, surface protection, and moisture resistance.

Next, the insulating film 23 is formed on the insulating film 22. The insulating film 23 is formed by a CVD method such as a plasma CVD method,
And the like. The insulating film 23 is made of, for example, a silicon nitride film. As another material for the insulating film 23, for example, a silicon carbide (SiC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. The insulating film 23 is formed by an etching process other than the etching process for removing the insulating film 23.
It functions to prevent the underlying insulating film 22 from being etched and causing shoulder scraping.

Next, an antireflection film 24a is formed on the insulating film 23. Then, a photoresist film is formed on the antireflection film 24a, and the photoresist film is patterned by exposure to form a photoresist pattern 24b. As a result, the structure shown in FIG. 3 is obtained.

Next, as shown in FIG. 4, the antireflection film 24a is selectively removed by a dry etching method using the photoresist pattern 24b as an etching mask. Then, the insulating film 2 is formed by a dry etching method using the photoresist pattern 24b as an etching mask.
Selectively remove 3. Then, the insulating film 22 is selectively removed by a dry etching method using the photoresist pattern 24b as an etching mask. After that, the insulating film 21 is selectively removed by a dry etching method using the photoresist pattern 24b as an etching mask. As a result, the opening 25 is formed and the opening 25
The insulating film 20 is exposed at the bottom of the.

Next, as shown in FIG.
The insulating film 20 exposed from the NH ₃ plasma treatment or N ₂
The photoresist pattern 24b and the antireflection film 24a are removed by ashing while being etched by a reducing plasma treatment such as / H ₂ plasma treatment. The reducing atmosphere plasma is, for example, a reducing action,
That is, it is a plasma environment in which reactive species such as radicals, ions, atoms, and molecules having an action of extracting oxygen are predominantly present.

Then, the insulating film 23 is removed by etching or the like. As a result, a wiring groove including the opening 25 formed in the insulating films 20, 21 and 22 is formed, and the upper surface of the plug 19 is exposed from the bottom surface of the wiring groove. Further, a conductive barrier film 26a and a main conductor film 26b, which will be described later, are formed with the insulating film 23 left, and CMP is performed.
Conductive barrier film 26a and main conductor film 26 unnecessary for processing
The insulating film 23 can be removed when removing b.

In the step of etching the insulating film 20, the insulating film 20 is completely opened and the photoresist pattern 2 is formed.
4b and the antireflection film 24a must be completely removed. Therefore, some over-etching is necessary. Therefore, if the insulating film 23 is not formed, the insulating film 22 is also etched, and the upper end corner portion (shoulder portion) of the opening 25 is shaved and rounded, that is, shoulder shading occurs. When such shoulder scraping occurs, the conductor is embedded in the shoulder scraping portion (near the upper end of the opening 25) in the step of forming the conductive barrier film 26a and the main conductor film 26b, which will be described later, and is not removed even by the CMP step. It may remain. This substantially reduces the distance between adjacent wirings of the same layer wiring (here, the second layer wiring 26 to be formed later), and lowers the dielectric breakdown resistance between the wirings.

In this embodiment, since the insulating film 23 is present on the insulating film 22, the insulating film 23 is simply etched in the etching process of the insulating film 20 even if overetching is performed. The insulating film 22 is hardly affected. In addition, even if some insulating film 23 is left on the insulating film 22 finally, there is no adverse effect.
In the step of removing 3, it is not necessary to perform overetching. Therefore, the insulating film 22 is hardly etched, and the shoulder scraping does not occur.

FIG. 6 is a plan view of an essential part of a region corresponding to FIG. 1 during the manufacturing process of the semiconductor device following FIG. 5, and FIG. 7 is a sectional view taken along line AA of FIG. Note that, also in FIG. 7, a portion corresponding to the structure below the insulating film 17 in FIG. 2 is omitted.

After the wiring groove formed of the opening 25 is formed, for example, titanium nitride (Ti) is formed on the entire main surface of the substrate 1.
A thin conductive barrier film (first conductor film) 26a made of N) or the like and having a thickness of about 50 nm is formed by using a sputtering method or the like. The conductive barrier film 26a has, for example, a function of suppressing or preventing diffusion of copper for forming a main conductor film, which will be described later, and a function of improving wettability of copper during reflow of the main conductor film. As a material of such a conductive barrier film 26a, instead of titanium nitride, tungsten nitride (WN) or tantalum nitride (Ta) which hardly reacts with copper is used.
Refractory metal nitrides such as N) can also be used. Further, as the material of the conductive barrier film 26a, a material obtained by adding silicon (Si) to a refractory metal nitride, tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (which is difficult to react with copper). A refractory metal such as a TiW) alloy can also be used.

Then, on the conductive barrier film 26a, a main conductor film (second conductor film) 26b made of, for example, relatively thick copper having a thickness of about 800 to 1600 nm is formed. The main conductor film 26b can be formed by using, for example, a CVD method, a sputtering method, a plating method, or the like. afterwards,
For example, the main conductor film 26b is reflowed by heat-treating the substrate 1 in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at about 475 ° C., and copper is embedded in the opening or the wiring groove 25 without any space.

Next, the main conductor film 26b and the conductive barrier film 2
6a is polished by CMP until the upper surface of the insulating film 22 is exposed. As a result, as shown in FIGS. 6 and 7, the second layer wiring (wiring) 26 including the relatively thin conductive barrier film 26a and the relatively thick main conductor film 26b is formed in the wiring groove (opening) 25. To form. The second layer wiring 26 is
It is electrically connected to the first layer wiring 15 via the plug 19. Further, the second-layer wiring 26 has a planar shape, for example, in the shape of a band, as shown in FIG.

Next, the semiconductor substrate 1 is placed in a processing chamber of a plasma CVD apparatus, and ammonia gas is introduced to apply a plasma power source to the substrate 1 (especially the CMP surface where the second layer wiring 26 is exposed). In contrast, ammonia (NH
₃ ) Perform plasma treatment. Alternatively, N ₂ gas and H ₂
Gas is introduced to perform N ₂ / H ₂ plasma treatment. By such a reducing plasma treatment, the copper oxide (CuO, CuO ₂ ) on the surface of the copper wiring oxidized by CMP is reduced to copper (Cu), and the copper nitride (CuN) layer forms the second layer wiring 26. Formed on the surface (thin area).

8 to 16 are cross-sectional views of essential parts in the manufacturing process of the semiconductor device, following FIG. Note that FIG.
1 to 16, the portions corresponding to the structure below the insulating film 17 in FIG. 2 are not shown.

After cleaning as needed, an insulating film 27 is formed on the entire main surface of the semiconductor substrate 1 by plasma CVD or the like, as shown in FIG. That is, the second
The insulating film 27 is formed on the insulating film 22 including the upper surface of the layer wiring 26.
To form. The insulating film 27 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore,
The insulating film 27 suppresses or prevents the copper in the main conductor film 26b of the second layer wiring 26 from diffusing into the interlayer insulating film 28 formed later. Other materials for the insulating film 27 include, for example, a silicon carbide (SiC) film and a silicon carbonitride (SiC).
A single film of N) film or silicon oxynitride (SiON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. The silicon carbide film formed by the plasma CVD method includes, for example, BLOk (manufactured by AMAT). The film forming gas is as described above. When the SiCN film is formed, for example, helium (H
A mixed gas of e), ammonia (NH ₃ ) and trimethylsilane (3MS) is used. Further, as the silicon oxynitride film formed by the plasma CVD method, there is, for example, PE-TMS (manufactured by Canon, dielectric constant = 3.9). In forming the silicon oxynitride film, for example, trimethoxysilane (TMS) gas and nitric oxide (N ₂ O) are used.
A mixed gas with a gas is used.

Next, the insulating film 28 is formed on the insulating film 27. In order to reduce the parasitic capacitance between the upper layer wiring (third layer wiring 39 described later) and the lower layer wiring (second layer wiring 26), the insulating film 28 is preferably formed using the above-mentioned Low-K material. .

Next, a thin insulating film 29 C is formed on the insulating film 28.
It is formed by using the VD method or the like. The insulating film 29 is, for example, 1
It has a thickness of about 0 to 20 nm. The insulating film 29 is preferably an insulating film formed without using oxidizing plasma such as oxygen plasma, and is made of, for example, a silicon nitride (Si _x N _y ) film. As another material of the insulating film 29, for example, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film may be used. Then, the insulating film 30 is formed on the insulating film 29 by the CVD method or the like.
The insulating film 30 is made of, for example, a silicon oxide film. After forming the insulating film 30, CMP treatment is performed as necessary to planarize the upper surface of the insulating film 30. Like the insulating film 21, the insulating film 29 can function to improve the adhesion between the insulating film 28 and the insulating film 30. Further, since the insulating film 29 is thin, the inter-wiring capacitance hardly increases.

Next, an antireflection film 31a is formed on the insulating film 30. Then, a photoresist film is formed on the antireflection film 31a, and the photoresist film is patterned by exposure to form a photoresist pattern 31b. As a result, the structure shown in FIG. 8 is obtained.

Next, the antireflection film 31a is selectively removed by a dry etching method using the photoresist pattern 31b as an etching mask. Then, the insulating film 30 is selectively removed by a dry etching method using the photoresist pattern 31b as an etching mask to form an opening 32. In the step of forming the opening 32, the insulating film 29 functions as an etching stopper. Then, the remaining photoresist pattern 31b and antireflection film 31a are removed by ashing. As a result, the structure shown in FIG. 9 is obtained. At this time, Low-
Since the insulating film 28 made of the K material is protected by the insulating film 29, the photoresist pattern 31b and the antireflection film 31a can be removed by oxygen-based ashing treatment.

Then, after performing cleaning as necessary, FIG.
0, the insulating film 29 exposed from the opening 32 is selectively removed by a dry etching method using the insulating film 30 as an etching mask, and the insulating film 28 is exposed at the bottom of the opening 32.

Next, as shown in FIG. 11, the opening 3
An insulating film 33 is formed on the insulating film 30 so as to fill the inside of 2. The insulating film 33 is made of the same material as the insulating film 28, that is, a Low-K material. As a material of the insulating film 33,
When the coating type Low-K material is used, the upper surface of the insulating film 33 is flattened without being affected by the step due to the opening 32.

Next, a thin insulating film 34 similar to the insulating film 29 is formed on the insulating film 33. The insulating film 34 has a thickness of, for example, about 10 to 20 nm. The insulating film 34 is preferably an insulating film formed without using oxidizing plasma such as oxygen plasma, and is made of, for example, a silicon nitride film. Other materials for the insulating film 34 include, for example, a silicon carbide (SiC) film or a silicon carbonitride (SiC).
N) film may be used.

Next, an insulating film 35 is formed on the insulating film 34 by CVD.
It is formed by using the method. The thickness of the insulating film 35 is relatively smaller than that of the insulating film 33, and is, for example, 25 nm to 100 nm.
It is a degree. The insulating film 35 is made of, for example, a silicon oxide film typified by silicon dioxide. The insulating film 22 is preferably made of a material having a lower dielectric constant than silicon nitride in order to reduce the capacitance between adjacent wirings of the same layer wiring,
More preferably, it is made of a material having a relative dielectric constant of 5 or less.
The material of the insulating film 35 is preferably silicon oxide, but as the other material of the insulating film 35, for example, a SiOC film may be used. Alternatively, as the other material of the insulating film 35, a SiON film having a nitrogen content of less than 10% can be used.

Like the insulating films 21 and 29, the insulating film 34 can function to improve the adhesion between the insulating film 33 and the insulating film 35. The insulating film 35 is, for example, CMP.
It has functions such as securing the mechanical strength of the insulating film 33 during processing, surface protection, and moisture resistance. The formation of the insulating film 34 can be omitted.

Next, the insulating film 36 is formed on the insulating film 35. The insulating film 36 is made of, for example, a silicon nitride film. As another material of the insulating film 36, for example, silicon carbide (Si
A C) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used. The insulating film 36 is
In an etching process other than the etching process for removing the insulating film 36, it functions to prevent the underlying insulating film 35 from being etched and causing shoulder scraping.

Next, an antireflection film 37a is formed on the insulating film 36. Then, a photoresist film is formed on the antireflection film 37a, and the photoresist film is patterned by exposure to form a photoresist pattern 37b. As a result, the structure shown in FIG. 11 is obtained.

Next, as shown in FIG. 12, the antireflection film 37a is selectively removed by a dry etching method using the photoresist pattern 37b as an etching mask. After that, the insulating film 3 is formed by a dry etching method using the photoresist pattern 37b as an etching mask.
6 is selectively removed to form the opening 38. The plane area of the opening 32 is included (or overlaps) within the plane area of the opening 38.

Next, as shown in FIG. 13, the insulating film 3 exposed from the opening 38 is formed by the dry etching method using the photoresist pattern 37b as an etching mask.
5 is selectively removed. Then, the insulating film 34 exposed from the opening 38 is selectively removed by a dry etching method using the photoresist pattern 37b as an etching mask. As a result, the insulating film 3 is formed at the bottom of the opening 38.
3 is exposed.

Next, as shown in FIG. 14, the opening 3
While etching the insulating film 33 exposed from 8 and the insulating film 28 exposed from the opening 32 by reducing plasma treatment such as NH ₃ plasma treatment or N ₂ / H ₂ plasma treatment, the photoresist pattern 37b is formed. And the antireflection film 37a is removed by ashing. In this etching process, the insulating film 27 and the insulating film 30 function as an etching stopper. As mentioned above, the planar area of the opening 32 is contained (or overlaps) within the planar area of the opening 38. Therefore, when the insulating film 33 is etched, the insulating film 28 is exposed from the opening 32 at the bottom of the opening 38. Therefore, the insulating film 33 and the insulating film 28 can be etched at the same time, and at the same time, the photoresist pattern 37b and the antireflection film 37a can be removed. Further, the photoresist pattern 37b is formed so that the thicknesses of the insulating film 33 and the insulating film 28 to be etched are substantially the same as the remaining photoresist pattern 37b and antireflection film 37a.
By setting the initial formation thickness of the antireflection film 37a, the overetching amount in this etching step can be small.

Next, as shown in FIG. 15, the insulating film 27 exposed at the bottom of the opening 32 is removed by dry etching to expose the second layer wiring 26. At this time, the insulating film 36 can also be removed. If the insulating film 36 is not formed, the upper corner portion of the insulating film 35, which is the upper corner portion of the opening 38, is formed by the etching step of the insulating film 33 and the insulating film 28 and the subsequent etching step of the insulating film 27. Is etched, and it is sharpened and rounded. That is, shoulder scraping occurs. If the insulating film 35 is shaved, a shoulder shaved portion (opening 38) of the insulating film 35 will be formed in a process of forming a conductive barrier film 39a and a main conductor film 39b described later.
The conductor may be embedded in the vicinity of the upper end of) and remain without being removed by the CMP process. This reduces the distance between adjacent wirings of the same layer wiring (here, the third layer wiring 39 to be formed later), and lowers the dielectric breakdown resistance.

In this embodiment, since the insulating film 36 is present on the insulating film 35, the insulating film 33 and the insulating film 28 are formed.
The insulating film 35 is hardly affected by the etching process of 1. and the subsequent etching process of the insulating film 27. If the insulating film 36 is formed to have a thickness substantially similar to that of the insulating film 27, the insulating film 35 is exposed and the insulating film 35 is almost etched when the second layer wiring 26 is exposed at the bottom of the opening 32. Not done. Therefore, the shoulder scraping of the insulating film 35 does not occur at the end of the opening 38. Further, in the step of etching the insulating film 27, etching may be performed until the second layer wiring 26 is exposed at the bottom of the opening 32,
Even if the insulating film 36 slightly remains on the insulating film 35, no particular adverse effect is exerted.

Next, a conductive barrier film 39a made of the same material as the conductive barrier film 26a, for example, titanium nitride is formed on the entire main surface of the substrate 1 by a sputtering method or the like. Then, the opening 32 is formed on the conductive barrier film 39a.
A main conductor film 39b made of copper is formed in the same manner as the main conductor film 26b so as to fill the opening 38.

Next, the main conductor film 39b and the conductive barrier film 3 are formed.
9a is polished by CMP until the upper surface of the insulating film 35 is exposed. As a result, as shown in FIG.
Third layer wiring (wiring) 39 is formed in the openings 32 and 38. The third-layer wiring 39 has a relatively thin conductive barrier film 39a and a relatively thick main conductor film 39b, and is electrically connected to the second-layer wiring 26. In addition,
The opening 38 corresponds to a wiring groove, and the opening 32 corresponds to a hole for connecting the upper layer wiring (third layer wiring 39) and the lower layer wiring (second layer wiring 26). Therefore, the conductor portion embedded in the opening 38 corresponds to the wiring portion, and the opening 38
The conductor portion embedded in corresponds to the plug portion.

Thereafter, the same steps as the steps after the formation of the second layer wiring 26 (that is, the steps of FIGS. 7 to 16) can be repeated as necessary to form the upper layer wirings after the fourth layer wiring. For example, an insulating film that functions as a barrier insulating film similarly to the insulating film 27 is formed on the insulating film 35 including the upper surface of the third-layer wiring 39, and a low-K material is formed thereon similarly to the insulating film 28. Forming an interlayer insulating film.

In this embodiment, the insulating film 36 is formed on the insulating film 35. Therefore, the insulating film 35 is hardly etched by the etching process of the insulating film 33 and the insulating film 28 and the etching process of the insulating film 27, so that the above-mentioned shoulder scraping does not occur in the insulating film 35. Therefore,
When the conductive barrier film 39a and the main conductor film 39b are embedded in the openings 32 and 38, unnecessary conductor portions are not embedded in the vicinity of the upper ends of the openings 38, and unnecessary conductor portions remain after polishing by the CMP method. Nor. As a result, the dielectric breakdown resistance between adjacent wirings of the same layer wiring can be improved. It is also possible to reduce the design value of the distance between adjacent wirings of the same layer wiring.

Further, in this embodiment, the insulating films 20, 2
Although the Low-K material was used as 8 and 33, the method for manufacturing the semiconductor device of the present embodiment is used when the low-k material is weak and is damaged by an oxidizing plasma treatment such as oxygen (O ₂ ) plasma treatment and is damaged. Is more preferable. Examples of the low dielectric constant material that is weak against oxidizing plasma treatment include, for example, the above organic polymer-based low dielectric constant material (SiL).
K (manufactured by The Dow Chemical Co., USA) etc. Further, even if a low dielectric constant material other than the organic polymer low dielectric constant material is used, a low dielectric constant material having a large etching selection ratio with respect to silicon oxide and weak against oxidizing plasma treatment such as O ₂ ashing is used. In that case, it is extremely effective to apply the method for manufacturing a semiconductor device of the present embodiment.

Further, in the present embodiment, the conductive barrier film 39a and the main conductor film 39b are buried in the wiring groove formed of the openings 32 and 38 with the insulating films 34 and 35 remaining, so that the third layer wiring 39 is formed. Formed. However,
The insulating films 34 and 35 may be finally removed. For example, after the process of FIG. 15, the insulating films 34 and 35 are formed.
Can be removed, and thereafter, the conductive barrier film 39a and the main conductor film 39b can be embedded in the wiring groove formed of the openings 32 and 38 to form the third-layer wiring 39. Alternatively, after forming the conductive barrier film 39a and the main conductor film 39b after the step of FIG. 15 and polishing the conductive barrier film 39a and the main conductor film 39b by the CMP method, until the insulating film 33 is exposed ( That is, polishing can be performed until the insulating films 34 and 35 are removed.

(Embodiment 2) FIGS. 17 to 25 are cross-sectional views of essential parts in the manufacturing process of a semiconductor device according to another embodiment of the present invention. The manufacturing process up to FIG. 7 is the same as in the first embodiment.
The description is omitted here, and the manufacturing process following FIG. 7 will be described.

As shown in FIG. 17, insulating films 27, 2
After sequentially forming 8, 29 and 30, in the present embodiment, the antireflection film 31a and the photoresist pattern 3 are formed.
The insulating film 33 is formed on the insulating film 30 without forming 1b.
34, 35 and 36 are formed in order. Insulation film 27-3
The materials and functions of Nos. 0 and 33 to 36 are almost the same as those of the first embodiment, and therefore the description thereof is omitted here. Further, in the present embodiment, the insulating films 29 and 30 may be single-layer insulating films, for example, a single film of silicon nitride, silicon carbide or silicon carbonitride.

Next, an antireflection film 50a is formed on the insulating film 36. Then, a photoresist film is formed on the antireflection film 50a, and the photoresist film is patterned by exposure to form a photoresist pattern 50b. As a result, the structure shown in FIG. 17 is obtained.

Next, as shown in FIG. 18, the antireflection film 50a is selectively removed by a dry etching method using the photoresist pattern 50b as an etching mask, and then a dry process using the photoresist pattern 50b as an etching mask is performed. The insulating film 36 is selectively removed by an etching method to form the opening 51. In the step of forming the opening 51, the insulating film 35 functions as an etching stopper. After that, the remaining photoresist pattern 5
0b and the antireflection film 50a are removed by ashing or the like.

Next, as shown in FIG. 19, the opening 5
An antireflection film 52a is formed on the insulating film 36 so as to fill the inside of the film 1. Then, a photoresist film is formed on the antireflection film 52a, and the photoresist film is patterned by exposure to form a photoresist pattern 52b.

Next, as shown in FIG. 20, the antireflection film 52a is selectively removed by a dry etching method using the photoresist pattern 52b as an etching mask. Then, the insulating films 34 and 35 are selectively removed by dry etching using the photoresist pattern 52b as an etching mask to form an opening 53, and the insulating film 33 is exposed at the bottom of the opening 53. In addition,
The plane area of the opening 53 exists in the plane area of the opening 51.

Next, as shown in FIG. 21, by NH ₃ plasma treatment or N ₂ / H ₂ plasma treatment,
While etching the insulating film 33 exposed from the opening 53, the photoresist pattern 52b and the antireflection film 5 are formed.
2a is removed by ashing. At this time, the insulating film 30
Functions as an etching stopper.

Next, as shown in FIG. 22, the opening 5
The insulating film 30 exposed at the bottom of 3 is removed by a dry etching method or the like. At this time, the insulating film 35 exposed from the opening 51 is also removed, and the insulating film 34 is removed from the opening 51.
Is exposed. Then, the insulating film 29 exposed at the bottom of the opening 53 and the insulating film 34 exposed at the opening 51 are removed by a dry etching method or the like to expose the insulating film 28 at the bottom of the opening 53, and The insulating film 33 is exposed from 51. At this time, the insulating film 36 is also etched, but since the insulating film 36 is thicker than the insulating films 29 and 34, the insulating film 36 only becomes thin and remains on the insulating film 35.

Next, as shown in FIG. 23, the opening 5
The insulating film 28 exposed from 3 and the insulating film 33 exposed from the opening 51 are etched by NH ₃ plasma treatment or N ₂ / H ₂ plasma treatment. At this time, the insulating film 36 functions as an etching mask, and the insulating film 27
And 30 function as etching stoppers.

Next, as shown in FIG. 24, the opening 5
The insulating film 27 exposed at the bottom of 3 is removed by a dry etching method or the like to expose the second layer wiring 26 at the bottom of the opening 53. At this time, the insulating film 36 can also be removed.

Next, a conductive barrier film 39a made of, for example, titanium nitride is formed on the entire main surface of the substrate 1 by a sputtering method or the like. Then, the conductive barrier film 39a
A main conductor film 39b made of copper is formed thereover so as to fill the openings 51 and 53.

Next, the main conductor film 39b and the conductive barrier film 39a are polished by CMP until the upper surface of the insulating film 35 is exposed. Thus, as shown in FIG. 25, the third layer wiring (wiring) 39 is formed in the wiring groove formed of the openings 51 and 53. The third-layer wiring 39 has a relatively thin conductive barrier film 39a and a relatively thick main conductor film 39b, and is electrically connected to the second-layer wiring 26.

Subsequent manufacturing steps are the same as those in the first embodiment.
Since it is similar to the above, the description thereof will be omitted.

In this embodiment, etching is performed without a photoresist pattern in the steps of FIGS. For this reason, the uppermost insulating film 36 is etched by these etching steps, and the upper corners of the opening are shaved and rounded. That is, shoulder scraping occurs. However, the insulating film 36 in which the shoulder is shaved is
Since the insulating film 27 is removed in the etching step, the shoulder of the exposed insulating film 35 is considerably small. Therefore, when the conductive barrier film 39a and the main conductor film 39b are embedded in the openings 51 and 53, unnecessary conductor portions are left in the openings 5.
Nothing is buried in the vicinity of the upper end of 1 and almost no unnecessary conductor portion remains after polishing by the CMP method. As a result, the dielectric breakdown resistance between adjacent wirings of the same layer wiring can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

In the above embodiments, the semiconductor device having the CMISFET has been described, but the present invention is not limited to this, and various semiconductor devices having wirings containing a main conductor film containing copper as a main component. Can be applied to.

[0090]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

The dielectric breakdown resistance between adjacent wirings can be improved.

A buried wiring can be formed without scraping the upper corners of the wiring groove.

[Brief description of drawings]

FIG. 1 is a plan view of a principal part during a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA of FIG.

FIG. 3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

6 is a main-portion plan view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG.

7 is a cross-sectional view taken along the line AA of FIG.

8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

9 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;

10 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 9;

11 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 13 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;

FIG. 14 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 13;

15 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

16 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 17 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 18 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 17;

FIG. 19 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;

FIG. 20 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 19;

FIG. 21 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 20;

FIG. 22 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 21;

FIG. 23 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 22;

FIG. 24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23;

25 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 24.

[Explanation of symbols]

1 semiconductor substrate 2 isolation region 3 p-type well 4 n-type well 5 n-channel type MISFET 6 p-channel type MISFET 7 gate insulating film 8 the gate electrode 9 side wall 10a n ^- -type semiconductor region 10b n ⁺ -type semiconductor region 11a p ^- Type semiconductor region 11b p ⁺ type semiconductor region 12 Insulating film 13 Contact hole 14 Plug 14a Titanium nitride film 15 First layer wiring 16, 17 Insulating film 18 Through hole 19 Plug 20-23 Insulating film 24a Antireflection film 24b Photoresist pattern 25 Opening 26 Second layer wiring 26a Conductive barrier film 26b Main conductor film 27-30 Insulating film 31a Antireflection film 31b Photoresist pattern 32 Opening 33-36 Insulation film 37a Antireflection film 37b Photoresist pattern 38 Opening 39th Three-layer wiring 39a Conductive barrier film 39 Main conductive film 50a antireflection film 50b photoresist pattern 51 opening 52a antireflection film 52b photoresist pattern 53 opening

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroyuki Maruyama             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center (72) Inventor Naofumi Ohashi             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F term (reference) 5F033 HH08 HH09 HH18 HH19 HH33                       JJ11 JJ18 JJ19 JJ21 JJ23                       JJ32 JJ33 JJ34 KK01 KK08                       KK09 KK11 KK18 KK19 KK21                       KK23 KK32 KK33 KK34 MM02                       MM05 MM12 MM13 NN05 NN06                       PP06 QQ00 QQ04 QQ09 QQ28                       QQ31 QQ37 QQ48 QQ90 RR01                       RR06 RR08 RR11 RR15 RR21                       RR25 RR29 SS01 SS03 SS11                       SS15 SS21 TT02 TT04 XX24

Claims (20)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; c) a step of forming a second insulating film made of a low dielectric constant material on the first insulating film, (d) a step of forming a third insulating film on the second insulating film, (e) ) Forming a fourth insulating film on the third insulating film, (f) Forming a mask pattern on the fourth insulating film, (g) Using the mask pattern as an etching mask, Selectively removing the fourth insulating film to form a first opening, (h) removing the third insulating film exposed from the first opening, (i) the first insulating film A step of removing the second insulating film exposed from the first opening and the mask pattern;
(J) A step of forming wiring in the first opening. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the fourth insulating film after the step (i). 3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (i), the second insulating film is etched and the mask pattern is removed by a reducing plasma treatment. And a method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the mask pattern includes a photoresist pattern. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is made of a material that is weak against an oxidizing plasma treatment. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is made of a silicon oxide film. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth insulating film is made of a silicon nitride film, a silicon carbide film, a silicon carbonitride film or a silicon oxynitride film. Device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (c), a step of forming a fifth insulating film on the second insulating film without using oxidizing plasma, In the step (d), the third insulating film is formed on the fifth insulating film. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring contains copper as a main component. 10. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (j), copper diffusion is suppressed over the entire surface of the semiconductor substrate including the bottom and sidewall of the first opening. Or a step of forming a first conductor film having a preventing function, and forming a second conductor film containing copper as a main component on the first conductor film so as to fill the first opening. A step, wherein the first and second conductor films in the first opening are left and the other first and second conductor films are removed so that the first and second conductor films are removed. And a step of polishing the semiconductor device. 11. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; c) a step of forming a second insulating film made of a low dielectric constant material on the first insulating film, (d) a step of forming a third insulating film on the second insulating film, (e) ) Forming a fourth insulating film on the third insulating film, (f) Forming a first mask pattern on the fourth insulating film, (g) Forming the first mask pattern Selectively removing the fourth insulating film by using as an etching mask to form a first opening, (h) removing the first mask pattern,
(I) a step of removing the third insulating film exposed from the first opening, and (j) a fifth insulating film made of a low dielectric constant material so as to fill the first opening. Forming a fourth insulating film, (k) forming a sixth insulating film on the fifth insulating film, (l) forming a seventh insulating film on the sixth insulating film And (m) forming a second mask pattern on the seventh insulating film, and (n) selectively removing the seventh insulating film by using the second mask pattern as an etching mask. To form a second opening, (o) removing the sixth insulating film exposed from the second opening, (p) the fifth exposed from the second opening Removing the insulating film of
Removing the second insulating film exposed from the first opening at the bottom of the opening, and removing the second mask pattern, (q) the first opening and the second Forming wiring in the opening of the. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of removing the seventh insulating film after the step (p). 13. The method of manufacturing a semiconductor device according to claim 11, wherein after the step (p), the seventh insulating film and the first insulating film exposed from the first opening are removed. A method of manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (p), the fifth insulating film and the second insulating film are etched by a reducing plasma treatment and the second insulating film is etched. 2. A method for manufacturing a semiconductor device, wherein the mask pattern 2 is removed. 15. The method of manufacturing a semiconductor device according to claim 11, wherein the first and second mask patterns include a photoresist pattern. 16. The method of manufacturing a semiconductor device according to claim 11, wherein the second insulating film and the fifth insulating film are made of a material weak against oxidizing plasma treatment. Method. 17. The method of manufacturing a semiconductor device according to claim 11, wherein after the step (j), an eighth insulating film is formed on the fifth insulating film without using oxidizing plasma. In the step (k), the sixth insulating film is formed on the eighth insulating film. 18. The method of manufacturing a semiconductor device according to claim 11, wherein the wiring contains copper as a main component. 19. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; c) a step of forming a second insulating film made of a low dielectric constant material on the first insulating film, (d) a step of forming a third insulating film on the second insulating film, (e) ) Forming a fourth insulating film made of a low dielectric constant material on the third insulating film, (f) Forming a fifth insulating film on the fourth insulating film, (g)
Forming a sixth insulating film on the fifth insulating film;
(H) a step of forming a first mask pattern on the sixth insulating film, (i) a step of selectively removing the sixth insulating film using the first mask pattern as an etching mask, and No. 1 opening, (j) removing the first mask pattern, and (k) forming a mask layer on the sixth insulating film so as to fill the first opening. And (l) patterning the mask layer to form a second mask pattern, (m) using the second mask pattern as an etching mask, and exposing the bottom of the first opening. Removing a part of the fifth insulating film to form a second opening in the first opening, (n) the fourth opening exposed from the second opening
Removing the insulating film and the second mask pattern, (o) the third insulating film exposed from the second opening and the fifth insulating exposed from the first opening. And (p) removing the second insulating film exposed from the second opening and the fourth insulating film exposed from the first opening, (p) Removing the sixth insulating film and the first insulating film exposed from the second opening, and (r) forming wiring in the first opening and the second opening. . 20. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (n), the fourth insulating film is etched and the second mask pattern is removed by a reducing plasma treatment. A method of manufacturing a semiconductor device, comprising: