JP2003330881A - Data transfer system and signal timing correction method thereof - Google Patents

Abstract

(57) Abstract: Provided is a data transfer system and a signal timing correction method capable of correcting received data so as not to cause an error even when a timing violation of a strobe signal or a data signal occurs. A host computer (1) includes test data output means (13) for outputting a data signal of test data to a data line (3), and a receiving side device (2) outputs data signals after a strobe signal is asserted. The delay amount setting means 20 for setting a delay time until the data is latched, the received data output by latching the data signal of the test data by the data latch means 17 are compared with the test data, and the two match. If not, the delay time is increased by a predetermined time by the delay amount setting means 20 and the test data output means 1
3 for outputting a test data output request signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system and a signal timing correction method therefor capable of correcting a received data error even when a timing violation of a strobe signal or a data signal occurs in a communication interface. It is about.

[0002]

2. Description of the Related Art Conventionally, as a data transfer system for transferring print data between a personal computer or a workstation and a printer, a system using a parallel interface for asynchronously transferring data by a handshake method is often used. Has been done. In such a data transfer system using a parallel interface, a data bus line and a strobe (nS) are provided between a transmission side device such as a personal computer and a reception side device such as a printer.
Data transfer is performed by the 3-line handshake using the 3-line status line of the probe line, the busy line, and the ac (nAck) line.

FIG. 5 is a timing chart of signals on a data line and a status line of a data transfer system using a conventional parallel interface.

In FIG. 5, the horizontal axis represents time and the vertical axis represents voltage. (A) shows the data bus line (D
data1 to Data8), (b) represents a data signal output to a data bus line when a timing violation occurs, and (c) represents a signal output to a strobe line. (D) represents a busy signal output to the busy line. Also, T
_setup is the time from the output of the data signal to the assertion of the strobe signal (data setup time), and T _hold is the time from the negation of the strobe signal to the switching of the data signal (data hold time). Is.

In a normal state, as shown in FIG.
As shown in (c) and (d), when the transmission side device switches the data signal, the transmission side device has a constant data setup time T.
_The strobe signal is asserted when _setup has elapsed. This setup time is set so that a noise signal such as ringing generated at the time of switching the data signal or a reflection on the transmission line is sufficiently attenuated and an error in the received data does not occur. When the strobe signal is asserted, the receiving side device latches the data signal and outputs the latched data signal as received data. In addition, the receiving side device asserts the busy signal while the data signal is latched, the received data is output, and other processing relating to the received data is performed. The transmitting device negates the strobe signal when the busy signal is asserted. In this way, the data transfer system performs asynchronous data transfer by the handshake method.

[0006]

However, the positional relationship between the strobe signal and the data signal may deviate depending on the characteristics of the transmitting side device, the receiving side device, and the cable connecting the two devices, which may cause a timing violation. .

FIGS. 5 (b), 5 (c) and 5 (d) show the case where a timing violation occurs. In this case, the transmission side device asserts the strobe signal immediately before the data signal is switched. Therefore, the reception side device latches the data signal before or during the switching of the data signal and outputs the data signal as received data. Therefore, in this case, an error occurs in the received data. For example, if the receiving device is a printer, erroneous printing may occur or the printing operation may stop. The conventional data described above has a drawback in that it is impossible to prevent an error in the received data that occurs when such a timing violation of the strobe signal or the data signal occurs.

Therefore, the present invention solves the above-mentioned conventional problems, and data transfer that can be corrected so that an error in received data does not occur even if a timing violation of a strobe signal or a data signal occurs in a communication interface. An object of the present invention is to provide a system and a signal timing correction method thereof.

[0009]

In order to solve the above problems, the data transfer system of the present invention transmits a data line for transmitting a data signal and a strobe signal indicating that the data signal is available. A strobe line and a receiving side device connected by an interface having a control line, the transmitting side device outputting the data signal to the data line; When the data signal is output to the data line, a strobe signal output means for asserting the strobe signal of the strobe line is provided, and the receiving-side device, within a period in which the strobe signal is asserted, Data latch means for latching the data signal of the data line and outputting it as received data In the data transfer system, the transmission side device generates the test data and outputs the data when a test data output request signal requesting output of test data having a predetermined bit pattern is input. Means for outputting a data signal of the test data to the data line by means of the means, wherein the receiving side device is configured such that the data latch means operates after the strobe signal of the strobe line is asserted. A delay amount setting means for setting a delay time until a signal is latched, a bit pattern of received data output by the data latch means latching a data signal of the test data output to the data line, and Compare with the bit pattern of the test data and check that they match. If not, the delay amount setting means increases the delay time by a predetermined time, and the delay time adjusting means outputs a test data output request signal to the test data output means through the control line. It is characterized by doing.

With this configuration, it is possible to provide a data transfer system capable of performing correction so that an error in received data does not occur even if a timing violation of a strobe signal or a data signal occurs in a communication interface.

The signal timing correction method for a data transfer system according to the present invention comprises a data line for transmitting a data signal, a strobe line for transmitting a strobe signal indicating that the data signal is available, and a control. A transmission side device and a reception side device which are connected by a data line, the transmission side device outputs the data signal to the data line, and the data signal is output to the data line. The strobe signal output means for asserting or negating the strobe signal of the strobe line when the strobe signal is asserted. Data having a data latch means for latching and outputting as received data In the transmission system, there is provided a signal timing correction method for correcting a timing at which the data latch means latches a data signal, when a test data output request signal requesting output of test data having a predetermined bit pattern is input. A test data output step in which the transmission side device generates the test data and outputs a data signal of the test data to the data line by the data output means, and a predetermined delay time after the strobe signal is asserted. When the time elapses, the data latching means latches the data signal of the test data output to the data line and outputs it as received data, and the receiving side device sets the bit of the received data. Compare the pattern with the bit pattern of the test data Then, when the two do not match, the delay time is increased by a predetermined time, and a delay time adjusting step of outputting a test data output request signal to the transmitting side device through the control line is performed. It is characterized by having.

With this configuration, it is possible to provide a signal timing correction method for a data transfer system which can correct a received data error even if a timing violation of a strobe signal or a data signal occurs in a communication interface. it can.

[0013]

A data transfer system according to claim 1 of the present invention includes a data line for transmitting a data signal and a strobe line for transmitting a strobe signal indicating that the data signal is available. , A transmission side device and a reception side device connected by an interface having a control line, and the transmission side device outputs a data signal to the data line and a data signal output to the data line. When the strobe signal is asserted, the strobe signal output means for asserting the strobe signal of the strobe line is provided, and the receiving side device latches the data signal of the data line and outputs it as the reception data within the period in which the strobe signal is asserted. The data transfer system is provided with a data latch means for A test data output means for generating test data and outputting the data signal of the test data to the data line by the data output means when the test data output request signal for requesting the output of the test data consisting of the pattern is inputted. The receiving side device has a delay amount setting means for setting a delay time from the assertion of the strobe signal of the strobe line to the latching of the data signal of the data line by the data latch means, and the test data output to the data line. The bit pattern of the received data output by latching the data signal by the data latch means is compared with the bit pattern of the test data. If they do not match, the delay amount setting means determines the delay time. The test data through the control line. And it is characterized in that it comprises a delay time adjustment means to the output means for outputting the test data output request signal. With this configuration, the following effects can be obtained.

Usually, after the data output means outputs the data signal to the data line, in order to remove the influence of the interference noise due to the switching of the data signal of the data line, the strobe signal output means has a predetermined time (hereinafter, Assume strobe signal after "data setup time") has elapsed. Then, the data latch means receives the data signal transmitted from the data output means by latching the data signal within the period in which the strobe signal is asserted, and outputs it as received data. On the other hand, the strobe signal output means or the data output means causes a timing violation due to the positional relationship between the strobe signal and the data signal being shifted due to the characteristics of the cable connecting the transmitting side device, the receiving side device, and both devices. If the strobe signal is asserted before the output means outputs the data signal to the data line or when the influence of the interfering noise on the data signal of the data line is not sufficiently reduced, the data latch means may be activated after the strobe signal is asserted. If the data signal of the data line is immediately latched, incorrect data may be latched and a reception error may occur.

In such a case, when a test data output request signal is input to the test data output means by a user's instruction or the like, the test data output means generates test data, and the data output means outputs the data line. The data signal of the test data is output to. When the data signal is output, the strobe signal output means asserts the strobe signal. When the strobe signal is asserted, the data latch means latches the data signal and outputs the received data. At this time, if the strobe signal is asserted too early, the data may not be output sufficiently before the data signal is output to the data line or immediately after the data signal is switched, when the disturbing noise such as ringing is not sufficiently small. Since the signal is latched, the bit pattern of the received data and the bit pattern of the test data do not match. In this case, the delay time adjusting means increases the delay time by the delay amount setting means by a predetermined time and outputs the test data output request signal to the test data output means through the control line. Upon receiving the test data output request signal, the test data output means generates test data again and outputs the data signal of the test data to the data line. In this way, the above-described operation is repeated until the bit pattern of the received data matches the bit pattern of the test data, and the delay time is extended by a predetermined time. When the bit pattern of the received data and the bit pattern of the test data match, the delay amount setting means ends the operation and the appropriate delay time is set.

Here, the "transmission side device" means a device on the side of transmitting data, and for example, a personal computer or a workstation is used. "Reception side device" means a device on the side of receiving data, for example,
Printers, facsimiles, etc. are used. The “interface” is not particularly limited as long as it has a data line, a strobe line, and a control line, and specifically, for example, IEEE1
A parallel interface defined by H.284 or an interface conforming to this is used. "test data"
The term "data" is used to adjust the delay time from when the strobe signal is asserted to when the data latch means latches the data signal. The "predetermined bit pattern" constituting the test data is not particularly limited, but it is preferable to use a pattern that maximizes the margin of the latch timing of the data latch means after the adjustment of the delay time. . Specifically, a bit pattern in which data signals frequently change, for example, a pattern such as "0101" in which data signals are changed bit by bit and the influence of ringing is likely to be large is used. It should be noted that this test data is predetermined between the transmission side device and the reception side device. Also, "Test data output request signal"
Is a signal that requests the test data output means to output test data. "Assert a strobe signal" means validating a strobe signal and logic. When an H-active strobe signal is asserted, it becomes a digital H level, and when an L-active strobe signal is asserted, it becomes a digital L level. Become. Further, "to negate the strobe signal" means that the strobe signal and the logic become invalid.

The invention according to claim 2 is the data transfer system according to claim 1, wherein the delay time adjusting means comprises:
The minimum value of an appropriate delay time at which the bit pattern of the received data output by the data latch means latching the data signal of the test data output to the data line by the test data output means and the bit pattern of the test data match And a maximum value and a timing margin maximizing means for setting an average value of the minimum value and the maximum value of the proper delay times determined by the margin determining means as the delay time by the delay amount setting means. It consists of and.

With this configuration, the timing margin determining means determines the minimum value and the maximum value of the appropriate delay time,
The timing margin maximizing means obtains an average value of the minimum value and the maximum value of the appropriate delay time, and sets this average value as the delay time. This makes it possible to set a delay time that maximizes the timing margin for the data latch means to latch the data signal at an appropriate timing, and even if the timing of asserting the strobe signal is accidentally deviated, It is possible to minimize the probability of data error.

Here, the "average value" means 1/2 of the sum of the minimum value t _max and the maximum value of the appropriate delay time t _min .
Here, when the delay time can be set only by discrete values (for example, when it can be set only for each one clock of the system clock of the receiving side device), the “average value” is [(t _min + t _max ) / 2] (however, [] is a Gaussian symbol).

The invention according to a third aspect is the data transfer system according to the second aspect, wherein the receiving side device is such that the timing margin determining means cannot detect an appropriate minimum value of the delay time or an appropriate delay. When the difference between the minimum value and the maximum value of time is less than or equal to a predetermined threshold value, a transfer mode change request means for outputting a transfer mode change request signal to the control line is provided, and the transmission side device transfers to the control line. When the mode change request signal is output, the data output means is provided with transfer mode changing means for changing the transfer mode to a transfer mode different from the current transfer mode. As a result, the following effects are obtained.

For example, when the data latch means cannot latch the data signal at an appropriate timing even if the delay time is adjusted due to ringing occurring in the data line when the data signal is switched, the timing margin determining means is , The proper minimum delay time cannot be detected. Further, when the timing margin for the data latch means to latch the data signal at the proper timing is narrower than the predetermined threshold value, the data latch means outputs erroneous reception data, and a reception error is likely to occur. In such cases,
The transfer mode change request means of the receiving side device outputs a transfer mode change request signal to the control line. The transfer mode changing means of the transmitting side device changes the current transfer mode to a transfer mode different from the current transfer mode. This allows
It is possible to eliminate the error in the received data caused by the improper transfer mode.

Here, the "predetermined threshold value" is experimentally determined so that the error rate of the received data becomes lower than the compensation value of the receiving side device. The "transfer mode different from the current transfer mode" is not particularly limited,
Generally, the transfer mode is set to a data transfer speed slower than the data transfer speed of the current transfer mode. Specifically, for example, IEEE1284 is used as the interface.
If the current transfer mode is the ECP mode or the EPP mode when using the parallel interface defined in Section 2, "Transfer mode different from the current transfer mode"
Compatible mode is used as. Further, as a method for the transmission side device to change the transfer mode, when the transmission mode change request signal is received, the transmission side device may change the transfer mode in a predetermined order, or the transmission side device may display a display screen such as a display. A message prompting the user to change the transfer mode may be displayed above, and the transfer mode may be changed by the user's selection.

According to a fourth aspect of the present invention, in the data transfer system according to the second aspect, the receiving side device has a predetermined difference between the minimum value and the maximum value of the proper delay time detected by the timing margin determining means. When it is less than or equal to the threshold value, it is provided with transfer rate change requesting means for outputting the transfer rate change request signal to the control line, and the transmitting side device outputs the data output means in accordance with the transfer rate change request signal output to the control line. It is characterized in that it is provided with a transfer rate changing means for slowing down the data transfer rate, and with this configuration, the following effects can be obtained.

The timing margin determining means changes the delay time from the assertion of the strobe signal until the data latch means latches the data signal, and receives the test signal output to the data line by the test data output means, By comparing the received data output from the data latch means and the test data, the minimum value and the maximum value of the appropriate delay time are obtained, and the difference (margin width) between them is obtained. When the margin width is less than or equal to the predetermined threshold value, the transfer rate change requesting means outputs a transfer rate change request signal to the control line. Upon receiving the transfer rate change request signal, the transfer rate changing means slows down the data transfer rate of the data output means. As a result, the margin width can be widened, so that it is possible to prevent the data latching means from latching the data signal at the wrong timing and outputting the wrong received data.

Here, the "predetermined threshold value" is experimentally determined so that the error rate of the received data becomes lower than the compensation value of the receiving side device. The “transfer rate change request signal” refers to a signal from the receiving device side to the transmitting device side, which requests to change the transfer rate of the data output to the data line. As a method for the transmission side device to change the transfer rate, when the transfer rate change request signal is received, the transfer rate is decreased by a predetermined value.
Information on the difference (margin width) between the minimum value and the maximum value of the appropriate delay time is also included in the transfer rate change request signal, and a predetermined calculation formula (eg, margin width) is used based on the size of the margin width. (The transfer speed is reduced in proportion to
Is used to determine and change the transfer rate.

According to a fifth aspect of the present invention, there is provided a signal timing correction method for a data transfer system, comprising a data line for transmitting a data signal and a strobe line for transmitting a strobe signal indicating that the data signal is available. And a transmission side device and a reception side device connected by a control line, the transmission side device is a data output means for outputting a data signal to the data line, and a data signal is output to the data line. When the strobe signal is asserted or negated, the receiving side device latches the data signal of the data line and receives it as received data while the strobe signal is asserted. In a data transfer system having a data latch means for outputting, a data latch A signal timing correction method for correcting the timing at which a stage latches a data signal, wherein when a test data output request signal requesting output of test data having a predetermined bit pattern is input, At the test data output step of generating the data and outputting the data signal of the test data to the data line by the data output means, and when the predetermined delay time elapses after the strobe signal is asserted, the data latch means changes the data line to the data line. The data receiving step of latching the data signal of the test data output to and outputting it as received data and the receiving side device compare the bit pattern of the received data with the bit pattern of the test data, and the two match. If not, the delay time is increased by the specified time and the control It is characterized in that it has a delay time adjustment step of outputting test data output request signal to the transmission side apparatus through a line.

With this configuration, first, the strobe signal or the data signal shifts in the positional relationship between the strobe signal and the data signal due to, for example, the characteristics of the transmitting side device, the receiving side device, and the cable connecting the both devices. When the strobe signal is asserted before the data output means outputs the data signal to the data line or when the influence of the interfering noise on the data signal of the data line is not sufficiently reduced, the user's instruction etc. When a test data output request signal is input to the transmission side device, the transmission side device generates test data, and the data output means outputs the data signal of the test data to the data line. At this time, the strobe signal output means asserts the strobe signal. The data latch means latches the data signal of the data line and outputs the received data after a predetermined delay time has elapsed since the strobe signal was asserted. At this time, if the received data does not match the test data, the receiving side device increases the delay time by a predetermined time and outputs a test data output request signal to the transmitting side device through the control line. When the test data output request signal is input, the transmission side device repeats the same operation as the above operation. Then, when the received data finally matches the test data, the series of operations is completed. in this way,
By adjusting the delay time using test data,
It can be adjusted so that the data latch means can latch the data signal at an appropriate timing. Therefore, even when the strobe signal or the data signal transmitted from the transmission side device causes a timing violation, it is possible to prevent an error in the received data.

A sixth aspect of the present invention is the signal timing correction method for a data transfer system according to the fifth aspect, wherein the receiving side device outputs the data of the test data output to the data line by the test data output means. A timing margin determining step of determining a minimum value and a maximum value of an appropriate delay time at which the bit pattern of the received data output by latching the signal by the data latch means and the bit pattern of the test data match; The apparatus has a timing margin maximizing step of setting, as a delay time, an average value of the minimum value and the maximum value of the appropriate delay times determined in the margin determining step.

With this configuration, the delay time can be set to an appropriate average value of the minimum value and the maximum value of the delay time, and the margin of the timing at which the data latch means latches the data signal can be maximized. It will be possible. Therefore, even if the timing of asserting the strobe signal is accidentally deviated, it is possible to minimize the probability that an error occurs in the received data.

The invention according to claim 7 is the signal timing correction method for a data transfer system according to claim 6, wherein in the timing margin determining step, an appropriate minimum value of the delay time cannot be detected or an appropriate delay time is detected. When the difference between the minimum value and the maximum value of the delay time is less than or equal to a predetermined threshold value, the receiving side device outputs a transfer mode change request signal to the control line, and a transfer mode change request step to the control line. When the change request signal is output,
The transmission side device has a transfer mode changing step of changing the transfer mode of the data output means to a transfer mode different from the current transfer mode.

With this configuration, for example, due to ringing generated in the data line when the data signal is switched,
If the data latching means cannot latch the data signal at proper timing even if the delay time is adjusted,
The timing margin for the data latch means to latch the data signal at the proper timing is narrower than the predetermined threshold value, and the data latch means outputs erroneous received data,
When a reception error is likely to occur, it is possible to prevent the reception error by switching the transfer mode of the transmission side device.

The invention according to claim 8 is the signal timing correction method for a data transfer system according to claim 6, wherein the difference between the minimum value and the maximum value of the appropriate delay time detected in the timing margin determining step. Is less than or equal to a predetermined threshold value, the receiving side device, a transfer rate change request step of outputting a transfer rate change request signal to the control line,
According to the transfer rate change request signal output to the control line, the transmission side device has a transfer rate changing step of slowing the data transfer rate of the data output means.

With this configuration, first, the timing margin determining means changes the delay time from the assertion of the strobe signal until the data latch means latches the data signal, and the test data output means outputs it to the data line. By receiving the test signal and comparing the received data output from the data latch means with the test data, the minimum value and the maximum value of the appropriate delay time are obtained, and the difference (margin width) between them is obtained. When the margin width is less than or equal to the predetermined threshold, the transfer rate change requesting means
The transfer rate change request signal is output to the control line. When the transfer rate change means receives the transfer rate change request signal,
The data transfer speed of the data output means is reduced. As a result, the margin width can be widened, so that it is possible to prevent the data latching means from latching the data signal at the wrong timing and outputting the wrong received data.

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) A data transfer system according to the present embodiment includes a data line for transmitting a data signal, a strobe line for transmitting a strobe signal indicating that the data signal is available, and a control. A transmission side device and a reception side device connected by an interface having a data line, and the transmission side device outputs a data signal to the data line, and a data signal is output to the data line. When the strobe signal output means for asserting the strobe signal of the strobe line is provided, the receiving side device latches the data signal of the data line and outputs it as the received data during the period when the strobe signal is asserted. A data transfer system comprising a latch means, wherein Test data output means for generating test data when a test data output request signal for requesting output of test data consisting of a test pattern is input, and outputting the data signal of the test data to the data line by the data output means; And a transfer mode changing means for changing the transfer mode of the data output means to a transfer mode different from the current transfer mode when the transfer mode change request signal is output to the strobe line. Delay amount setting means for setting the delay time from the assertion of the strobe signal of 1 to the data latch means latching the data signal of the data line, and the data latch means latches the data signal of the test data output to the data line. The received data bit pattern output by If the two do not match, the delay amount setting means increases the delay time by a predetermined time, and the test data output means requests the test data output means through the control line. In the case where the delay time adjusting means for outputting a signal and the timing margin determining means cannot detect the minimum value of the appropriate delay time or the difference between the minimum value and the maximum value of the appropriate delay time is less than or equal to a predetermined threshold value,
And a transfer mode change requesting means for outputting a transfer mode change request signal to the control line.

FIG. 1 is a block diagram of a data transfer system according to an embodiment of the present invention.

Referring to FIG. 1, in the data transfer system according to the present embodiment, a host computer 1 as a transmission side device and a printer 2 as a reception side device have a data line 3, a strobe line 4 and a busy line (not shown). ), And a parallel interface (IEEE1284) having control lines 5 and 6. In addition,
Actually, lines for fault (nFault) and initial (nInit) in the parallel interface are used as the control lines 5 and 6.

The host computer 1 has a system control means 9, a data output means 10, and a strobe signal output means 1.
1, timing correction start signal output means 12, test data output means 13, and parallel interface circuit 7
Have.

The system control means 9 is a central processing unit (C
PU), memory, printer driver program, etc., and controls the entire host computer 1.
The data output circuit 10 outputs a data signal to the data line 3 via the parallel interface circuit 7. The strobe signal output means 10 asserts or negates the strobe signal output to the strobe line 4 via the parallel interface circuit 7. The strobe signal is a signal indicating that the data signal output to the data line 3 is available. The timing correction start signal output means 12 outputs the timing correction start signal to the control line 6 via the parallel interface circuit 7. The timing correction start signal is the timing of capturing the data signal of the data line after the strobe signal of the strobe line is asserted, that is, the delay time correction process from the assertion of the strobe signal to the latching of the data signal (hereinafter,
It is called the “signal timing correction process”. ) Is a signal for notifying the printer 2 from the host computer 1. The test data output unit 13 generates test data when the test data output request signal is input, and the data output unit 10 outputs the data signal of the test data to the data line 3. The test data is data having a predetermined bit pattern, and is a signal used for correcting the delay time from the assertion of the strobe signal to the latching of the data signal. The test data output request signal means a signal requesting the test data output means 13 to output test data.

The printer 2 includes a system control means 14, a data strobe signal detection means 15, a delay means 16, a data latch means 17, a received data storage means 18, a timing correction start signal detection means 19, a delay amount setting means 20, and a test. It has data comparison means 21.

The system control means 14 comprises a central processing unit (CPU), a memory, a printer control program, etc., and controls the entire printer 2. The data strobe signal detecting means 15 detects that the strobe signal input from the strobe line 4 via the parallel interface circuit 8 is asserted or negated, and outputs a strobe detection signal. When the strobe detection signal is input, the delay means 16 outputs the data latch timing signal at the time point when the strobe detection signal is input and delayed by a predetermined delay time. When the data latch timing signal is input, the data latch means 17 latches the data signal input from the data line 3 via the parallel interface circuit 8 and outputs it as received data. The reception data storage means 18 stores the input reception data.

The timing correction start signal detecting means 19 is
The timing correction start signal input from the control line 6 via the parallel interface circuit 8 is detected and notified to the system control means 14. This causes the system control means 14 to start the signal timing correction process. The delay amount setting means 20 sets and changes the delay time of the delay means 16. Test data comparison means 21
Compares the bit pattern of the received data output by the data latch means 17 latching the data signal of the test data output to the data line 3 with the bit pattern of the test data, and when they do not match. Outputs a test error signal to the system control means 14. When the test error signal is input, the system control means 14 outputs the test data output request signal to the control line 5 via the parallel interface circuit 8 and the delay amount setting means 20 causes the delay means 16 to operate.
Change the delay time of.

In the present embodiment, the delay time adjusting means is realized by the system control means 14 and the delay amount setting means 20 of the printer 2. The transfer mode change requesting means is realized by the system control means 14 of the printer 2, and the transfer mode changing means is realized by the system control means 9 of the host computer 1.

In the data transfer system of the present embodiment configured as described above, the signal timing correction method will be described below.

FIG. 2 is a flowchart showing a signal timing correction method for the data transfer system according to the first embodiment of the present invention.

In FIG. 2, first, the function selection screen is displayed on the input screen of the host computer 1 by the printer driver program of the host computer 1. When the user selects the signal timing correction function from the function selection screen (S1), the system control means 9 notifies the timing correction start signal output means 12 of the instruction,
The timing correction start signal output means 12 outputs the timing correction start signal to the control line 6 via the parallel interface circuit 7 (S2). When the timing correction start signal detection means 19 of the printer 2 receives the timing correction start signal from the control line 6 via the parallel interface circuit 8, it notifies the system control means 14 of the reception. Upon receiving the notification, the system control means 14 changes the operation mode to the calibration mode (S3). Here, the “calibration mode” refers to an operation mode in which the timing at which the data latch means 17 of the printer 2 latches the data signal is calibrated.

Next, the system control means 14 of the printer 2
Sets the delay time t _d to 0 and the internal variable Loop indicating the number of tests to 0. Then, the delay amount setting means 20 sets the delay time t _d in the delay means 16 (S
4). When the above preparation is completed, the system control means 14 of the printer 2 outputs a test data output request signal to the control line 5 via the parallel interface circuit 8 (S5). When the system control means 9 of the host computer 1 receives the test data output request signal from the control line 5 via the parallel interface circuit 7,
The test data output request signal is output to the test data output means 13.

When the test data output request signal is input to the test data output means 13, the data output means 10 outputs a test pattern to the data line 3 via the parallel interface circuit 7 (S6). At this time, the strobe signal output means 11 asserts the strobe signal of the strobe line 4.

Data strobe detecting means 1 of printer 2
When detecting that the strobe signal of strobe line 4 is asserted, 5 outputs a strobe detection signal to delay means 16. The delay means 16 outputs a data latch timing signal to the data latch means 17 at the time when the delay time set by the delay amount setting means 20 has elapsed from the time when the strobe detection signal was input. When the data latch timing signal is input, the data latch means 17 latches the data signal output to the data line 3, outputs the latched data signal to the received data storage means 18 as received data, and also the busy line ( Assert a busy signal (not shown).
The reception data storage means 18 stores the reception data input from the data latch means 17 (S7). When the busy signal on the busy line is asserted, the strobe signal output means 11 negates the strobe signal on the strobe line 4. Also, the busy signal is sent to the printer 2
It is asserted until the processing of the received data in (3) is completed, and is negated when the processing is completed.

When the data latch means 17 outputs the received data, the system control means 14 increments the internal variable Loop indicating the number of tests (S8). Next, the test data comparison unit 21 compares the bit pattern of the reception data stored in the reception data storage unit 18 with the bit pattern of the test data (S9).

If they match (S10), the test data comparison means 21 sets the current delay time t _d to the delay time t ₁ (S11), and the system control means 14
The delay amount setting means 20 causes the delay means 16 to apply the delay time t.
Set ₁ to exit calibration mode and end the signal timing correction process.

On the other hand, in step S9, when the test data comparing means 21 determines that the bit pattern of the received data stored in the received data storage means 18 and the bit pattern of the test data are different (S10), the data latch The latch timing of the means 17 is not proper.
Therefore, the system control means 14 firstly determines the internal variable Lo.
It is determined whether the value of op is greater than or equal to a predetermined limit value (S1
2). Here, the predetermined limit value is for determining the maximum value of the delay time, and is a value which is determined that the proper delay time cannot be already set when the value of the internal variable Loop becomes equal to or larger than the limit value. This limit value is determined by an experimentally obtained data transfer cycle of each transmission mode and the resolution of the delay amount setting means 20, and is determined by a value calculated by, for example, (transfer cycle) / (resolution). . If the value of the internal variable Loop is less than or equal to a predetermined limit value, the system control means 1
4 outputs a test data output request signal to the control line 5 via the parallel interface circuit 8 (S1
3), increment the value of t _d by 1 clock (S
14) and returns to the operation of step S6. That is, the delay time is increased by one clock and the delay time adjusting operation based on the test data is continued again.

In step S12, when the system control means 14 determines that the value of the internal variable Loop is equal to or larger than the predetermined limit value, it is no longer possible to set an appropriate delay time in the current transmission mode. Therefore, the system control means 14 of the printer 2 controls the control line 5 via the parallel interface circuit 8.
The transfer mode change request signal is output to (S15). The system control means 9 of the host computer 1 is a parallel
When the transfer mode change request signal is received from the control line 5 via the interface circuit 7, the current transfer mode of the host computer 1 is switched to a different transfer mode (S16). For example, when the current transfer mode is the ECP mode or the EPP mode, the mode is switched to the compatible mode having a slower data transfer rate. In this case, the system control means 9 may display an image prompting mode switching on the display screen of the display device of the host computer 1 and switch to another mode according to a user's instruction. When the mode switching as described above is completed, the operation returns to step S4 again, and the signal timing correction process is performed in the new transfer mode.

(Embodiment 2) The data transfer system according to the present embodiment includes a data line for transmitting a data signal, a strobe line for transmitting a strobe signal indicating that the data signal is available, and a control. A transmission side device and a reception side device connected by an interface having a data line, and the transmission side device outputs a data signal to the data line, and a data signal is output to the data line. When the strobe signal output means for asserting the strobe signal of the strobe line is provided, the receiving side device latches the data signal of the data line and outputs it as the received data during the period when the strobe signal is asserted. A data transfer system comprising a latch means, wherein A test data output request signal for requesting output of test data composed of a test pattern, the test data is generated, and the data output means outputs the data signal of the test data to the data line. The receiving side device outputs a delay amount setting means for setting a delay time from the assertion of the strobe signal of the strobe line until the data latch means latches the data signal of the data line, and the test data output means for outputting to the data line. A timing margin that determines the minimum value and the maximum value of the appropriate delay time at which the bit pattern of the received data output by the data latch means latching the data signal of the tested test data matches the bit pattern of the test data. The deciding means and the margin deciding means are decided And the average of the minimum and maximum values of the appropriate delay time, is characterized in that it comprises a timing margin maximization means for setting a delay time by the delay amount setting unit.

The block diagram of the data transfer system according to the present embodiment is the same as that shown in FIG. 1, and therefore its explanation is omitted. In FIG. 1, the timing margin determining means and the timing margin maximizing means are system controlled. It is realized by means 14.

FIG. 3 is a flow chart showing a signal timing correction method of the data transfer system according to the second embodiment of the present invention.

In FIG. 3, first, the function selection screen is displayed on the input screen of the host computer 1 by the printer driver program of the host computer 1. When the user selects the signal timing correction function from the function selection screen (S21), the system control means 9 notifies the timing correction start signal output means 12 of the instruction, and the timing correction start signal output means 12 causes the parallel A timing correction start signal is output to the control line 6 via the interface circuit 7 (S22). When the timing correction start signal detection means 19 of the printer 2 receives the timing correction start signal from the control line 6 via the parallel interface circuit 8, it notifies the system control means 14 of the reception. The system control means 14
When the notification is received, the operation mode is changed to the calibration mode (S23).

Next, the system control means 14 of the printer 2
Sets the delay time t _d to 0, the internal variable Loop indicating the number of tests to 0, and the internal variable Mode indicating the test mode to 0. Then, the delay time t _d is set in the delay means 16 by the quantity setting means 20 (S2).
4). Here, the test mode is to identify whether the minimum value or the maximum value of the proper delay time is currently being investigated, and when the Mode is 0, the minimum value of the proper delay time is determined. Test mode to check, Mode is 1
In the case of, it means a test mode in which the appropriate maximum delay time is checked. When the above preparation is completed, the system control means 14 of the printer 2 outputs a test data output request signal to the control line 5 via the parallel interface circuit 8 (S25). Upon receiving the test data output request signal from the control line 5 via the parallel interface circuit 7, the system control means 9 of the host computer 1 outputs the test data output request signal to the test data output means 13.

When the test data output request signal is input to the test data output means 13, the data output means 10 outputs the test pattern to the data line 3 via the parallel interface circuit 7 (S26). At this time, the strobe signal output means 11 asserts the strobe signal of the strobe line 4.

When the data strobe signal detection means 15 of the printer 2 detects that the strobe signal of the strobe line 4 is asserted, it outputs a strobe detection signal to the delay means 16. The delay unit 16 starts the delay amount setting unit 20 from the time when the strobe detection signal is input.
When the delay time set by is passed, the data latch timing signal is output to the data latch means 17. When the data latch timing signal is input, the data latch means 17 latches the data signal output to the data line 3, outputs the latched data signal to the received data storage means 18 as received data, and
Assert the busy signal on the busy line (not shown). The reception data storage means 18 is a data latch means 17.
The received data input from is stored (S27). When the busy signal on the busy line is asserted, the strobe signal output means 11 negates the strobe signal on the strobe line 4. Further, the busy signal is asserted until the processing of the received data in the printer 2 is completed, and is negated when the processing is completed.

When the data latch means 17 outputs the received data, the system control means 14 increments the internal variable Loop indicating the number of tests (S28). Next, the test data comparison unit 21 compares the bit pattern of the reception data stored in the reception data storage unit 18 with the bit pattern of the test data (S29).

If they do not match, the latch timing of the data latch means 17 is not proper. Therefore,
The system control means 14 first determines the current test mode M.
The value of the internal variable Loop is compared with a predetermined limit value (S32), and if the value of Loop is less than the predetermined limit value, the printer 2 is checked. The system control means 14 of
A test data output request signal is output to the control line 5 via the interface circuit 8 (S33), and the value of t _d is set to 1
Only the clock is incremented (S34) and the parallel
A test data output request signal is output to the control line 5 via the interface circuit 8, and the operation returns to step S26. That is, the delay time is increased by one clock and the delay time adjusting operation based on the test data is continued again.

When the system control means 14 determines in step S32 that the value of the internal variable Loop is equal to or greater than the predetermined limit value, it is no longer possible to set an appropriate delay time in the current transmission mode. Therefore, the system control means 14 of the printer 2 controls the control line 5 via the parallel interface circuit 8.
A calibration error signal is output to (S4
2). Then, the value of t _d is set to 0 (S43), and the signal timing correction process ends.

In step S30, if the test data comparison means 21 determines that the bit pattern of the received data stored in the received data storage means 18 matches the bit pattern of the test data, the system control means 14 internally It is determined whether or not the variable Mode is 0 (S3
5) In this case, since Mode is 0, the system control means 14 sets the present delay time t _d to the minimum value t ₁ of the appropriate delay time and sets the test mode Mode to
Mode to test the maximum value of the appropriate delay time (Mode
= 1) (S36). Then, the system control means 14 increments the value of t _d (S37), and controls the control line 5 via the parallel interface circuit 8.
The test data output request signal to the step S26.
Return to operation. That is, the delay time is increased by one clock, and in this time, in the test mode (Mode = 1) for checking the appropriate maximum value of the delay time, the delay time adjusting operation based on the test data is started.

The operations in steps S26 to S30 are the same in the test mode for checking the appropriate maximum value of the delay time, and therefore the description thereof will be omitted.

In step S30, if the test data comparison means 21 determines that the bit pattern of the received data stored in the received data storage means 18 matches the bit pattern of the test data, the system control means 14 internally It is determined whether or not the variable Mode is 0 (S3
5), in this case, Mode is 1, so the system control unit 14 increments the value of t _d (S37), the line control through a parallel interface circuit 8 5
The test data output request signal to the step S26.
Return to operation. That is, the delay time is increased by one clock and the delay time adjusting operation based on the test data is continued again.

On the other hand, in step S30, when the test data comparison means 21 determines that the bit pattern of the received data stored in the received data storage means 18 and the bit pattern of the test data do not match, the system control means 14 examines the current test mode mode (S31), in this case, mode is 1, so the system control unit 14 sets the current delay time t _d to the maximum value t ₂ of the appropriate delay time (S39). Next, the system control means 14 causes the minimum value t ₁ and the maximum value t ₂ of the appropriate delay time to be appropriate.
And the average value [(t ₁ −t ₂ ) / 2] (where [] is a Gaussian symbol) is calculated and set as a variable t _d (S40),
The delay amount setting means 20 sets t _d as the delay time in the delay means 16 (S41). That is, the margin of the latch timing of the data signal of the data latch means 17 is maximized by setting the middle value of the minimum value t ₁ and the maximum value t ₂ of the appropriate delay time as the delay time. When the above operation is completed, the system control means 14 releases the calibration mode and ends the signal timing correction process.

FIG. 4 is a timing chart of each signal after the delay time of the data latch means is adjusted by the signal timing correction method according to the second embodiment.

In FIG. 4, (a) is a data signal when a timing violation occurs, (b) is a strobe signal before delay time correction, (c) is a strobe signal after delay time correction, and (d). Is a busy signal before delay time correction,
(E) represents the busy signal after delay time correction.

In the example of FIG. 4, the strobe signal is asserted immediately before the data signal is switched, and a timing violation has occurred. Therefore, before delay time correction,
The data latch means 17 latches the data signal at point A immediately after the strobe signal is asserted, and an error occurs in the received data. However, after the correction of the delay time, the data latch means 17 latches the data signal at the time point (point B) after the delay time t _d has passed since the strobe signal was asserted, so that an error in the received data is prevented. You can see that you can.

[0071]

As described above, according to the data transfer system of the first aspect of the present invention, the strobe signal output means or the data output means of the transmitting side device is, for example, the transmitting side device, the receiving side device, or both devices. Depending on the characteristics of the cable that connects the strobe signal and the data signal, the positional relationship between the strobe signal and the data signal may deviate, causing timing violations and preventing accurate data transfer. By adjusting the delay time from the assertion until the data latch means latches the data signal, it is possible to provide a data transfer system capable of being repaired so that accurate data transfer is performed.

According to the second aspect of the present invention, it is possible to set the delay time that maximizes the timing margin for the data latching means to latch the data signal at the proper timing, so that it happens accidentally. It is possible to provide a data transfer system capable of minimizing the probability of an error in received data even when the timing of asserting the strobe signal is deviated.

According to the third aspect of the invention, when the timing margin determining means cannot detect the minimum value of the proper delay time or the difference between the minimum value and the maximum value of the proper delay time is less than or equal to a predetermined threshold value. In this case, since the transfer mode changing unit changes the current transfer mode to a transfer mode different from the current transfer mode, it is possible to eliminate the error in the received data caused by the improper transfer mode. A data transfer system can be provided.

According to the invention described in claim 4, the transfer rate changing means outputs the transfer rate changing request signal even when the difference (margin width) between the minimum value and the maximum value of the appropriate delay time is narrow. Since the transfer rate changing means slows the data transfer rate of the data output means in response to the transfer rate change request signal, the margin width can be widened, and the data latching means latches the data signal at the wrong timing and receives the wrong signal. A data transfer system capable of avoiding outputting data can be provided.

According to the signal timing correction method for the data transfer system of the fifth aspect of the present invention, the test data is used even when the strobe signal or the data signal transmitted from the transmitting side device has a timing violation. By adjusting the delay time to an appropriate value, it is possible to provide a signal timing correction method for a data transfer system capable of preventing an error in received data of a receiving side device.

According to the invention described in claim 6, since it becomes possible to set the delay time which maximizes the timing margin for the data latch means to latch the data signal at the proper timing, it is possible to set it by accident. It is possible to provide a signal timing correction method for a data transfer system that can minimize the probability of an error in received data even when the strobe signal is asserted at a different timing.

According to the invention described in claim 7, even if the delay time is adjusted, the data latch means cannot latch the data signal at an appropriate timing due to the ringing generated in the data line when the data signal is switched. In some cases, even when the timing margin for the data latching means to latch the data signal at an appropriate timing is narrower than a predetermined threshold value and a reception error is likely to occur, the reception error can be eliminated by switching the transfer mode of the transmission side device. It is possible to provide a signal timing correction method for a data transfer system, which can be prevented.

According to the invention described in claim 8, even when the difference (margin width) between the minimum value and the maximum value of the appropriate delay time is narrow, the receiving side device outputs the transfer rate change request signal and transmits it. Since the device on the side slows the data transfer rate of the data output means in response to the transfer rate change request signal, the margin width can be widened, and the data latch means latches the data signal at an incorrect timing to output incorrect received data. A signal timing correction method for a data transfer system capable of avoiding output can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a signal timing correction method of the data transfer system according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a signal timing correction method of the data transfer system according to the second embodiment of the present invention.

FIG. 4 is a timing chart of each signal after the delay time of the data latch means is adjusted by the signal timing correction method according to the second embodiment.

FIG. 5 is a timing chart of signals of a data line and a status line of a data transfer system using a conventional parallel interface.

[Explanation of symbols]

1 Host computer 2 printer 3 data lines 4 Strobe line 5,6 control line 7,8 parallel interface circuit 9 System control means 10 Data output means 11 Strobe signal output means 12 Timing correction start signal output means 13 Test data output means 14 System control means 15 Data strobe signal detecting means 16 delay means 17 Data Latch Means 18 Received data storage means 19 Timing correction start signal detecting means 20 Delay amount setting means 21 Test data comparison means

Claims (8)

[Claims] 1. A data line for transmitting a data signal,
The transmission side device and the reception side device are connected by an interface having a strobe line for transmitting a strobe signal indicating that the data signal is available, and a control line, the transmission side device, The reception device further comprises data output means for outputting the data signal to a data line, and strobe signal output means for asserting the strobe signal of the strobe line when the data signal is output to the data line. The side device is a data transfer system including a data latch means for latching the data signal of the data line and outputting it as received data during a period in which the strobe signal is asserted. Is a test data requesting output of test data consisting of a predetermined bit pattern. When the output request signal is input, the test data output means is provided for generating the test data and outputting the data signal of the test data to the data line by the data output means. A delay amount setting means for setting a delay time from the assertion of the strobe signal of the strobe line to the latching of the data signal of the data line by the data latch means, and the data signal of the test data output to the data line. The bit pattern of the received data output by the data latching means latching the data and the bit pattern of the test data are compared. If they do not match, the delay time setting means causes the delay time Is increased for a predetermined time, and the Data transfer system, characterized in that to Todeta output means are provided with a delay time adjusting means for outputting a test data output request signal. 2. A bit pattern of received data output by the delay time adjusting means when the data signal of the test data output to the data line by the test data output means is latched by the data latch means, and A timing margin determining unit that determines a minimum value and a maximum value of an appropriate delay time that match the bit pattern of the test data; and a minimum value and a maximum value of the appropriate delay time that are determined by the margin determining unit. The data transfer system according to claim 1, further comprising: a timing margin maximizing unit that sets an average value as the delay time by the delay amount setting unit. 3. The receiving side device, when the timing margin determining means cannot detect the minimum value of the proper delay time or when the difference between the minimum value and the maximum value of the proper delay time is less than or equal to a predetermined threshold value. In this case, the transmission side device comprises a transfer mode change request means for outputting a transfer mode change request signal to the control line, and the transmitting side device, when the transfer mode change request signal is output to the control line, 3. The data transfer system according to claim 2, further comprising transfer mode changing means for changing the transfer mode of the output means to a transfer mode different from the current transfer mode. 4. The receiving side device controls the transfer rate change request signal when the difference between the minimum value and the maximum value of the appropriate delay time detected by the timing margin determining means is less than a predetermined threshold value. Transmission rate change requesting means for outputting to the control line, the transmission side device slows down the data transfer rate of the data output means in accordance with the transfer rate change request signal output to the control line. The data transfer system according to claim 2, further comprising: 5. A data line for transmitting a data signal,
A strobe line for transmitting a strobe signal indicating that the data signal is available, and a transmission side device and a reception side device connected by a control line,
The transmission side device asserts or negates the strobe signal of the strobe line when the data signal is output to the data line and the data output means that outputs the data signal to the data line. Data having a strobe signal output means, and the receiving side device having a data latch means for latching the data signal of the data line and outputting it as received data within a period in which the strobe signal is asserted. In a transfer system, there is provided a signal timing correction method for correcting the timing at which the data latch means latches a data signal, when a test data output request signal requesting output of test data having a predetermined bit pattern is input. , The transmitting device generates the test data At the test data output step of outputting the data signal of the test data to the data line by the data output means, and at a time point when a predetermined delay time has elapsed after the strobe signal was asserted, A data receiving step of latching the data signal of the test data output to the line and outputting it as received data, the receiving side device compares the bit pattern of the received data with the bit pattern of the test data, If the two do not match, the delay time is increased by a predetermined time, and a delay time adjusting step of outputting a test data output request signal to the transmitting side device through the control line is included. A method for correcting signal timing in a data transfer system, comprising: 6. A bit pattern of received data output by the data latch means latching the data signal of the test data output to the data line by the test data output means by the receiving side device, and A timing margin determining step of determining a minimum value and a maximum value of an appropriate delay time that matches a bit pattern of test data, and the receiving side device, the minimum value of the appropriate delay time determined in the margin determining step. 6. A signal timing correction method for a data transfer system according to claim 5, further comprising a timing margin maximizing step of setting an average value of the maximum value and the maximum value as the delay time. 7. The reception when the minimum value of the proper delay time cannot be detected or the difference between the minimum value and the maximum value of the proper delay time is less than or equal to a predetermined threshold value in the timing margin determining step. The transmission side device outputs the transfer mode change request signal to the control line, and the transmission side device outputs the data when the transfer mode change request signal is output to the control line. 7. The signal timing correction method for a data transfer system according to claim 6, further comprising a transfer mode changing step of changing the transfer mode of the means to a transfer mode different from the current transfer mode. 8. When the difference between the minimum value and the maximum value of the appropriate delay time detected in the timing margin determining step is less than or equal to a predetermined threshold value, the receiving side device sends a transfer rate change request signal to the transfer rate change request signal. According to the transfer rate change request signal output to the control line and the transfer rate change request signal output to the control line, the transmission side device,
7. A signal timing correction method for a data transfer system according to claim 6, further comprising: a transfer rate changing step of reducing a data transfer rate of the data output means.