JP2003318324A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device having a reduced package size, capable of supporting both high-density mounting on a motherboard and chip repair, and having high connection reliability. SOLUTION: As a configuration of a semiconductor device, a semiconductor element 1 on which an element is formed, a conductor pattern 7 for rewiring formed on an element formation surface of the semiconductor element 1 via an insulating film 5, and a semiconductor element Connection holes 9 and 12 formed so as to cover element formation surface 1 and conductive pattern 7.
, A conductive buffer 10 formed on the conductor pattern 7 inside the connection hole of the insulating resin films 8 and 9, and an electric And an external connection electrode portion 14 formed in the opening of the connection hole in a state where the connection portion is mechanically and mechanically connected.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small semiconductor device having a semiconductor element as a base. 2. Description of the Related Art Generally, a semiconductor device having a chip-shaped semiconductor element is often configured as one package. As one of the package forms for realizing such a small and light semiconductor device, a CSP (Chip Size) in which the package size is reduced to a level close to a chip size.
Package) is known. As a configuration of a conventional semiconductor device belonging to the CSP, for example, the configuration shown in FIGS. 5A to 5C is known. FIG. 5A shows a face-down BGA (Ball Grid).
1 shows a configuration of a semiconductor device adopting an (Array) structure. In this configuration, when mounting the semiconductor element 51 face down, a plurality of protruding terminals 52 are formed on the semiconductor element 51, and these protruding terminals 52 are electrically and electrically connected to the electrode terminals 54 on one surface of the circuit board 53. Connected mechanically. Further, a plurality of solder balls 55 are formed on the other surface of the circuit board 53, and the solder balls 55 are used as external connection terminals to a mother board (mother board). Further, an insulating resin 56 is filled in a portion (a gap portion) between the semiconductor element 51 and the circuit board 53 so as to cover a connection portion between the protruding terminal 52 and the electrode terminal 54. FIG. 5B shows a configuration of a semiconductor device employing a face-up BGA structure. In this configuration, the semiconductor element 61 is mounted (mounted) face-up on the circuit board 62, and the electrode section (aluminum pad or the like) formed on the semiconductor element 61 and the electrode section formed on the circuit board 62. And a wire 63 such as a gold wire
(Wire bonding). In addition, the semiconductor element 61 is sealed on one surface of the circuit board 62 with the sealing resin 64, and a plurality of solder balls 65 are formed on the other surface of the circuit board 62, and the solder balls 65 are externally connected to the mother board. Terminals. FIG. 5C shows a face-up LGA (Lan
1 shows a configuration of a semiconductor device adopting a (d Grid Array) structure. In this configuration, the semiconductor element 71 is mounted face-up on the circuit board 72, and the electrodes formed on the semiconductor element 71 and the electrodes formed on the circuit board 72 are connected to wires 73 such as gold wires. Connected with. In addition, the semiconductor element 71 is sealed on one surface of the circuit board 72 with the sealing resin 74, and a plurality of connection terminals 75 are formed on the other surface of the circuit board 72. Terminals. This figure 5
The semiconductor device illustrated in FIG. 5C is different from the semiconductor device illustrated in FIG. 5B only in the shape of the external connection terminal. Conventionally, as shown in FIG. 6, a flip-chip mounting structure in which a semiconductor element 82 is directly mounted face down on a mother substrate 81 made of a glass epoxy substrate has been adopted. In this flip-chip mounting structure, a plurality of solder electrodes (projection electrodes) 83 are formed on a semiconductor element 82, and the solder electrodes 83 are electrically and mechanically connected to an electrode portion 84 of a mother substrate 81 by a reflow method. I have. In addition, an opposing portion (a gap portion) between the mother substrate 81 and the semiconductor element 82 is filled with an inner fill 85 in a state of covering a connection portion between the solder electrode 83 and the electrode portion 84. However, the above-described conventional semiconductor device and flip-chip mounting have the following problems. That is, the CS shown in FIGS.
In the semiconductor device of P, in order to improve the mountability when mounting the semiconductor device on the motherboard by the reflow method,
A semiconductor element is mounted on a circuit board, and a conductor pattern for rewiring is routed within the circuit board, so that the size and arrangement pitch of the external connection terminals are widened. Therefore, a circuit board as an interposer, and a film substrate and a lead frame as alternatives are required, which hinders a reduction in the size and weight of the CSP, a reduction in cost, and a high-density mounting on a mother board. . In the flip-chip mounting structure shown in FIG. 6, since the thermal expansion coefficients of the mother substrate 81 and the semiconductor element 82 are different, the connection between the solder electrode 83 and the electrode portion 84 is affected by the difference in thermal expansion between the two. (Joint) generates stress. That is, while the mother board 81 is based on the glass epoxy board, the semiconductor element 82 is based on the silicon board, so that the difference in thermal expansion between the two is increased, stress is applied to the connection portion, and cracks may occur. is there. For this reason, it is difficult to ensure connection reliability in a mounted state. Such a defect in connection reliability due to a difference in thermal expansion similarly occurs in the CSP semiconductor device shown in FIGS. 5A to 5C. That is, in the semiconductor device illustrated in FIG. 5A, stress due to a difference in thermal expansion between the semiconductor element 51 and the circuit board 53 is generated at a connection portion between the protruding terminal 52 and the electrode terminal 54. In the semiconductor device shown in FIG. 5B, stress due to a difference in thermal expansion between the semiconductor element 61 and the circuit board 62 is generated at a connection portion (second bonding portion of wire bonding) between the wire 63 and the circuit board 62 electrode. Also in the semiconductor device shown in FIG. 5C, stress due to a difference in thermal expansion between the semiconductor element 71 and the circuit board 72 is generated at a connection portion between the wire 73 and the electrode of the circuit board 72. Therefore, conventionally, in order to reduce the stress acting on the connecting portion due to the difference in thermal expansion, FIG.
In the semiconductor device shown in FIG. 5, the insulating resin 56, the sealing resin 64 in the semiconductor device shown in FIG. 5B, and the sealing resin 74 in the semiconductor device shown in FIG. As a result, connection reliability is improved. Therefore, in the semiconductor device shown in FIGS. 5A to 5C, the package size is inevitably larger than the chip size due to the presence of the rewiring interposer (such as a circuit board) and the resin portion having a buffer function. However, further miniaturization cannot be expected. In the case of the flip-chip mounting structure shown in FIG. 6, although the connection reliability is improved by incorporating the inner fill 85 as a cushioning material, the inner fill 85 is provided in the gap between the mother substrate 81 and the semiconductor element 82. 85, the semiconductor elements 83 on the mother substrate 81
It is necessary to secure an area for filling the inner fill in the peripheral portion of. Since other components cannot be mounted in this filling area, the chip mounting area on the mother board 81 is substantially enlarged, which hinders high-density mounting. In order to improve the connection reliability, it is effective to use a large-diameter solder ball for connection to the mother board 81. However, using a large-diameter solder ball is disadvantageous in terms of mounting density and mounting height. Therefore, it becomes difficult to respond to the demand for miniaturization. Further, in the method of filling the inner fill 85, when the semiconductor element 82 is determined to be defective in a step (for example, operation check) after the filling of the inner fill 85, repair (replacement of a defective chip to a good chip) is performed. ) Cannot be handled. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. It is an object of the present invention to reduce the package size and to cope with both high-density mounting on a mother board and chip repair. Another object of the present invention is to provide a semiconductor device having high connection reliability. [0013] A semiconductor device according to the present invention comprises a semiconductor element on which an element is formed, and a rewiring formed on an element formation surface of the semiconductor element via an insulating film. A conductive pattern, an insulating resin film formed so as to cover the element forming surface of the semiconductor element, and having a connection hole communicating with the conductor pattern; and an insulating resin film formed on the conductive pattern inside the connection hole of the insulating resin film. A conductive buffer portion, and an external connection electrode portion formed in the opening of the connection hole while being electrically and mechanically connected to the buffer portion. In the semiconductor device having the above configuration,
By forming a conductor pattern for rewiring on an element forming surface of a semiconductor element via an insulating film, an interposer for rewiring becomes unnecessary and the element forming surface of the semiconductor element is covered with an insulating resin film. Thereby, the element formation surface is resin-sealed with the insulating resin film. Further, by providing a conductive buffer portion inside the connection hole of the insulating resin film and forming an electrode portion in the opening of the connection hole in a state of being electrically and mechanically connected to the buffer portion, the electrode is formed. The buffer effect of the buffer portion acts directly and intensively on the portion. Therefore, when this semiconductor device is mounted on a motherboard, the connection portion (the electrode portion on the semiconductor device side and the corresponding electrode portion on the motherboard side) depends on the difference between the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the motherboard. The stress acting on the connection portion is effectively reduced by the buffer portion. Embodiments of the present invention will be described below in detail with reference to the drawings. A configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. First, in a wafer processing step using a silicon wafer, as shown in FIG. 1A, an electrode pad (such as an aluminum pad) is formed on a main surface of a semiconductor element (a silicon substrate in this example) 1 on which an element is formed. 2) and a passivation film 3 are formed. A plurality of electrode pads 2 are formed at a predetermined arrangement pitch on the outer peripheral edge of the semiconductor element 1 having a chip shape. Further, the passivation film 3 is formed (formed) so as to cover the main surface (element formation surface or the like) of the semiconductor element 1. In the passivation film 3, a connection hole 4 exposing the electrode pad 2 is formed. Incidentally, in a general semiconductor manufacturing process, the wafer processing step is completed when the formation of the electrode pads 2 and the passivation film 3 is completed, and thereafter, a dicing step for dividing the chips and an electrical connection for electrical connection are performed. The process proceeds to an assembling process (packaging process) such as a wire bonding process and a molding process for sealing. In the method of manufacturing a semiconductor device according to the present embodiment, subsequent processes are performed in a wafer state. In this wafer state, a large number of semiconductor elements 1 corresponding to one semiconductor element are formed on one wafer, and these semiconductor elements 1
Will be divided into individual pieces. That is, as shown in FIG. 1B, an insulating film 5 is formed on the main surface of the semiconductor element 1 in a wafer state. The insulating film 5 is formed so as to cover the entire main surface (element formation surface) of the semiconductor element 1. As a specific film forming method, for example, while rotating a silicon wafer held in a horizontal state, on this silicon wafer,
An insulating film 5 made of a polyimide resin film is formed on the semiconductor elements 1 in the wafer by forming a coating film made of the polyimide resin on the entire surface of the wafer by a so-called spin coating method in which a polyimide resin having an appropriate viscosity is dropped and diffused. Form. In this spin coating method, a film of about 3 to 5 μm is formed by one application. In addition to the spin coating method, the insulating film 5 may be formed by laminating a film-like resin. In this case, the physical properties of the insulating film 5 are such that the elastic modulus is 5 to reduce the warpage of the semiconductor element.
It is preferable to select one having 10 GPa and a thermal expansion coefficient of 60 ppm or more. Next, as shown in FIG. 1C, a connection hole 6 communicating with the electrode pad 2 is formed on the insulating film 5 by patterning the insulating film 5. This connection hole 6
Is formed with a diameter larger than the connection hole 4 of the passivation film 3 (for example, a diameter substantially equal to the size of the electrode pad 2). The patterning of the insulating film 5 may be performed, for example, by using a polyimide resin (photoresist) mixed with a photosensitive material as a film forming material of the insulating film 5.
It can be performed using photolithography technology. Subsequently, on the surface of the electrode pad 2 exposed by the formation of the connection hole 6, for example, titanium (Ti),
A barrier metal (not shown) is formed by performing a plating process with nickel (Ni). After that, the exposed portion of the electrode pad 2 covers the barrier metal as shown in FIG.
As shown in (1), a conductor pattern 7 is formed on the insulating film 5 of the semiconductor element 1 by plating copper (Cu), for example.
The conductor pattern 7 is provided on the element formation surface of the semiconductor element 1 with a plurality of electrode pads 2 formed on the outer peripheral edge of the semiconductor element 1. It becomes a conductor pattern for rewiring for distributing and arranging over the entire surface. Next, as shown in FIG. 2A, a first insulating resin film 8 is formed on the insulating film 3 of the semiconductor element 1 so as to cover the conductor pattern 7, and then the first insulating resin film 8 is formed. Through the insulating resin film 8 (in other words, the conductor pattern 7).
The connection hole 9 is formed in a state in which a part of the connection hole 9 is exposed. First
The insulating resin film 8 is formed by, for example, forming a polyimide resin on the semiconductor element 1 by a spin coating method or a dry film method. The connection hole 9 is formed by forming a hole in the first insulating resin film 8 by patterning. The connection hole 9 serves as a contact hole (via hole) for forming an electrode for external connection when conducting rewiring by routing the above-described conductor pattern 7, and is provided over the entire area on the main surface of the semiconductor element 1. Are formed at an arrangement pitch of. Subsequently, as shown in FIG. 2B, a conductive buffer 10 is buried in the connection hole 9 of the first insulating resin film 8. This buffer 10 is made of, for example, copper (Cu), gold (A
u), a conductive paste produced by kneading a metal fine powder such as silver (Ag) with an epoxy-based resin is applied to the conductor pattern 7 from the opening of the connection hole 9 so as to be embedded.
The conductive paste is thermally cured (cured) after application. Thereby, the buffer portion 1 is placed on the conductor pattern 7 inside the connection hole 9.
0 is stacked. When an epoxy resin is used as the resin material of the conductive paste, the elastic modulus of the buffer section 10 obtained by thermosetting the conductive paste is about 20 GPa. The buffer portion 10 is formed not only by a buffer effect against stress but also by using its conductivity to form a layered layer to serve as a ground (GND) layer, and this ground layer serves as a signal line for rewiring. It is also possible to exert the effect of preventing interference between them. Here, the hole diameter of the connection hole 9 serving as a portion where the buffer portion 10 is formed is determined as much as possible while taking into consideration the pitch and size of the electrode after rewiring in order to enhance the buffering effect of the buffer portion 10. It is desirable to set a large value (preferably 300 μm or more). In addition, since the buffering effect of the buffer 10 largely depends on its height, the insulating film 8 is formed with a sufficiently large film thickness, whereby the height of the buffer 10 is limited to the mounting height. As large as possible within the allowable range (preferably 150 to 180 μm
It is desirable to set. In mounting a semiconductor device based on the semiconductor element 1 on a motherboard, the thermal expansion coefficient of the buffer section 10 is intermediate between the thermal expansion coefficient of the semiconductor element 1 and the thermal expansion coefficient of the motherboard. It is desirable to set it to an appropriate value. For example, when the mother substrate is an FR-4 grade glass epoxy substrate, the thermal expansion coefficient of the mother substrate is 15 ppm, while the silicon semiconductor element 1
Has a coefficient of thermal expansion of 3 ppm, so that the coefficient of thermal expansion of the buffer 10 is in the range of 3 to 15 ppm (for example, 10 ppm).
ppm). As a method for embedding the buffer section 10, a method other than the above method may be adopted. For example, a film in which connection holes are formed in advance at positions corresponding to the electrode formation sites is pasted on the semiconductor element 1 (on an actual process, on a wafer), and then a photosensitive resist is applied, and this is exposed and developed. This exposes the connection hole. Next, a conductive paste obtained by mixing the fine metal powder with an epoxy resin to be a thermosetting resin is applied by a spin coating method, so that the conductive paste is poured into the connection holes. Subsequently, after unnecessary conductive paste is removed by peeling off the resist, the conductive paste remaining in the connection hole is thermally cured, so that the buffer portion 10 made of the conductive paste is embedded in the connection hole. Thus, the connection hole 9 of the first insulating resin film 8 is formed.
After the buffer portion 10 is buried in the semiconductor device 1, as shown in FIG. 2C, a second insulating resin film 11 is formed on the semiconductor element 1 so as to cover the first insulating resin film 8. A state penetrating the second insulating resin film 11 (in other words, the buffer portion 1)
0 is exposed) to form the connection hole 12. The connection hole 12 is formed coaxially with the connection hole 9 described above. The diameters of the connection holes 9 and 12 may be set to be equal to each other, or the diameter of the connection hole 12 may be set slightly smaller than the diameter of the connection hole 9. In addition, as a method of forming the second insulating resin film 11 and the connection hole 12, the same method as that of the first insulating resin film 8 and the connection hole 9 described above may be employed. Next, as shown in FIG. 3A, nickel plating, titanium plating or the like is applied on the buffer section 10 through the connection hole 12 of the second insulating resin film 11 to form the barrier metal 13. After the formation, an electrode section 14 is formed by solder plating on the buffer section 10 via the barrier plating 13 as shown in FIG. At this time, solder plating is applied to the connection holes 1 formed in the second insulating resin film 11.
2 is filled (embedded) with solder.
In the surface layer portion of the semiconductor element 1, the electrode portion 14 is formed so as to be slightly exposed from the surface of the second insulating resin film 11. Thus, in the openings of the connection holes 9, 12 formed in the first and second insulating resin films 8, 11, the electrode section 1 is electrically and mechanically connected to the buffer section 10.
4 are formed. In this case, inside the connection holes 9 and 12, the buffer portions 10,
The barrier metal 13 and the electrode portion 14 are sequentially laminated, and the lower portions of the connection holes 9 and 12 (rear portions of the holes).
The buffer unit 10 is buried in the state. This electrode part 14
Is electrically and mechanically connected to an electrode for external connection when the semiconductor device obtained by the manufacturing method according to the present embodiment is mounted on the motherboard, that is, an electrode portion formed on the motherboard side by a reflow method or the like. Electrode terminals to be used. At this time, on the semiconductor element 1, a plurality of electrodes formed on the outer peripheral edge of the semiconductor element 1 are formed by the rewiring formation using the copper conductor pattern 7 and the electrode formation on the conductor pattern 7. As shown in FIG. 4, a plurality of (the same number as the electrode pads 2) electrode portions 14 are arranged in an array with a pitch wider than the arrangement pitch of the pads 2.
For example, the arrangement pitch of the electrode pads 2 is 90 to 100 μm.
In this case, the electrode portions 14 are arranged at an arrangement pitch of 0.35 to 0.8 mm, which is sufficiently wider than that. Further, assuming that the size of the electrode pad 2 is 70 to 100 μm □, the electrode portion 14 is formed with a sufficiently large size. Due to the pitch conversion and size conversion of the electrodes by the rewiring, the mountability on the motherboard is improved. In the configuration of the semiconductor device obtained by the above-described manufacturing method, the main surface (element forming surface) of the semiconductor element 1 is covered with the first and second insulating resin films 8 and 11, and these insulating The element forming surface of the semiconductor element 1 is sealed with the resin by the resin films 8 and 11. In addition, since rewiring is performed by the conductor pattern 7 on the semiconductor element 1, an interposer for rewiring becomes unnecessary. As a result, a so-called wafer-level CSP in which copper rewiring formation, electrode terminal formation, and resin sealing are performed in a wafer state is realized.
This semiconductor device of the wafer level CSP becomes a package of the same size as a semiconductor element when cut out from a wafer into individual pieces, which contributes to the reduction in size and weight of the package. According to the structure of the semiconductor device obtained by the above-described manufacturing method, the buffer effect of the buffer section 10 acts directly and intensively on the electrode section 14 for external connection. When the semiconductor device is mounted on the mother substrate, the connection portion (the electrode portion on the semiconductor device side and the corresponding electrode portion on the mother substrate side) may differ depending on the difference between the thermal expansion coefficient of the semiconductor element 1 and the thermal expansion coefficient of the mother substrate. The stress acting on the connection portion is effectively reduced by the buffer portion 10. As a result, stress due to thermal expansion between the semiconductor element 1 and the mother substrate can be sufficiently reduced, and connection reliability between the two substrates can be increased. As a result, unlike the conventional flip chip mounting structure (see FIG. 6), there is no need to fill the semiconductor device and the mother substrate with an inner fill for relaxing stress. There is no need to secure a filling area for filling. In addition, it is possible to easily cope with repair when the semiconductor element is defective. Also, the first and second insulating resin films 8 and 11
Is formed of a material having a low dielectric constant (LowK material), thereby making it possible to cope with a high-frequency element. In general, in a semiconductor device that handles a high-frequency signal of 30 GHz or more, when the semiconductor device is mounted on a mother substrate, it is necessary to secure a gap (gap) of 35 μm or more between the mother substrate and the semiconductor device (particularly, a semiconductor element). is there. In such a case, if the mounting height of the components on the motherboard side is limited, the thickness of the semiconductor device (the thickness of the package) becomes a very bottleneck. On the other hand, in the semiconductor device according to the present embodiment, even when the height is restricted as described above, for example, the semiconductor element 1 is thinned by grinding the back surface of the wafer.
A spherical electrode such as a solder ball is formed on the external connection electrode (electrode portion 14) of the semiconductor element by using the dimensional margin obtained by this, so that the height restriction is cleared and high-frequency signals can be handled. It is possible to respond. Further, by forming (adding) the spherical electrode, an effect of increasing the stress relaxation effect can be obtained. As described above, according to the present invention, a conductor pattern for rewiring is formed on a device forming surface of a semiconductor device, and the device forming surface of the semiconductor device is formed of an insulating resin film. By covering, the package size can be reduced to the same level as the chip size. In addition, a conductive buffer is provided inside the connection hole of the insulating resin film covering the element forming surface of the semiconductor element, and an electrode is provided in the opening of the connection hole in a state of being electrically and mechanically connected to the buffer. By forming the portion, the connection reliability in the mounted state can be improved. As a result, it is possible to provide a semiconductor device which can reduce both the package size, and can cope with both high-density mounting on a motherboard and chip repair and has high connection reliability.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram (part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 3 is a diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a diagram showing an electrode arrangement of the semiconductor device according to the embodiment of the present invention. FIG. 5 is a diagram illustrating a configuration example of a conventional semiconductor device. FIG. 6 is a diagram showing a conventional flip chip mounting structure. [Description of Signs] 1 ... Semiconductor element, 2 ... Electrode pad, 3 ... Bassivation film, 4,6,9,12 ... Connection hole, 5 ... Insulation film, 7 ... Conductor pattern, 8 ... First insulating resin Membrane, 10 ... buffer part,
11: second insulating resin film, 14: electrode section

Claims (1)

Claims: 1. A semiconductor element on which an element is formed, a conductor pattern for rewiring formed on an element formation surface of the semiconductor element via an insulating film, and an element of the semiconductor element. An insulating resin film formed so as to cover the formation surface and having a connection hole communicating with the conductive pattern; and a conductive buffer formed on the conductive pattern inside the connection hole of the insulating resin film. And an external connection electrode portion formed in the opening of the connection hole while being electrically and mechanically connected to the buffer portion.