JP2003318349A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Problem] Since solder does not easily turn between the lead terminal and the pattern of the printed board at the time of soldering, it can not be confirmed,
Poor soldering may cause degradation of high frequency characteristics. SOLUTION: A slit 3, a slit 4, or a through hole 5 penetrating the lead terminal 2 is formed in a lead terminal 2 of a high-frequency FET 1. With this structure, the amount and position of the solder that has flowed into the lead terminal 2 and the pattern 6 through the slits and the through holes, not only from the outer periphery of the lead terminal 2 at the time of soldering, can be visually confirmed. Solder of uniform quality can be performed with a sufficient amount of solder, and deterioration of high frequency characteristics due to poor soldering can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high power FET or a power transistor for power supply,
The present invention relates to improvement of lead terminals.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional high-power high-power FET.
It is a top view which shows (field effect transistor). 1 in the figure
Is a high output FET, and 2 is a lead terminal. Lead terminal 2
Are a gate terminal and a drain terminal. Generally, in a high frequency device, the lead terminal 2 is formed in a flat plate shape as shown in FIG. 1 to prevent deterioration of the high frequency characteristic of the device.

[0003]

However, in the above conventional semiconductor device, when the lead terminal 2 of the high power FET 1 is soldered to the printed board 7 at the soldering position 8 as shown in FIG. It was difficult to turn between 2 and the pattern 6 on the printed board 7, and no confirmation could be made.
That is, when the lead terminal 2 is soldered on the pattern 6, the solder is attached to the outer periphery of the lead terminal 2 or the solder flowing from the outer periphery of the lead terminal 2 into the pattern 6 below the lead terminal 2 is connected. Since there is no way to check the amount of solder that has flowed in and the position where it has flowed in, the mounting was subject to considerable variations depending on the conditions of the operator and the soldering iron.

Therefore, the high frequency characteristics are often deteriorated due to poor soldering. Further, in order to avoid this soldering failure, it is necessary to apply a soldering iron to the lead terminal 2 portion for a long time, resulting in poor workability. Further, in some cases, excessive heat may destroy the device.

The present invention has been made in view of the above conventional problems, and an object thereof is to provide a semiconductor device capable of preventing deterioration of high-frequency characteristics or deterioration or destruction of a device.

[0006]

In order to achieve the above object, the present invention provides a semiconductor device having a flat lead terminal for electrically connecting by soldering on a pattern of an external substrate. It is characterized in that a slit or a through hole penetrating the lead terminal is formed in the terminal so that the amount of solder on the pattern of the substrate can be confirmed through the slit or the through hole when soldering.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of the semiconductor device of the present invention. In the following embodiments, the semiconductor device is used as a high frequency high power output F
An ET (field effect transistor) will be described as an example. In FIG. 1, 1 is a high-power high-frequency FET and 2 is a lead terminal. The high output FET 1 is provided with lead terminals 2 on the gate side and the drain side, respectively.

Here, the upper lead terminal in the drawing is a drain terminal, and the lower lead terminal is a gate terminal. By applying an appropriate bias voltage to the two lead terminals 2, the RF signal input to the gate terminal is amplified and output from the drain terminal. High-power FET
The left and right terminals of 1 are source terminals, which are fixed to a case (not shown) with screws.

The lead terminal 2 has a flat plate shape, and the lower surface of the lead terminal 2 is in contact with the printed board when it is mounted on a printed board (not shown). Also,
A plurality of slits 3 are formed in each lead terminal 2 along the longitudinal direction of the lead terminal 2. The slit 3 penetrates the lead terminal 2, and when mounted on the printed board, the pattern of the printed board can be viewed from above the lead terminal 2.

FIG. 2 is a plan view showing a second embodiment of the semiconductor device of the present invention. The difference from FIG. 1 is the lead terminal 2.
Is the structure of. In this embodiment, a plurality of slits 4 are formed in the flat lead terminal 2 of the high-power FET 1 along the lateral direction thereof. The slit 4 penetrates the lead terminal 2 as in the first embodiment, and the pattern of the printed circuit board can be viewed from above.

FIG. 3 is a plan view showing a third embodiment of the semiconductor device of the present invention. The difference from FIGS. 1 and 2 is the structure of the lead terminal 2. In this embodiment, a plurality of circular through holes 5 are formed in the flat lead terminal 2. The through hole 5 penetrates the lead terminal 2 as in the first and second embodiments, and the pattern of the printed circuit board can be viewed from above.

The through hole 5 is not limited to a circular shape, but may be an elliptical shape or the like. The slit shape of the lead terminal 2 is not limited to the slit shape of FIGS. 1 and 2, but the slit 3 of FIG. 1 is formed obliquely or the slit 4 of FIG. 2 is formed obliquely. May be.

FIG. 4 is a plan view showing a state in which the high power FET 1 is mounted on a printed board. In FIG. 4, the high output F of FIG.
The case where the ET1 is mounted on a printed board is shown as an example. In the figure, 7 is a printed board, 6 is a pattern formed on the printed board 7, and 8 is a soldering position. Also, high output FET
1, the source terminal is fixed to the case (not shown) with screws 9 as described above. When the high-power FET 1 is soldered to the printed board 7, the lead terminal 2 is placed on the pattern 6 of the printed board 7 and is soldered at the soldering position 8 using a soldering iron.

At the time of this soldering, the solder flows not only between the outer periphery of the lead terminal 2 but also through the slit 3 and between the lead terminal 2 and the pattern 6 of the printed board 7. In this case, let alone the solder attached to the outer circumference of the lead terminal 2,
The position and amount of the solder flowing into the pattern 6 under the lead terminal 2 can be visually confirmed through the slit 3.
Therefore, if the amount and position of the solder that flows in is specified, even if the operator is different or the conditions such as the soldering iron are different, it is possible to visually solder with a substantially uniform quality, and it is possible to reliably use an appropriate amount of solder. Soldering can be done.

Here, in the high-frequency high-power FET 1, if the amount of solder flowing between the lead terminal 2 and the pattern 6 is too small, there is a high-frequency inductance between the lead terminal 2 and the pattern 6. Are equivalent. this is,
It may be one of the factors that deteriorate the high frequency characteristics. In the present embodiment, since it is possible to easily confirm that the amount of solder is appropriate, it is possible to prevent deterioration of high-frequency characteristics due to the above factors and a short-circuit accident due to excessive solder flow.

Further, compared with the conventional lead terminal as shown in FIG. 5, the lead terminal of the present embodiment has a smaller volume and a smaller heat capacity, so a soldering iron is applied during soldering. The time is short. Therefore, not only the time required for mounting can be shortened, but also the possibility of damaging the device or the printed board due to over-application of the soldering iron can be reduced. Here, in FIG. 4, the case of soldering the high-power FET of FIG. 1 to the printed board has been described, but when soldering the high-power FET of FIGS. 2 and 3, the position of the solder through the slit 4 and the through hole 5 is also used. Since the amount and amount can be confirmed, exactly the same effect can be obtained.

In the above embodiments, the high-frequency high-power FET is used as an example of the semiconductor device, but the present invention is not limited to this. It can also be used for power transistors. At this time, the same effect can be obtained from the viewpoint of solderability and damage to the device. Further, according to the present invention, not only the RF signal input / output lead terminals but also the ground lead terminals need to be directly soldered to the printed board. Similarly, slits or through holes are formed in the lead terminals. This is effective in terms of both solderability and high frequency characteristics.

[0018]

As described above, according to the present invention, by forming a slit or a through hole in a flat lead terminal, it is possible to easily confirm the amount and position of solder, and also to solder from the slit or through hole. Flows into between the lead terminal and the pattern of the printed board, so that it is possible to reliably perform soldering with an appropriate amount of solder. Therefore, it is possible to prevent variations in high frequency characteristics or deterioration in high frequency characteristics caused by poor soldering of the semiconductor device.

Further, since unnecessary work such as applying a soldering iron for a long time to avoid defective soldering is eliminated, it is possible to improve workability without spending unnecessary time for soldering. Further, by forming the slits or through holes, the volume of the lead terminal is reduced, the heat capacity is reduced, and the time for applying the soldering iron is short, so the time required for mounting can be shortened and damage to the semiconductor device or printed board Can be made smaller.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing a third embodiment of the present invention.

FIG. 4 is a plan view showing a state in which the semiconductor device of the present invention is mounted on a printed board.

FIG. 5 is a plan view showing a conventional high output FET.

6 is a plan view showing a state in which the high-power FET of FIG. 6 is mounted on a printed board.

[Explanation of symbols]

1 High output FET 2 lead terminals 3, 4 slits 5 through holes 6 patterns 7 printed board 8 Soldering position 9 screws

Claims (6)

[Claims] 1. A semiconductor device having a flat lead terminal for electrical connection by soldering on a pattern of an external substrate, wherein a slit or a through hole penetrating the lead terminal is formed in the lead terminal. A semiconductor device characterized in that the amount of solder on the pattern of the substrate can be confirmed through the slits or through holes during soldering. 2. The semiconductor device according to claim 1, wherein the through holes or slits are formed in all lead terminals. 3. The semiconductor device according to claim 1, wherein a plurality of the through holes or slits are formed in one lead terminal. 4. The semiconductor device according to claim 1, wherein the through hole has a circular shape or an elliptical shape. 5. The semiconductor device is a high-power FE for high frequencies.
It is T, The semiconductor device of Claims 1-4 characterized by the above-mentioned. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a power transistor for power supply.