JP2003318059A - Multilayer ceramic capacitors - Google Patents
Multilayer ceramic capacitorsInfo
- Publication number
- JP2003318059A JP2003318059A JP2002124210A JP2002124210A JP2003318059A JP 2003318059 A JP2003318059 A JP 2003318059A JP 2002124210 A JP2002124210 A JP 2002124210A JP 2002124210 A JP2002124210 A JP 2002124210A JP 2003318059 A JP2003318059 A JP 2003318059A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- ceramic capacitor
- laminated body
- internal electrode
- conductive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
- H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】
【課題】 温度サイクルや熱衝撃の条件が厳しくなった
場合も、積層体にクラックが発生しない高品質かつ高信
頼性の積層セラミックコンデンサを提供する。
【解決手段】 NiまたはCuを主成分とする内部電極
層3、4を有する誘電体層2を交互に積層してなる積層
体1と、積層体1の両端面に内部電極層3、4と接続す
る外部電極5、6を形成してなる積層セラミックコンデ
ンサ10において、外部電極5、6は、積層体1内側か
ら、少なくともCuとNiとの合金及びガラス成分を含
有する下地導体膜5a、6aと、Cu、Ni、Agの少
なくとも1種以上を含有する導電性樹脂層5b、6b
と、メッキ層5c〜5d、6c〜6dとを順次積層して
なることを特徴とする。
(57) [Problem] To provide a high-quality and high-reliability multilayer ceramic capacitor in which a crack does not occur in a laminated body even when conditions of a temperature cycle and a thermal shock become severe. SOLUTION: A laminated body 1 is formed by alternately laminating dielectric layers 2 having internal electrode layers 3, 4 mainly composed of Ni or Cu, and internal electrode layers 3, 4 on both end surfaces of the laminated body 1. In the multilayer ceramic capacitor 10 formed with the external electrodes 5 and 6 to be connected, the external electrodes 5 and 6 are formed from the inside of the multilayer body 1 with the base conductor films 5 a and 6 a containing at least an alloy of Cu and Ni and a glass component. And conductive resin layers 5b and 6b containing at least one of Cu, Ni and Ag
And plating layers 5c to 5d and 6c to 6d are sequentially laminated.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、積層セラミックコ
ンデンサに関し、特に外部電極の構造に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor, and more particularly to the structure of external electrodes.
【0002】[0002]
【従来の技術】従来、積層セラミックコンデンサは、複
数のチタン酸バリウム等の誘電体層と、複数の内部電極
層とが交互に積層されてなる積層体と、その積層体の両
端面に形成した一対の外部電極とから構成され、積層方
向に隣接しあう各内部電極層は、各々異なる外部電極に
接続されている。また、外部電極は、Cu及びガラス成
分を含有し、積層体の両端面に焼き付けることにより形
成される下地導体膜と、この下地導体膜表面に形成され
た、Niメッキ層、SnまたはSn−Pbメッキ層等と
からなる。2. Description of the Related Art Conventionally, a laminated ceramic capacitor is formed on both end faces of a laminated body in which a plurality of dielectric layers such as barium titanate and a plurality of internal electrode layers are alternately laminated. Each internal electrode layer, which is composed of a pair of external electrodes and is adjacent to each other in the stacking direction, is connected to different external electrodes. The external electrode contains Cu and a glass component and is formed by baking on both end faces of the laminated body, and a Ni plating layer, Sn or Sn-Pb formed on the surface of the underlying conductor film. It consists of a plating layer and the like.
【0003】しかしながら、上記積層セラミックコンデ
ンサにおいて、外部電極の下地導体膜を焼き付けによっ
て形成されるので、下地導体膜と積層体との接合部、と
くに下地導体膜の周辺部分におけるCu粉末の焼結収縮
及び誘電体層へのガラス成分の拡散によって応力が生
じ、そのため、この積層セラミックコンデンサを回路基
板に半田付けにより実装したものに対し、温度サイクル
試験や熱衝撃試験を行うと、誘電体層、外部電極、半
田、回路基板、各々の熱膨張係数差により応力吸収が不
十分となり、外部電極の周辺部から積層体にクラックが
発生し、その結果、積層セラミックコンデンサが機能し
なくなっていた。However, in the above-mentioned laminated ceramic capacitor, since the base conductor film of the external electrode is formed by baking, the sintering contraction of the Cu powder at the joint between the base conductor film and the laminated body, especially at the peripheral portion of the base conductor film. Since stress is generated by the diffusion of the glass component into the dielectric layer and the dielectric layer, when a temperature cycle test or a thermal shock test is performed on the one mounted with the laminated ceramic capacitor on the circuit board by soldering, the dielectric layer, the external Due to the difference in thermal expansion coefficient between the electrodes, the solder, and the circuit board, stress absorption becomes insufficient, and cracks occur in the laminated body from the peripheral portions of the external electrodes, and as a result, the laminated ceramic capacitor fails to function.
【0004】そこで、外部電極として、積層体内側か
ら、Cu単体及びガラス成分を含有する下地導体膜と、
Cu、Ni、Agの少なくとも1種以上を含有する導電
性樹脂層と、Niメッキ層、SnまたはSn−Pbメッ
キ層とを順次積層してなる積層セラミックコンデンサが
特開平6−29144号公報、特開平8−107039
号公報に開示されている。Therefore, as an external electrode, from the inside of the laminate, a base conductor film containing a simple substance of Cu and a glass component,
A monolithic ceramic capacitor in which a conductive resin layer containing at least one of Cu, Ni and Ag and a Ni plating layer and a Sn or Sn-Pb plating layer are sequentially laminated is disclosed in Japanese Patent Laid-Open No. 6-29144. Kaihei 8-107039
It is disclosed in the publication.
【0005】積層セラミックコンデンサを回路基板に半
田付けにより実装し、その後、温度サイクルや熱衝撃を
行った場合も、導電性樹脂層で応力を吸収できるため、
積層体にクラックが発生することを防ぐことができた。Even when the monolithic ceramic capacitor is mounted on the circuit board by soldering and then subjected to a temperature cycle or thermal shock, the conductive resin layer can absorb the stress.
It was possible to prevent the occurrence of cracks in the laminate.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記積
層セラミックコンデンサによれば、下地導体膜の焼き付
け時に、Cu単体とガラス成分とは互いに濡れ性が不十
分であり、Cuとガラスの分布が不均一になっていた。
このため、下地導体膜の焼き付け時の応力が部分的に差
異が生じ、温度サイクル試験や熱衝撃試験の条件が厳し
くなった場合、クラックが発生することがあった。However, according to the above-mentioned multilayer ceramic capacitor, when the base conductor film is baked, the wettability between the simple substance of Cu and the glass component is insufficient, and the distribution of Cu and glass is uneven. It was.
For this reason, the stress at the time of baking the underlying conductor film partially differs, and cracks may occur when the conditions of the temperature cycle test and the thermal shock test become strict.
【0007】本発明は、上記課題に鑑みて案出されたも
のであり、その目的は、温度サイクルや熱衝撃の条件が
厳しくなった場合も、積層体にクラックが発生しない高
品質かつ高信頼性の積層セラミックコンデンサを提供す
ることにある。The present invention has been devised in view of the above problems, and an object thereof is high quality and high reliability in which cracks do not occur in a laminated body even when the conditions of temperature cycle and thermal shock become severe. To provide a monolithic ceramic capacitor having excellent properties.
【0008】[0008]
【課題を解決するための手段】本発明の積層セラミック
コンデンサは、NiまたはCuを主成分とする内部電極
層を有する誘電体層を交互に積層してなる積層体と、積
層体の両端面に前記内部電極層と接続する外部電極を形
成してなる積層セラミックコンデンサにおいて、前記外
部電極は、積層体内側から、少なくともCuとNiとの
合金及びガラス成分を含有する下地導体膜と、Cu、N
i、Agの少なくとも1種以上を含有する導電性樹脂層
と、メッキ層とを順次積層してなることを特徴とする。A monolithic ceramic capacitor of the present invention comprises a laminated body formed by alternately laminating dielectric layers having internal electrode layers containing Ni or Cu as a main component, and both end faces of the laminated body. In a monolithic ceramic capacitor formed by forming an external electrode connected to the internal electrode layer, the external electrode includes a base conductor film containing at least an alloy of Cu and Ni and a glass component from the inside of the laminate, and Cu, N.
It is characterized in that a conductive resin layer containing at least one of i and Ag and a plating layer are sequentially laminated.
【0009】好ましくは、前記下地導体膜は、CuとN
iとの重量比率95:5〜25:75の範囲にあること
を特徴とする。Preferably, the base conductor film is made of Cu and N.
The weight ratio with i is in the range of 95: 5 to 25:75.
【作用】本発明によれば、積層体の両端面にCuとNi
との合金及びガラス成分よりなる下地導体膜を形成して
も、Cu単体を用いた場合より、金属成分とガラス成分
との濡れ性が良好になる。このため、下地導体膜中での
金属成分とガラス成分との分布が均一となって、焼き付
け時に発生する応力が下地導体膜全体で均一となる。こ
のため、回路基板に半田実装後、温度サイクル試験や熱
衝撃試験を行っても、積層体にクラックが発生したり、
外部電極が剥離したりすることがなく、回路基板との固
着強度にも優れ、その結果、高品質かつ長期信頼性の積
層セラミックコンデンサを提供することができる。According to the present invention, Cu and Ni are formed on both end faces of the laminate.
Even if the base conductor film made of the alloy and the glass component is formed, the wettability between the metal component and the glass component becomes better than when Cu alone is used. Therefore, the distribution of the metal component and the glass component in the underlying conductor film becomes uniform, and the stress generated during baking becomes uniform in the entire underlying conductor film. Therefore, after soldering on the circuit board, even if a temperature cycle test or a thermal shock test is performed, cracks may occur in the laminate,
It is possible to provide a monolithic ceramic capacitor having high quality and long-term reliability, since the external electrodes are not peeled off and the adhesion strength to the circuit board is excellent.
【0010】また、下地導体膜は、CuとNiとの重量
比率95:5〜25:75の範囲とすることにより、特
に焼き付け時の金属成分とガラス成分との濡れ性が良好
になり、積層セラミックコンデンサと回路基板との固着
強度をさらに増大させることができる。By setting the weight ratio of Cu to Ni of the base conductor film in the range of 95: 5 to 25:75, the wettability between the metal component and the glass component becomes particularly good during baking, and the lamination is achieved. The bonding strength between the ceramic capacitor and the circuit board can be further increased.
【0011】[0011]
【発明の実施の形態】以下、本発明の積層セラミックコ
ンデンサを図面に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION A laminated ceramic capacitor of the present invention will be described below with reference to the drawings.
【0012】図1は、本発明の積層セラミックコンデン
サの外観斜視図である。図2は、図1の積層セラミック
コンデンサの断面図である。FIG. 1 is an external perspective view of the monolithic ceramic capacitor of the present invention. FIG. 2 is a sectional view of the monolithic ceramic capacitor of FIG.
【0013】図において、10は積層セラミックコンデ
ンサ、1は積層体、2は誘電体層、3、4は内部電極
層、5、6は外部電極である。In the figure, 10 is a monolithic ceramic capacitor, 1 is a laminated body, 2 is a dielectric layer, 3 and 4 are internal electrode layers, and 5 and 6 are external electrodes.
【0014】誘電体層2は、チタン酸バリウム(BaT
iO3)等を主成分とする非還元性誘電体材料からな
り、その厚みは高容量化のために5〜10μmとしてい
る。この誘電体層2は、その形状は2.0mm×1.2
mm等であり、図上、上方向に積層して積層体1が構成
される。なお、誘電体層2の形状、厚み、積層数は容量
値によって任意に変更することができる。The dielectric layer 2 is made of barium titanate (BaT).
It is made of a non-reducing dielectric material containing iO 3 ) or the like as its main component, and its thickness is set to 5 to 10 μm for high capacity. This dielectric layer 2 has a shape of 2.0 mm × 1.2
mm or the like, and the laminated body 1 is configured by laminating in the upward direction in the drawing. The shape, thickness, and number of stacked layers of the dielectric layer 2 can be arbitrarily changed depending on the capacitance value.
【0015】内部電極層3、4は、単一の金属成分であ
るNiまたはCuを主成分とする材料から構成され、そ
の厚みは0.5〜2μmとしている。そして、誘電体層
2の積層方向に隣接しあう2つの内部電極層3、4は、
互いに積層体1の異なる端面側に延出し、各々異なる外
部電極5、6に接続されている。The internal electrode layers 3 and 4 are made of a material whose main component is Ni or Cu, which is a single metal component, and the thickness thereof is 0.5 to 2 μm. The two internal electrode layers 3 and 4 that are adjacent to each other in the stacking direction of the dielectric layer 2 are
They extend to different end face sides of the laminated body 1 and are connected to different external electrodes 5 and 6, respectively.
【0016】外部電極5、6は、それぞれ積層体1側か
ら、下地導体膜5a、6a、導電性樹脂層5b、6b、
Niメッキ層5c、6c、SnまたはSn−Pb等のメ
ッキ層5d、6dを順次積層して構成される。The external electrodes 5 and 6 are, from the laminated body 1 side, respectively, underlying conductor films 5a and 6a, conductive resin layers 5b and 6b, and
The Ni plating layers 5c and 6c and the plating layers 5d and 6d such as Sn or Sn-Pb are sequentially laminated.
【0017】下地導体膜5a、6aは、CuとNiとの
重量比率95:5〜25:75の範囲にある金属成分
と、ホウケイ酸亜鉛等のホウケイ酸ガラスを含む導電ペ
ーストの塗布・焼き付けによって形成される。The underlying conductor films 5a and 6a are formed by applying and baking a conductive paste containing a metal component having a weight ratio of Cu and Ni in the range of 95: 5 to 25:75 and borosilicate glass such as zinc borosilicate. It is formed.
【0018】導電性樹脂層5b、6bは、エポキシ樹
脂、フェノール樹脂、アクリル樹脂等の熱硬化性樹脂
に、Cu、Ni、Ag等の導電性粉末が含有させて構成
されている。The conductive resin layers 5b and 6b are made of a thermosetting resin such as an epoxy resin, a phenol resin or an acrylic resin, and conductive powder such as Cu, Ni or Ag contained therein.
【0019】上記導電性樹脂層5b、6b上には半田食
われが生じ難い材料からなるNiメッキ層5c、6cが
形成され、さらにスズ(Sn)または半田(Sn−Pb
合金)等の材料からなるスズまたは半田のメッキ層(以
下、スズ系層と略記する)5d、6dが形成されてい
る。On the conductive resin layers 5b and 6b, Ni plating layers 5c and 6c made of a material in which solder erosion is unlikely to occur are formed, and tin (Sn) or solder (Sn-Pb) is further formed.
Plated layers of tin or solder (hereinafter abbreviated as tin-based layers) 5d and 6d made of a material such as alloy) are formed.
【0020】以下、本発明の積層セラミックコンデンサ
10の製造方法について説明する。The method of manufacturing the monolithic ceramic capacitor 10 of the present invention will be described below.
【0021】まず、誘電体層2となるセラミックグリー
ンシートの所定の領域に、内部電極層3、4となる金属
粉末を含有する導電ペーストをスクリーン印刷で形成す
る。First, a conductive paste containing a metal powder to be the internal electrode layers 3 and 4 is formed by screen printing on a predetermined region of the ceramic green sheet to be the dielectric layer 2.
【0022】そして、このようなセラミックグリーンシ
ートを、内部電極層3、4が互いに対向し、且つ内部電
極層3、4が互いに異なる端面に延出するように所定の
積層枚数重ねた後、切断して積層体1とし、所定の雰囲
気、温度、時間を加えて焼成する。これにより、積層体
1の一対の端面には、内部電極層3、4が露出してい
る。Then, a predetermined number of such ceramic green sheets are stacked so that the internal electrode layers 3 and 4 face each other and the internal electrode layers 3 and 4 extend to different end faces, and then cut. Then, the laminated body 1 is obtained, and the laminated body 1 is fired by adding a predetermined atmosphere, temperature and time. As a result, the internal electrode layers 3 and 4 are exposed at the pair of end faces of the laminated body 1.
【0023】次に、上記積層体1の両端面に外部電極
5、6を形成する。具体的には、まず積層体1の表面に
下地導体膜5a、6aを形成する。Next, external electrodes 5 and 6 are formed on both end faces of the laminate 1. Specifically, first, the underlying conductor films 5a and 6a are formed on the surface of the laminated body 1.
【0024】下地導体膜5a、6aは、Cu粉末とNi
粉末との混合粉末、ホウ珪酸亜鉛系のガラス粉末、アク
リル系有機バインダ樹脂、及びテルピネオール等の有機
溶剤とを混合した導電性ペーストを積層体1の両端にデ
ィップ法により塗布し100〜150℃で乾燥後、窒素
雰囲気中で、750〜850℃で焼き付けて形成され
る。ここで金属粉末としてCu粉末とNi粉末との混合
粉末を用いているため、下地導体膜5a、6aにはCu
とNiの合金が形成され、従来のようにCu粉末単体で
下地導体膜5a、6aを形成した場合に比較して、温度
サイクル試験や熱衝撃試験で生じる熱応力を均一にする
ことができる。The base conductor films 5a and 6a are made of Cu powder and Ni.
A conductive paste prepared by mixing a mixed powder with a powder, a zinc borosilicate glass powder, an acrylic organic binder resin, and an organic solvent such as terpineol is applied to both ends of the laminate 1 by a dipping method, and at 100 to 150 ° C. After drying, it is formed by baking at 750 to 850 ° C. in a nitrogen atmosphere. Here, since the mixed powder of Cu powder and Ni powder is used as the metal powder, Cu is used for the underlying conductor films 5a and 6a.
An alloy of Ni and Ni is formed, and the thermal stress generated in the temperature cycle test or the thermal shock test can be made uniform as compared with the case where the underlying conductor films 5a and 6a are formed by using the Cu powder alone as in the related art.
【0025】そして、下地導体膜5a、6aの表面に導
電性のエポキシ系熱硬化性樹脂層5b、6bを塗布、乾
燥、硬化の各工程を順次経て形成する。Then, conductive epoxy thermosetting resin layers 5b and 6b are formed on the surfaces of the base conductor films 5a and 6a by sequentially applying, drying and curing steps.
【0026】このような導電性樹脂ペーストは従来周知
の手段、たとえばスクリーン印刷、ディッピング等によ
って塗布し、付着させる。次に、80〜140℃の温度
にて仮乾燥させ、その後、ペースト中の溶媒成分を完全
に除去するために60〜120℃の温度雰囲気で15〜
90分間脱溶媒をおこなう。次に、150〜250℃の
温度にて30〜120分間加熱することで、硬化させ、
導電性のエポキシ系熱硬化性樹脂層を形成する。Such a conductive resin paste is applied and attached by a conventionally known means such as screen printing or dipping. Next, it is temporarily dried at a temperature of 80 to 140 ° C., and thereafter, in a temperature atmosphere of 60 to 120 ° C. for 15 to 15 to completely remove the solvent component in the paste.
Desolvation is performed for 90 minutes. Next, it is cured by heating at a temperature of 150 to 250 ° C. for 30 to 120 minutes,
A conductive epoxy thermosetting resin layer is formed.
【0027】上記導電性樹脂層5b、6b上に、Niメ
ッキ層5c、6cを電解メッキ等で形成し、さらに同様
に、スズ系層5d、6dを電解メッキ等で形成する。Ni plating layers 5c and 6c are formed on the conductive resin layers 5b and 6b by electrolytic plating or the like, and tin-based layers 5d and 6d are similarly formed by electrolytic plating or the like.
【0028】このようにして、図1に示すような積層セ
ラミックコンデンサ10が得られる。In this way, the monolithic ceramic capacitor 10 as shown in FIG. 1 is obtained.
【0029】なお、本発明は以上の実施形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲で種々
の変更・改良を加えることは何ら差し支えない。The present invention is not limited to the above embodiment, and various modifications and improvements may be added without departing from the gist of the present invention.
【0030】例えば、導電性樹脂層5b、6bの表面を
Ag、Au、Pd、Pt等の酸化しにくいメッキ層で被
覆しても良い。このことにより、導電性樹脂ペーストに
よる接続固定に有する加熱処理や、環境条件による経時
変化や湿度の影響における外部電極5、6の酸化を防ぐ
ことができ、外部回路との電気的接続が良好になる。For example, the surfaces of the conductive resin layers 5b and 6b may be covered with a plating layer of Ag, Au, Pd, Pt or the like which is hard to oxidize. As a result, it is possible to prevent the heat treatment involved in the connection and fixing with the conductive resin paste and the oxidation of the external electrodes 5 and 6 due to the change over time due to environmental conditions and the influence of humidity, and the electrical connection with the external circuit is improved. Become.
【0031】[0031]
【実施例】上述の下地導体膜5a、6aは、Cu及びN
iの合金を主成分としてガラスフリットを含む導電ぺー
ストを10〜50μmの厚みで塗布し、乾燥し、焼き付
けた。EXAMPLE The above-mentioned base conductor films 5a and 6a are made of Cu and N.
A conductive paste containing a glass frit as a main component of the alloy i was applied in a thickness of 10 to 50 μm, dried and baked.
【0032】次に、エポキシ系熱硬化性導電性樹脂材料
からなる導電性樹脂層5b、6bは、Cu系フィラーを
エポキシ系樹脂に分散した導電性樹脂ペーストより形成
され、この導電性樹脂ペーストを下地導体膜5a、6a
表面に20〜100μmの厚みで塗布後、乾燥し、次に
80〜120℃の温度にて脱溶剤し、その後150〜2
00℃の温度で硬化させて形成した。Next, the conductive resin layers 5b and 6b made of an epoxy thermosetting conductive resin material are formed from a conductive resin paste in which a Cu filler is dispersed in an epoxy resin. Base conductor film 5a, 6a
After being coated on the surface in a thickness of 20 to 100 μm, it is dried, then desolvated at a temperature of 80 to 120 ° C., and then 150 to 2
It was formed by curing at a temperature of 00 ° C.
【0033】次に、導電性樹脂層5b、6b表面に、N
iメッキ層5c、6cを電解メッキで形成し、このNi
メッキ層5c、6cの表面に、スズ系層5d、6dを電
解メッキで形成し、そして、規格にもとづく全長2.0
mmの2012型積層セラミックコンデンサを得た。Next, on the surfaces of the conductive resin layers 5b and 6b, N
i plating layers 5c and 6c are formed by electrolytic plating.
The tin-based layers 5d and 6d are formed on the surfaces of the plated layers 5c and 6c by electrolytic plating, and the total length is 2.0 based on the standard.
A mm type 2012 multilayer ceramic capacitor was obtained.
【0034】また、導電性樹脂層5b、6bは、Ni系
フィラーまたはAg系フィラーをエポキシ系樹脂に分散
した導電性樹脂ペーストを用い、積層セラミックコンデ
ンサ10を同様に作製した。For the conductive resin layers 5b and 6b, a conductive resin paste in which a Ni-based filler or an Ag-based filler is dispersed in an epoxy-based resin is used, and the monolithic ceramic capacitor 10 is similarly manufactured.
【0035】さらに、比較例として、導電性樹脂層5
b、6bが存在しない積層セラミックコンデンサ10を
同様に作製した。Further, as a comparative example, the conductive resin layer 5
A monolithic ceramic capacitor 10 without b and 6b was prepared in the same manner.
【0036】このようにして作成された本発明の試料
と、比較のために作成された比較例を用いて評価試験を
行った。その結果を表1に示す。An evaluation test was conducted using the sample of the present invention thus prepared and a comparative example prepared for comparison. The results are shown in Table 1.
【0037】[0037]
【表1】 [Table 1]
【0038】表のように、内部電極層3、4の金属をN
i、Cuに変化させるとともに、下地導体膜5a、6a
内のCuとNiの比率を変化させ、また樹脂電極層5
b、6bの金属をCu、Ni、Agに変化させた本発明
の試料(試料番号2〜6、9〜13、16〜20、22
〜25)を作製した。比較例として、下地導体膜5a、
6aの金属成分がCuまたはNi単体である試料(試料
番号1、7、8、14、15、21)を作製した。ま
た、導電性樹脂層5b、6bを形成せずに、下地導体膜
5a、6aの上に直接Niメッキ層5c、6c及びスズ
系層5d、6dを形成した試料(試料番号26〜29)
を作製した。As shown in the table, the metal of the internal electrode layers 3 and 4 is changed to N.
i, Cu and the underlying conductor films 5a and 6a
By changing the ratio of Cu and Ni in the resin electrode layer 5
Samples of the present invention in which the metal of b, 6b was changed to Cu, Ni, Ag (Sample Nos. 2 to 6, 9 to 13, 16 to 20, 22)
~ 25) were produced. As a comparative example, the base conductor film 5a,
Samples (sample numbers 1, 7, 8, 14, 15, 21) in which the metal component of 6a was Cu or Ni alone were prepared. Also, samples (Sample Nos. 26 to 29) in which the Ni plating layers 5c and 6c and the tin-based layers 5d and 6d were directly formed on the underlying conductor films 5a and 6a without forming the conductive resin layers 5b and 6b.
Was produced.
【0039】これらの試料に対し、温度サイクル耐久性
試験を行った。A temperature cycle durability test was conducted on these samples.
【0040】温度サイクル耐久性試験は、試料を−55
℃の雰囲気に30分間保持後、150℃の雰囲気に30
分間保持する、冷却/加熱サイクルを1000サイクル
及び2000サイクル行って、それぞれ試験前後の固着
強度を調べた。評価基準として、固着強度が2.5k
g.f以上であるものを二重丸印の優良品、2.0〜
2.5kg.fであるものを丸印の良好品、2.0k
g.f未満であるものをばつ印の不良品とした。また、
試験後に試料50個を切断して、積層体1にクラックの
発生した個数を調べた。For the temperature cycle durability test, the sample was tested at -55.
After holding in the atmosphere of ℃ for 30 minutes, in the atmosphere of 150 ℃ 30
The cooling / heating cycle of holding for 1000 minutes was performed 1000 times and 2000 cycles to examine the bonding strength before and after the test. Adhesion strength is 2.5k as an evaluation standard
g. Goods with f or more are excellent products with double circles, 2.0 ~
2.5 kg. Items with f are good products with a circle, 2.0k
g. Those with a value of less than f were regarded as defective products with a cross mark. Also,
After the test, 50 samples were cut and the number of cracks generated in the laminate 1 was examined.
【0041】表から明らかなとおり、外部電極5、6
が、CuとNiとの合金を含有する下地導体膜5a、6
aと、下地導体膜5a、6a表面に形成された導電性樹
脂層5b、6bとを有する本実施例(試料番号2〜6、
9〜13、16〜20、22〜25)では、2000サ
イクルの温度サイクル耐久性試験を行っても、固着強度
は2.0kg.f以上となり、また積層体1にクラック
が発生しなかった。特に、CuとNiとの重量比率9
5:5〜25:75の範囲にある場合(試料番号2〜
5、9〜12、16〜19、22〜25)、固着強度が
2.5kg.f以上の優良品となった。これらの結果
は、内部電極層3、4がNi、Cuのいずれの場合にお
いても、また導電性樹脂層5b、6b中の金属成分がC
u、Ni、Agの内のいずれの場合においても、同じだ
った。As is apparent from the table, the external electrodes 5, 6
Of the base conductor films 5a, 6 containing an alloy of Cu and Ni
a and the conductive resin layers 5b and 6b formed on the surfaces of the underlying conductor films 5a and 6a, respectively (the sample numbers 2 to 6,
9 to 13, 16 to 20, 22 to 25), the fixing strength was 2.0 kg. It was not less than f and no crack was generated in the laminate 1. In particular, the weight ratio of Cu and Ni is 9
In the range of 5: 5 to 25:75 (Sample No. 2 to
5, 9-12, 16-19, 22-25), and the fixing strength is 2.5 kg. It was a good product of f or higher. These results show that the metal components in the conductive resin layers 5b and 6b are C when the internal electrode layers 3 and 4 are both Ni and Cu.
The same was true in any of u, Ni, and Ag.
【0042】これに対し、下地導体膜5a、6aの金属
成分がCu単体である比較例(試料番号1、8、15)
では、1000サイクル後にはクラックが発生しなかっ
たが、2000サイクル後にはクラックが試料50個中
2〜5個発生した。これは、導電性樹脂層5b、6b中
の金属成分がCu、Ni、Agの内のいずれの場合にお
いても、同じだった。On the other hand, Comparative Examples (Sample Nos. 1, 8, 15) in which the metal component of the underlying conductor films 5a, 6a is Cu alone.
No cracks were generated after 1000 cycles, but 2 to 5 cracks were generated in 50 samples after 2000 cycles. This was the same in any case where the metal component in the conductive resin layers 5b and 6b was Cu, Ni or Ag.
【0043】一方、下地導体膜5a、6aの金属成分が
Ni単体である比較例(試料番号7、14、21)で
は、1000サイクル後にはクラックが試料50個中1
〜3個発生し、2000サイクル後にはクラックが試料
50個中8〜10個発生した。これは、導電性樹脂層5
b、6b中の金属成分がCu、Ni、Agの内のいずれ
の場合においても、同じだった。On the other hand, in the comparative example (Sample Nos. 7, 14, and 21) in which the metal component of the underlying conductor films 5a and 6a was Ni alone, cracks were observed in 1 of 50 samples after 1000 cycles.
.About.3, and after 2000 cycles, 8 to 10 cracks in 50 samples. This is the conductive resin layer 5
The same was true in the cases where the metal components in b and 6b were Cu, Ni and Ag.
【0044】さらに、導電性樹脂層5b、6bを形成せ
ずに、下地導体膜5a、6aの上に直接Niメッキ層5
c、6c及びスズ系層5d、6dを形成した試料(試料
番号26〜29)は、1000サイクル後に、クラック
が試料50個中21〜26個発生した。また、2000
サイクル後には、クラックが試料50個中50個発生し
た。これは、CuとNiの比率を変化させても、同じだ
った。Further, the Ni plating layer 5 is directly formed on the underlying conductor films 5a and 6a without forming the conductive resin layers 5b and 6b.
In the samples (Sample Nos. 26 to 29) on which c, 6c and the tin-based layers 5d and 6d were formed, 21 to 26 cracks occurred in 50 samples after 1000 cycles. Also, 2000
After the cycle, 50 of 50 cracks were generated. This was the same even if the ratio of Cu and Ni was changed.
【0045】これらの結果から、外部電極5、6が、C
uとNiとの合金及びガラス成分を含有する下地導体膜
5a、5bと、その表面に形成された導電性樹脂層5
b、6bと、その表面に形成されたNiメッキ層5c〜
5d、スズ系層6c〜6dとを順次積層してなる本発明
の積層セラミックコンデンサ10は、2000サイクル
の温度サイクル耐久性試験を行っても、固着強度は2.
0kg.f以上となり、また積層体1にクラックが発生
しないことがわかる。From these results, the external electrodes 5 and 6 are C
Base conductor films 5a and 5b containing an alloy of u and Ni and a glass component, and a conductive resin layer 5 formed on the surfaces thereof.
b and 6b, and the Ni plating layer 5c formed on the surface thereof.
5d and the tin-based layers 6c to 6d are sequentially laminated, the laminated ceramic capacitor 10 of the present invention has a fixing strength of 2. even after a 2000-cycle temperature cycle durability test.
0 kg. It can be seen that the value is not less than f and that cracks do not occur in the laminate 1.
【0046】[0046]
【発明の効果】以上、本発明の積層セラミックコンデン
サによれば、積層体の両端面にCuとNiとの合金及び
ガラス成分よりなる下地導体膜を形成しても、Cu単体
を用いた場合より、金属成分とガラス成分との濡れ性が
良好になる。このため、下地導体膜中での金属成分とガ
ラス成分との分布が均一となって、焼き付け時に発生す
る応力が下地導体膜全体で均一となる。このため、回路
基板に半田実装後、温度サイクル試験や熱衝撃試験を行
っても、積層体にクラックが発生したり、外部電極が剥
離したりすることがなく、回路基板との固着強度にも優
れ、その結果、高品質かつ長期信頼性の積層セラミック
コンデンサを提供することができる。As described above, according to the monolithic ceramic capacitor of the present invention, even when a base conductor film made of an alloy of Cu and Ni and a glass component is formed on both end faces of the laminated body, it is more than in the case of using only Cu. The wettability between the metal component and the glass component is improved. Therefore, the distribution of the metal component and the glass component in the underlying conductor film becomes uniform, and the stress generated during baking becomes uniform in the entire underlying conductor film. For this reason, even if a temperature cycle test or a thermal shock test is performed after solder mounting on the circuit board, the laminated body is not cracked or the external electrodes are not peeled off, and the adhesion strength to the circuit board is also improved. As a result, it is possible to provide a high-quality and long-term reliable multilayer ceramic capacitor.
【図1】本発明の積層セラミックコンデンサの外観斜視
図である。FIG. 1 is an external perspective view of a monolithic ceramic capacitor of the present invention.
【図2】図1の積層セラミックコンデンサの断面図であ
る。2 is a cross-sectional view of the monolithic ceramic capacitor of FIG.
10 積層セラミックコンデンサ 1 積層体 2 誘電体層 3、4 内部電極層 5、6 外部電極 5a、6a 下地導体膜 5b、6b 導電性樹脂層 5c、6c Niメッキ層 5d、6d スズ系層 10 Multilayer ceramic capacitors 1 stack 2 Dielectric layer 3, 4 internal electrode layer 5, 6 External electrode 5a, 6a Base conductor film 5b, 6b conductive resin layer 5c, 6c Ni plating layer 5d, 6d tin-based layer
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E001 AB03 AC04 AC09 AF00 AF06 AH07 AJ03 5E082 AB03 BC23 BC33 EE04 EE23 EE26 EE35 FG06 FG26 GG10 GG11 GG26 GG28 JJ03 JJ12 JJ21 JJ23 PP03 PP08 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 5E001 AB03 AC04 AC09 AF00 AF06 AH07 AJ03 5E082 AB03 BC23 BC33 EE04 EE23 EE26 EE35 FG06 FG26 GG10 GG11 GG26 GG28 JJ03 JJ12 JJ21 JJ23 PP03 PP08
Claims (2)
層を有する誘電体層を交互に積層してなる積層体と、 積層体の両端面に前記内部電極層と接続する外部電極を
形成して成る積層セラミックコンデンサにおいて、 前記外部電極は、積層体側から少なくともCuとNiと
の合金及びガラス成分を含有する下地導体膜と、Cu、
Ni、Agの少なくとも1種以上を含有する導電性樹脂
層とメッキ層とを順次積層してなることを特徴とする積
層セラミックコンデンサ。1. A laminated body in which dielectric layers having internal electrode layers containing Ni or Cu as a main component are alternately laminated, and external electrodes connected to the internal electrode layers are formed on both end faces of the laminated body. In the monolithic ceramic capacitor, the external electrode includes a base conductor film containing at least an alloy of Cu and Ni and a glass component, and Cu,
A monolithic ceramic capacitor comprising a conductive resin layer containing at least one of Ni and Ag and a plating layer, which are sequentially laminated.
比率95:5〜25:75の範囲にあることを特徴とす
る請求項1記載の積層セラミックコンデンサ。2. The multilayer ceramic capacitor according to claim 1, wherein the underlying conductor film has a weight ratio of Cu and Ni in a range of 95: 5 to 25:75.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002124210A JP2003318059A (en) | 2002-04-25 | 2002-04-25 | Multilayer ceramic capacitors |
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| JP2003318059A true JP2003318059A (en) | 2003-11-07 |
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