JP2003303961A - Mos semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of the difficulty in achieving an MOS transistor, having superior breakdown voltage characteristics, since an N- type drain region is formed in a P- type diffusion region in the conventional MOS transistor. <P>SOLUTION: In the MOS transistor 21, the end section of the P- type diffusion region 30, set to be a channel formation region, is formed so that it is positioned in the lower region of a gate electrode. Then, an N-- type epitaxial layer 23 is utilized as the drain region. As a result, a depletion layer formation region, affecting the breakdown voltage characteristics can be widely secured at the side of a drain electrode 38 where a high voltage, is applied, hence a structure, having the high breakdown voltage characteristics can be achieved in the MOS transistor 21. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

An object of the present invention is to realize a high breakdown voltage in a MOS transistor by ensuring a depletion layer forming region on the drain region side rather than the source region side.

[0002]

2. Description of the Related Art In recent years, portable devices such as MDs and CDs are required to have high integration, improved capability and low power consumption. The power MOS transistor shown below as a conventional example is generally used as a battery-driven motor driver IC for portable equipment, for example, MD and CD.
And, it is researched and developed every day aiming at the above-mentioned development theme.

FIG. 10 shows a conventional N-channel MO.
3 is a cross-sectional view of the S transistor 1. FIG.

As shown in the figure, an N-type epitaxial layer having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6.0 μm is formed on the P-type single crystal silicon substrate 2. 3 is formed. Then, the substrate 2 and the epitaxial layer 3 are N-doped by the P + type isolation region 4 penetrating them.
An island region 5 forming the channel type MOS transistor 1 is formed. Then, the substrate 2 and the epitaxial layer 3
A P + type burying layer 6 is formed between and.

In the epitaxial layer 3 of the island region 5, a P− type diffusion region 7 is formed so as to overlap the P + type buried layer 6 at the end. In the P− type diffusion region 7, N− type diffusion regions 8 and 9 serving as a source region and a drain region and a P ++ type diffusion region 10 are formed. Then, in the N− type diffusion regions 8 and 9, N ++ type diffusion regions 11 and 12 respectively serving as extraction regions of the source region and the drain region are formed.

Then, a gate electrode 13, an insulating layer 14, etc. are formed on the surface of the epitaxial layer 3. Through the contact hole formed in the insulating layer 14, the source electrode 1
5, the drain electrode 16 and the back gate electrode 17 are formed, and the N-channel MOS transistor 1 shown in FIG. 10 is completed.

[0007]

As described above, in the conventional MOS transistor 1, a certain voltage is applied to the gate electrode 13 while a voltage higher than that of the source electrode 15 is applied to the drain electrode 16. . Then, an N type channel region is formed in the surface layer of the P − type diffusion region 7 located under the gate electrode 13 and driven. Then, a constant voltage is applied to the P− type diffusion region 7 through the back gate electrode 17 to prevent the parasitic effect.

However, as described above, the conventional MOS
In the transistor 1, the N− type diffusion regions 8 and 9 serving as the source region and the drain region are formed in the P− type diffusion region 7. Therefore, in order to configure the MOS transistor 1, the concentration of the N− type diffusion regions 8 and 9 must be set higher than that of the P− type diffusion region 7. As a result, there is a problem that it is difficult to form the source region and the drain region of the MOS transistor 1. Further, since the N − type diffusion regions 8 and 9 become high-concentration regions to some extent, there is a problem that a depletion layer forming region cannot be secured and it is difficult to obtain a desired breakdown voltage.

Further, as described above, in the conventional MOS transistor 1, the P− type semiconductor substrate 2, the P + type buried layer 6 and the P− type diffusion region 7 are connected to form a P type region. Was there. Then, the back gate electrode 17 was in contact with the P− type diffusion region 7 from the device surface, and a constant voltage was applied. However, the P-type diffusion region 7
Since the substrate 2 and the substrate 2 are connected via the P + type buried layer 6, the back gate voltage and the substrate voltage are constant,
There is a problem that it is difficult to use for multi-functionalization.

[0010]

The present invention has been made in view of the above-mentioned conventional problems. In the MOS semiconductor device of the present invention, a semiconductor substrate of one conductivity type is laminated on at least the surface of the substrate. A reverse conductivity type epitaxial layer, a reverse conductivity type buried layer formed between the substrate and the epitaxial layer, a conductivity type diffusion region serving as a channel forming region in the epitaxial layer, and the epitaxial layer A first diffusion region of opposite conductivity type serving as a source region or a drain extraction region, and a gate electrode made of polycrystalline silicon on the surface of the epitaxial layer, and the diffusion region of one conductivity type serves as a source region. The first conductivity type diffusion region is formed so as to surround only the first opposite conductivity type diffusion region side, and at least the one conductivity type diffusion region is formed. Characterized in that it is formed to include a portion of the part area.

The MOS semiconductor device of the present invention is preferably
A second reverse-conductivity type diffusion region is formed in the epitaxial layer located in the lower region of the gate electrode so as to at least partially overlap with the first reverse-conductivity type diffusion region to be a drain extraction region. The second opposite conductivity type diffusion region is lower in concentration than the first opposite conductivity type diffusion region.

The MOS semiconductor device of the present invention is preferably
The reverse conductivity type buried layer is interposed between the one conductivity type diffusion region and the substrate, and a voltage different from that of the substrate is applied to the one conductivity type diffusion region.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

1 and 2 are examples of cross-sectional views of an N-channel type MOS transistor 21 in the present embodiment.

First, the first embodiment shown in FIG. 1 will be described.

As shown in the figure, on the P-type single crystal silicon substrate 22, for example, a specific resistance of 0.1 to 3.5 Ω · cm,
An N--type epitaxial layer 23 having a thickness of 1.0 to 6.0 μm is formed. Then, in the substrate 22 and the epitaxial layer 23, an island region 25 is formed by a P + type isolation region 24 penetrating both. In the present embodiment, only the island region 25 is shown, but a plurality of other island regions are formed, and for example, similarly, an N-channel type M
An OS transistor, a P-channel type MOS transistor, an NPN type transistor, etc. are formed.

The isolation region 24 is composed of a first isolation region 26 diffused vertically from the surface of the substrate 22 and a second isolation region 27 diffused from the surface of the epitaxial layer 23. Then, the two are connected to separate the epitaxial layer 23 into islands. Further, since the LOCOS oxide film 28 is formed on the P + type isolation region 24, more element isolation is achieved. The structure of the N-channel MOS transistor 21 according to the present invention will be described below.

As shown in the drawing, an N--type epitaxial layer 23 is formed on the substrate 22. An N + type buried layer 29 is formed between the substrate 22 and the epitaxial layer 23. In the epitaxial layer 23, a P− type diffusion region 30 serving as a channel forming region is formed. Then, in the P− type diffusion region 30, a P ++ type diffusion region 33 and an N ++ type diffusion region 31 serving as a source region are formed. On the other hand, in the epitaxial layer 23 in which the P− type diffusion region 30 is not formed, the N ++ type diffusion region 32 to be the drain extraction region is formed. A gate oxide film 34 is formed on the epitaxial layer 23, and a gate electrode 35 made of, for example, polycrystalline silicon (polysilicon) is formed on the gate oxide film 34.

An insulating layer 36 is formed on the surface of the epitaxial layer 23 including the gate electrode 35. A contact hole is formed in the insulating layer 36, and a drain electrode 38 and a source electrode 37 are formed of, for example, aluminum (Al) through the contact hole. Further, P + formed in the P− type diffusion region 30
The back gate electrode 39 is made of, for example, aluminum (Al) and is in contact with the + type diffusion region 33. With this structure, the illustrated MOS transistor 21 is completed.

Then, the MOS transistor 21 of the present invention
The first feature of the P-type diffusion region 30 is as follows.
Is formed so as to be located at least in a part of the lower region of the gate electrode 35.

That is, as explained as the problem of the conventional MOS transistor 1 (see FIG. 10), P-
It was difficult to form the N − type diffusion regions 8 and 9 in the type diffusion region 7 (see FIG. 10) in terms of the impurity concentration. In particular, the concentration of the N− type diffusion regions 8 and 9 is P−.
There is a problem in that it is difficult to obtain a desired pressure resistance by setting the impurity concentration higher than that of the diffusion region 7 of the mold. Therefore,
In the MOS transistor 21 of the present invention, the N--type epitaxial layer 23 is used as a drain region, particularly on the side of the drain electrode 38 to which a high voltage is applied.

Specifically, as shown in the figure, the P-type diffusion region 30 is used as a channel forming region, and is therefore formed so as to be located at least in the lower region of the gate electrode 35. Then, an N ++ type diffusion region 31 is formed as a source region in the P− type diffusion region 30. On the other hand, on the drain electrode 38 side, the P− type diffusion region 30 is not formed, and only the epitaxial layer 23 is formed. The N ++ type diffusion region 32 is used as a drain extraction region in the epitaxial layer 23.
With this structure, the MOS transistor 21 of the present invention can obtain the effects described below.

In the MOS transistor 21 of the present invention, the depletion layer formed from the boundary surface between the P− type diffusion region 30 serving as the channel forming region and the epitaxial layer 23 is MO.
The withstand voltage of the S transistor 21 is affected. Therefore, in the present invention, the drain electrode 38 to which a high voltage is applied is
On the side, the N− type epitaxial layer 23 is used. As a result, in the MOS transistor 21, the depletion layer can be largely expanded from the boundary surface between the P− type diffusion region 30 and the epitaxial layer 23 to the drain region side. On the other hand, since the P− type diffusion region 30 is used on the source region side and the depletion layer spreads largely on the drain region side, the depletion layer does not spread so symmetrically. That is, in the MOS transistor 21 of the present invention, a large depletion layer forming region is secured on the side of the drain electrode 38 to which a high voltage is applied, so that the breakdown voltage can be significantly improved even with the same cell size.

However, in order to secure a depletion layer forming region on the drain electrode 38 side, if the P − type diffusion region 30 is formed on the source region side below the gate electrode 35, the parasitic resistance in the drain region increases. Problem occurs. That is, if the parasitic resistance in the drain region increases, the MOS
The ON resistance at the time of switching the transistor 21 increases. As a result, the power consumption of the MOS transistor 21 also increases.

Therefore, the MOS transistor 21 of the present invention is used.
Then, as shown in FIG. 2, the structure shown in the second embodiment may be employed. The description of the structure of the second embodiment is made by referring to the above description of the first embodiment, and the description is omitted here.

As shown in the figure, the structural difference between the first embodiment and the second embodiment is that, in the second embodiment, at least a part of the N ++ type diffusion region 32 which becomes the drain extraction region and That is, the N− type diffusion region 40 is formed in the lower region of the gate electrode 35 so as to be overlapped with each other. That is, the N− type diffusion region 40 is formed in the epitaxial layer 23 which will be the drain region, and the impurity concentration in the drain region is slightly increased. As a result, the parasitic resistance in the drain region can be reduced, and the MOS transistor 21
The ON resistance at the time of switching can also be reduced. Since the N− type diffusion region 40 has a lower concentration than the N ++ type diffusion region 32, the formation region of the depletion layer is somewhat reduced, but the MOS transistor 2
It does not become a factor of deteriorating the pressure resistance of No. 1.

As described above, the MOS transistor 21 of the present invention can have a structure as shown in FIG. 1 when the withstand voltage is required. On the other hand, for the purpose of balancing the withstand voltage of the MOS transistor 21 and the ON resistance at the time of switching, a structure as shown in FIG. 2 can be used. Furthermore, in the structure of FIG. 1 and FIG.
The depletion layer forming region is different depending on the position where the end of the − type diffusion region 30 is formed in the lower region of the gate electrode 35. Therefore, in the MOS transistor 21 of the present invention, the formation region of the P− type diffusion region 30 can be formed in consideration of the balance between the breakdown voltage and the ON resistance during switching.

Here, in the first embodiment, the N ++ type diffusion region 32 serving as the drain extraction region is formed so as not to be located in the region below the gate electrode 35. This is when the MOS transistor 21 is OFF, that is,
When the gate electrode 35 is at the ground voltage and the drain electrode is at the high voltage, the surface of the epitaxial layer 23 in the lower region of the gate electrode 35 is P-type inverted. Then, the P-type inversion region and the N ++ type diffusion region 32 are in contact with each other, so that the withstand voltage characteristic cannot be obtained. Therefore, as described above, in the first embodiment, the N− type epitaxial layer 23 is located between the P type inversion and the N ++ type diffusion region 32 to prevent the breakdown voltage characteristic from being deteriorated. In addition, in the second embodiment, the above-mentioned problem can be solved by the N− type diffusion region 40.

Next, the second characteristic of the MOS transistor 21 of the present invention is that it has a P-type diffusion region 30 and a P-type diffusion region.
The N + type buried layer 29 is formed between the − type substrate 22.

Then, as shown in the figure, a P-type diffusion region 3 is formed.
A back gate electrode 39 is in contact with 0 from the element surface through the P ++ type diffusion region 33. The parasitic effect is prevented by applying a constant voltage from the back gate electrode 39 to the P− type diffusion region 30. And
As described above, the P− type diffusion region 30 and the P− type substrate 22 are provided.
And are separated from each other by an N + type buried layer 29. Therefore, different voltages can be applied to the P− type diffusion region 30 and the P− type substrate 22, respectively.
As a result, the MOS transistor 21 of the present invention can be made multifunctional.

The present invention is not limited to this embodiment, and various modifications can be made without departing from the gist of the present invention.

Next, with reference to FIGS. 3 to 9, the N-channel MO which is the first embodiment of the present invention shown in FIG.
A method of manufacturing the S transistor 21 will be described below. In the following description, the same components as the components described in the structure of the MOS transistor shown in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 3, a P-type single crystal silicon substrate 22 is prepared, and the surface of the substrate 22 is thermally oxidized to form a silicon oxide film on the entire surface, for example, 0.03 to 0.
It is formed to about 05 μm. After that, the oxide film corresponding to the buried layer 29 is photo-etched by a known photolithography technique to form a selective mask. Then, an N-type impurity, for example, phosphorus (P) is added at an accelerating voltage of 20 to 65 keV,
Ion implantation is performed at a dose of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² to diffuse the ions.

Next, as shown in FIG. 4, an opening is formed on the silicon oxide film formed in FIG. 3 in the portion of the isolation region 24 where the first isolation region 26 is to be formed by a known photolithography technique. A photoresist is formed as a selective mask. Then, a P-type impurity, such as boron (B), is accelerated at an acceleration voltage of 60 to 100 keV, and the introduction amount is 1.0 ×
Ion implantation is performed at 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed.

Next, as shown in FIG. 5, the silicon oxide film formed in FIG. 3 is completely removed, and the substrate 22 is placed on the susceptor of the epitaxial growth apparatus. Then, the substrate 22 is heated to a high temperature of, for example, about 1000 ° C. by lamp heating, and SiH ₂ Cl ₂ gas and H ₂ are introduced into the reaction tube.
Introduce gas. Thereby, on the substrate 22, for example, a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6.
The epitaxial layer 23 of about 0 is grown. afterwards,
The surface of the epitaxial layer 23 is thermally oxidized to form a silicon oxide film, for example, about 0.03 to 0.05 μm.
Then, after forming the P− type diffusion region 30, a photoresist having an opening formed in a portion of the isolation region 24 where the second isolation region 27 is to be formed is formed by a known photolithography technique as a selection mask. Then, a P-type impurity, for example, boron (B) is added to the accelerating voltage 60 to 100 ke
V, ion implantation is performed at a dose of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² , and diffusion is performed. Then, the photoresist is removed.

Next, as shown in FIG. 6, first, a LOCOS oxide film 28 is formed in a desired region of the epitaxial layer 23. Although not shown, the surface of the epitaxial layer 23 is thermally oxidized to form a silicon oxide film on the entire surface, for example, 0.
The thickness is about 03 to 0.05 μm. Then, a silicon nitride film is formed on the oxide film, for example, 0.05 to 0.2 μm.
After forming approximately, the silicon nitride film is selectively removed so that an opening is formed in a portion where the LOCOS oxide film 28 is formed. Then, using this silicon nitride film as a mask, for example, 800 to 120 is applied from above the silicon oxide film.
An oxide film is attached by steam oxidation at about 0 ° C. And
At the same time, heat treatment is applied to the entire substrate 22 to form the LOCOS oxide film 28. In particular, LO is formed on the P + type isolation region 24.
By forming the COS oxide film 28, more element isolation is achieved. Here, the LOCOS oxide film 28 is, for example,
It is formed to have a thickness of about 0.5 to 1.0 μm.

Next, a silicon oxide film is formed on the surface of the epitaxial layer 23, for example, about 0.01 to 0.20 μm. Then, this silicon oxide film is used as the gate oxide film 34 below the gate electrode 35. Next, although not shown, a polysilicon film is deposited on the silicon oxide film to have a thickness of, for example, about 0.2 to 0.3 μm. Then, an N-type impurity such as phosphorus (P) is introduced into the polysilicon film at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 1.
Ion implantation is performed at 0 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, the polysilicon film other than the region where the gate electrode 35 is formed is removed by a known photolithography technique. At this time, the P + type second buried layer 27 simultaneously diffuses.

Next, as shown in FIG. 7, formed in FIG.
A well-known photolithography using a silicon oxide film
To the part where the P ++ type diffusion region 33 is formed by
Using the photoresist with the opening as a selection mask
Form. And a P-type impurity such as boron (B)
Acceleration voltage 60 to 100 keV, introduction amount 1.0 × 10 ¹³
~ 1.0 x 10¹⁵/ Cm²Ion implantation is carried out and diffused.
Then, the photoresist is removed.

Next, as shown in FIG. 8, using the silicon oxide film formed in FIG. 6, using the known photolithography technique, a photo in which an opening is provided in the portion where the N ++ type diffusion regions 31 and 32 are formed. A resist is formed as a selective mask. Then, an N-type impurity, for example, phosphorus (P) is added at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 1
Ions are implanted at 0 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffused. Then, the photoresist is removed.

Next, as shown in FIG. 9, BPSG is formed as an insulating layer 36 on the epitaxial layer 23 or the like, for example, on the entire surface.
(Boron Phospho Silicate G
(lass) film, SOG (Spin On Glass)
Deposit a film, etc. After that, a contact hole for forming an external electrode is formed by a known photolithography technique.

Finally, a back gate electrode 39, a source electrode 37 and a drain electrode 38 made of, for example, Al are formed through the contact hole formed in the insulating layer 36, and the N channel type MOS transistor 21 shown in FIG.
Is completed.

In the above-described embodiment, the case where only the N-channel type MOS transistor is formed has been described, but the N-channel type MOS transistor is similarly formed in the other island regions.
A transistor, an NPN transistor, etc. can be formed at the same time. Besides, various modifications can be made without departing from the scope of the present invention.

[0043]

According to the present invention, firstly, in the MOS semiconductor device, the end of the P-type diffusion region, which becomes the channel forming region so as to surround the source region, is formed at least in a part of the gate electrode lower region. It is formed so as to be located. And
It is characterized in that an N--type epitaxial layer is used as the drain region. As a result, a wide depletion layer forming region can be secured on the side of the drain electrode to which a high voltage is applied. As a result, MOS with high withstand voltage characteristics
A semiconductor device can be realized.

Secondly, in the MOS semiconductor device of the present invention,
It is characterized in that an N− type diffusion region is formed in the epitaxial layer to be the drain region so as to at least partially overlap with the N ++ type diffusion region to be the drain extraction region. As a result, the parasitic resistance in the drain region can be reduced, and the ON resistance during switching of the MOS semiconductor device can also be reduced.
As a result, it is possible to realize a MOS semiconductor device capable of reducing the ON resistance during switching while maintaining a constant withstand voltage.

Thirdly, in the MOS semiconductor device of the present invention,
It is characterized in that the P− type diffusion region and the P− type substrate are separated by an N + type buried layer. As a result, different voltages can be applied to the P− type diffusion region and the P− type substrate, respectively. As a result, MOS
It is possible to realize a multifunctional semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a first embodiment of a MOS semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a second embodiment of a MOS semiconductor device of the present invention.

FIG. 3 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross sectional view illustrating the method for manufacturing the MOS semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating a conventional method for manufacturing a MOS semiconductor device.

Continued front page    F-term (reference) 5F140 AA00 AA25 AA30 AC09 AC21                       BA01 BA16 BC06 BD05 BF01                       BF04 BF42 BG27 BG32 BH30                       BH43 BH47 BH50 BJ01 BJ05                       BJ23 CB00 CB01 CC03 CC07                       CC16 CD02

Claims (3)

[Claims] 1. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer laminated on at least the surface of the substrate, and a reverse conductivity type buried layer formed between the substrate and the epitaxial layer. A diffusion region of one conductivity type that serves as a channel formation region in the epitaxial layer, a first diffusion region of opposite conductivity type that serves as a source region or a drain extraction region in the epitaxial layer, and polycrystalline silicon on the surface of the epitaxial layer. A diffusion region of one conductivity type is formed so as to surround only the diffusion region side of the first opposite conductivity type serving as a source region, and the diffusion region of one conductivity type. Is formed so as to include at least a part of the lower region of the gate electrode. 2. The epitaxial layer located in the lower region of the gate electrode is of a second reverse conductivity type so as to at least partially overlap the diffusion region of the first reverse conductivity type which is a drain extraction region. The diffusion area is formed,
2. The MOS semiconductor device according to claim 1, wherein the diffusion region of the second opposite conductivity type has a lower concentration than the diffusion region of the first opposite conductivity type. 3. A voltage different from that of the substrate is applied to the diffusion region of one conductivity type via the buried layer of the opposite conductivity type between the diffusion region of one conductivity type and the substrate. The MOS semiconductor device according to claim 1 or 2, which is characterized in that.