JP2003344488A - Memory pause test method for semiconductor integrated circuit and test circuit thereof - Google Patents

Abstract

(57) [Summary] In a memory pause test method and a test circuit for a semiconductor integrated circuit, a test sequence for a plurality of memories can be completed simultaneously by increasing the number of small-scale circuits, and the pause time can be accurately measured. The purpose is to be able to. SOLUTION: A BIST circuit 2 for testing memories A and B, a memory having the largest address direction size, and other memories other than those required for a semiconductor integrated circuit having a plurality of memories having different address direction sizes are mounted. A hold signal for preliminarily calculating a time difference (difference time) required for one test sequence and causing the other memory test sequence to wait for each difference time from the start of the memory test sequence having the largest address size. A generation circuit 12 is provided. According to this configuration, one of the plurality of memories
Two test sequences can be completed at the same time, and the pause time measurement of each memory can be accurately realized with a small-scale circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory pause test method for a semiconductor integrated circuit in which a plurality of memories having different address directions are mounted, and a test circuit therefor.

[0002]

2. Description of the Related Art In recent years, the circuit scale has been increased due to the miniaturization of LSI manufacturing processes, and accordingly, the inspection cost in shipping test and the analysis cost when a defect occurs have increased. In such shipping test of LSI, the inspection cost should be reduced, that is, the test pattern should be compressed, and the inspection should be performed accurately in order to minimize the market defects in the users in the shipping test. It is becoming an important project to analyze semiconductors and take countermeasures in order to promote semiconductor development and differentiate from other companies.

Now, with the miniaturization of semiconductor manufacturing technology,
It has become possible to mount a plurality of memories on one semiconductor integrated circuit (element). When performing a pause test for a wide variety of memories mounted on such a semiconductor integrated circuit, even if a pause test for a single memory is required, an inspection time of several ms is required, and therefore, a wide variety of types of memory are required. It is necessary to realize the memory pause test accurately, simultaneously, and with the smallest test circuit. In addition, when a defect occurs, it is essential to devise a circuit that can perform the defect analysis as quickly and easily as possible.

In order to carry out the pause test and the like efficiently and easily, a BIST (Built-in Self-test) circuit, which can judge the quality of the memory inside the semiconductor integrated circuit, has been widely used. A memory pause test circuit for a semiconductor integrated circuit in which the BIST circuit is provided for each memory is disclosed in, for example, Japanese Patent Laid-Open No. 2001-266594.

The disclosed memory pause test circuit is a memory pause test circuit when a large number of memories having different checker pattern write completion times, which are the pause time measurement timings, are included in the semiconductor integrated circuit. A counter, so that the access to the memory where writing is completed waits until the checker pattern writing to the last memory is completed,
A hold signal generation unit including a comparator and a hold control circuit is inserted in the preceding stage of each BIST circuit.

Further, the inspection result information of each BIST circuit (error information of occurrence of expected value mismatch) is output to the LSI tester for error analysis. When one BIST circuit is provided for each of a plurality of memories (one BIST circuit
(If there are multiple memories controlled by the IST circuit)
In addition, the inspection result information is output to the LSI tester as one output signal regardless of the number of memories.

[0007]

However, in the configuration of the conventional memory pause test circuit described above, since the hold signal generating section including the counter, the comparator and the hold control circuit is required in the preceding stage of each BIST circuit, the circuit scale is reduced. Has become a factor that increases. Moreover, the pause time cannot be accurately measured because the checker pattern writing completion time to the memory differs depending on the memory size.

Further, in the above-described conventional memory pause test circuit configuration, when an expected value mismatch occurs, it is possible to identify the test sequence in which the failure occurs in the error analysis on the LSI tester. A huge number of man-hours was required.

Further, in order to specify the pause time measurement point of each memory controlled by a different BIST circuit, waveform investigation by simulation is indispensable, and extra man-hours are required for this purpose.

Further, when there are a plurality of memories controlled by one BIST circuit, in the conventional memory pause test circuit, error information is serially output as one output signal to one BIST circuit. Therefore, when the expected value mismatch of the memory output occurs, it is enormous to identify the location of the memory where the failure occurs in the error analysis on the tester and to debug (DEBUG) the failure phenomenon. It took a lot of work.

The present invention provides a memory pause test method for such a semiconductor integrated circuit and a test circuit therefor,
It is an object of the present invention to enable one test sequence of a plurality of memories to be completed at the same time by increasing the number of circuits on a small scale, and to realize the pause time measurement of each memory accurately and simultaneously.

[0012]

According to a method of testing a memory pause of a semiconductor integrated circuit of the present invention, a plurality of memories having the same size in the address direction are mounted on a semiconductor integrated circuit in which a plurality of memories having different sizes in the address direction are mounted. A memory pause test method for a semiconductor integrated circuit including a BIST circuit for testing each memory, wherein the memory having the largest address direction size among the memories mounted on the semiconductor integrated circuit. The difference between the time required for one test sequence required and the time required for one test sequence required for other memory is
It is determined in advance in each of the other memories, and the test sequence of each of the other memories is executed while waiting for each of the difference times obtained from the start of the test sequence of the memory having the maximum size in the address direction. It is a thing.

According to the present invention, it is possible to simultaneously complete one test sequence of a plurality of memories by increasing the number of circuits on a small scale, and to realize the pause time measurement of each memory accurately and simultaneously. A method for memory pause testing of a circuit is obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a semiconductor integrated circuit in which a plurality of memories having different address direction sizes are mounted, and each of the memories or each of the plurality of memories having the same address direction size. A method of testing a memory pause of a semiconductor integrated circuit having a BIST circuit for testing each memory, which is required for a memory having a maximum address direction size among the memories mounted on the semiconductor integrated circuit. The difference time between the time required for one test sequence and the time required for one test sequence required for the other memory is obtained in advance in each of the other memories, and the test sequence of each of the other memories is determined in the address direction size. The difference time obtained from the start of the memory test sequence that maximizes The test sequences of other memories are executed at the same time by waiting for the difference time from the start of the test sequence of the memory with the maximum size in the address direction for each test sequence. And the pause time of each memory can be measured accurately and simultaneously with a small number of circuits.

The invention according to claim 2 is the invention according to claim 1, in which each time one test sequence is completed, the completion of the test sequence is output. When the expected value disagreement occurs, it is possible to easily understand in which test sequence the defect has occurred, and it is also possible to use different BIST.
It has an effect that it becomes possible to specify a position where the pause time of each memory controlled by the circuit can be measured at the same time.

Further, the invention according to claim 3 is the same as that of claim 1.
Alternatively, in the invention according to claim 2, in a BIST circuit that tests a plurality of memories having the same size in the address direction, when the expected value mismatch of the memory outputs is detected, it is determined which memory is in trouble. By recognizing and testing only the memory unit in which the defect has occurred, it is possible to easily identify the location in which memory the defect occurs, and debug only in the defective memory. By enabling (DEBUG), the tester analysis man-hours can be significantly reduced.

According to a fourth aspect of the present invention, in a semiconductor integrated circuit in which a plurality of memories having different address direction sizes are mounted, each memory is provided, or each memory has a same address direction size. BIST circuit for testing, time required for one test sequence required for the memory having the largest address direction size among the memories mounted on the semiconductor integrated circuit, and one test sequence required for other memories The difference time from the time taken for each of the other memories is calculated in advance, and the execution of the test sequence of each of the other memories is calculated from the start of the test sequence of the memory having the maximum size in the address direction. Of the hold signal for holding the difference time of
A hold signal generating circuit for outputting to the ST circuit is provided, and the execution of the test sequence of each of the other memories is calculated from the start of the test sequence of the memory having the maximum size in the address direction. The waiting time allows the test sequences of a plurality of memories to be completed at the same time, and the pause time can be accurately measured with a small number of circuits.

Further, the invention according to claim 5 is the invention according to claim 4.
The hold signal generating circuit according to claim 1,
The circuit that outputs the completion signal of one test sequence is added, and when the expected value mismatch of the memory output occurs, it is easy to determine in which test sequence the failure has occurred due to the above test sequence completion signal. Therefore, it is possible to identify the location where the pause time of each memory controlled by different BIST circuits can be simultaneously measured.

Further, the invention according to claim 6 is the invention according to claim 4.
Alternatively, in the invention according to claim 5, in the BIST circuit for testing a plurality of memories having the same size in the address direction, which memory is defective when an expected value mismatch of memory outputs occurs. It is possible to easily identify the location of the memory in which a failure has occurred by recognizing the above and providing a circuit that allows testing to be performed on the memory in which the failure occurs. In addition, since it is possible to debug (DEBUG) only in the defective memory, it is possible to significantly reduce the tester analysis man-hours.

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a configuration diagram of a memory pause test circuit of a semiconductor integrated circuit according to Embodiment 1 of the present invention. One memory in a semiconductor integrated circuit device equipped with a plurality of memories having different address direction sizes. The structure of a pause test circuit is shown.

In FIG. 1, reference numeral 1 denotes a BIST circuit portion mounted on a semiconductor integrated circuit device. The BIST circuit portion 1 has a memory capacity (size in the address direction) of an inspected memory A and an inspected memory B (which are the same). The BIST circuit 2 is provided for executing inspection (memory pause test) of an example of a plurality of memories. That is, as the BIST circuit 2, the address generator 4 that operates as a kind of counter that sequentially indicates the addresses of the memory under test A and the memory under test B, and the test pattern of the memory under test A and the memory under test B are automatically generated. Of the memory under test A and the memory under test B and the expected value (data of the test pattern) are compared to determine whether they match, and the memory under test A and the memory under test are compared. When the expected signal is not obtained from B (when the expected values do not match), the expected value comparator 6 that determines that a failure (failure) occurs in the memory A or the memory B to be inspected, and the address generators 4,
A pattern generator 5 and a control signal generator 7 which is a state machine for controlling the expected value comparator 6 are provided.

Further, the BIST circuit section 1 receives the normal system input signal xa for the memory under test A and the signal from the BIST circuit 2 as a BIST test mode input signal (test signal).
a selector 8 for selecting by the a, and a selector 9 for selecting the normal system input signal xb for the memory under test B and the signal from the BIST circuit 2 by the test signal a.
Is equipped with.

The BIST circuit 2 starts its operation when a test sequence start signal (reset input signal; hereinafter referred to as a reset signal) b, a BIST clock signal c, and a hold control signal d are input, and the operation is started. The data output from the inspection memory A and the memory under test B (data output signal e) is judged by the expected value comparator 7 to be in agreement with the expected value, and the result is output as the expected value comparison result output signal f to the LSI tester. Is output to.

This BIS is used for semiconductor integrated circuit devices.
A hold signal control unit 11 is mounted in the preceding stage of the T circuit unit 1. The hold signal control unit 11 includes a hold signal generation circuit 12 that outputs a hold control signal d for controlling whether the BIST circuit 2 is in the active state or the hold state. The hold signal generation circuit 12 is activated by the reset signal b for starting the test sequence, and outputs the hold control signal d to the hold state for a predetermined time t to the control signal generation unit 7.

A plurality of BIST circuit units are mounted on the semiconductor integrated circuit device in accordance with the number of mounted memories, and the BIST circuit unit 1 executes the inspection of the plurality of memories. However, there is also a BIST circuit unit that executes the inspection of only a single memory.

As the predetermined time t, the time required for one test sequence depends on the size in the address direction so that one test sequence completion time of each memory mounted on the semiconductor integrated circuit device can be made simultaneous. Utilizing the fact that it is uniquely determined, the maximum test sequence time (the time required for one test sequence required for the memory having the maximum address direction size mounted on the semiconductor integrated circuit element) and the test memory A And the difference time between one test sequence time required for the memory B to be inspected and the difference time are set.

The hold control signal d from the outside of the BIST circuit 2 (the output signal of the hold signal generation circuit 12) causes the difference time from immediately after the test sequence of the memory having the maximum size in the address direction (maximum capacity) is started. If the execution of the test sequence (writing / reading of data) is held for each memory by t (waiting), one test sequence completion time can be made at the same time.

An example of the test sequence of the memory pause test circuit of the semiconductor integrated circuit is shown in FIG. In FIG. 2, reference numeral 21 is a pause time measurement sequence diagram (a test sequence diagram in the case of the memory having the maximum capacity) in the memory having the maximum memory capacity mounted on the semiconductor integrated circuit device
Reference numeral 22 is a characteristic diagram of the hold control signal d of the hold signal generating circuit 12 input to the BIST circuit 2 in order to control whether the BIST circuit 2 of the memory having the maximum capacity is in the active state or the hold state. is there. Again 2
3 is a pause time measurement sequence diagram in the memory A (or memory B to be inspected) whose memory capacity is not the maximum (test sequence diagram in the case of an arbitrary memory whose capacity is less than the maximum), and 24 is this memory A to be tested. FIG. 6 is a characteristic diagram of a hold control signal d of a hold signal generation circuit 12 that is input to the BIST circuit 2 in order to control whether the BIST circuit 2 is in an active state or a hold state. In the figure, "H" of the hold control signal d indicates an active state, and "L" indicates a hold state. The hold control signal d to the BIST circuit 2 of the memory having the maximum capacity is
Is always in the active state "H".

In FIG. 2, reference numeral 25 is the time required for one test sequence of the memory having the maximum capacity, and 26 is "0101" on the memory having the maximum capacity and the memory A to be inspected.
The checkerboard pattern (table pattern) [1] write sequence in which the checkerboard pattern is written in the order of "...", 27 is the read sequence for the written checkerboard pattern [1], 28 is the maximum capacity memory and the memory under test A Checkerboard pattern (back pattern) in which checkerboard patterns are written in the order of "1010 ..."
[2] shows a write sequence, and 29 shows a read sequence of the written checkerboard pattern [2]. Reference numeral 30 indicates a hold time during which the memory A to be inspected is in the hold state.

When the normal memory pause time is measured, the writing of the checkerboard pattern [1] is completed in all the memories mounted in the semiconductor integrated circuit, that is, the timing of the pause time measurement point (1). The first pause time measurement is performed when the memory for the guaranteed pause time is not accessed and no mismatch occurs in the expected value comparison by reading the checkerboard pattern [1]. Similarly, when the writing of the checkerboard pattern [2] is completed, that is, at the timing of the pause time measurement point (2), the memory for the pause time guaranteed time is not accessed, and the expectation is obtained by reading the checkerboard pattern [2]. When no discrepancy occurs in the value comparison, the second pause time measurement is performed.

In the pause time measuring sequence 21, since the memory has the maximum capacity, the size in the address direction becomes maximum, and the time 25 required for one test sequence becomes maximum. Based on the time 25 required for this maximum test sequence, the maximum test sequence time 25 and other memories (memory A to be inspected, etc.) are stored in advance.
The difference time t from the test sequence time required for

This difference time t is set in each hold signal generating circuit 12 of each BIST circuit 2, and as shown in FIG. 2, in the memory under test A, the test sequence of the memory having the maximum address direction size is started. Immediately after the execution, the test sequence (the checkerboard pattern [1], [2] write sequence and read sequence) is executed after the hold time 30. Therefore, the processing completion time in one test sequence is aligned with the memory having the maximum capacity. There is.

As described above, even when a plurality of memories having different sizes in the address direction are mounted on the semiconductor integrated circuit device, each of the plurality of memories is made to wait for the difference time from the start of the test sequence of the memory having the maximum size in the address direction. It is possible to complete the test sequence of the memory at the same time, and it is possible to accurately and simultaneously measure the pause time at the timing of the pause time measurement points (1) and (2) shown in FIG. In addition, it is possible to measure pause time accurately with a small number of circuits, and it is also possible to reduce redundant test circuits. (Embodiment 2) FIG. 3 shows a configuration diagram of a memory pause test circuit in the case where a plurality of BIST circuit portions are mounted on a semiconductor integrated circuit according to Embodiment 2 of the present invention. The same components as those of the memory pause test circuit (FIG. 1) according to the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 3, reference numeral 1A denotes a BIST circuit portion for executing an inspection of an inspected memory A and an inspected memory B (an example of a plurality of memories) having the same size in the address direction, and 1B denotes a subject having the same size in the address direction. BIS for executing inspection of inspection memory C and inspected memory D (an example of a plurality of memories)
A T circuit part is shown.

When a plurality of BIST circuit units 1A and 1B are mounted on the semiconductor integrated circuit device, one test sequence can be completed at the same time as in the case of the first embodiment, so that one test sequence can be completed at the same time. Since the time required for the test sequence is uniquely determined by the size in the address direction, the test sequence time of the memory having the maximum capacity and the inspected memories A and B and the inspected memories of the BIST circuit units 1A and 1B are preliminarily used. The difference times ta and tb from the test sequence time required for the memories C and D are calculated, and the hold signal generation circuit 34 of the hold signal control unit 33 starts the test sequence of the memory having the maximum size in the address direction from immediately after each. Hold control signal d for holding the execution of the test sequence of the memory for the difference times ta and tb , It is generating the db.

The hold control signal output from the hold signal generation circuit 34 is only "H" in the case of the memory having the maximum size in the address direction, and "H" in the other memory during the period in which the BIST circuit 2 is held. L ",
Utilizing the fact that the active period is "H", the two-input AND circuit 35 and the flip-flop (serial two-stage configuration)
36. Hold a circuit that is composed of a two-input AND circuit 37 having one negative input and outputs a test sequence completion signal g of "H" with a width of two clocks at the same time when one test sequence is completed. It is connected to the signal generation circuit 34.

By outputting this test sequence completion signal g to the outside, when the expected value mismatch of the memory outputs occurs, it is possible to easily understand in which test sequence the failure occurs on the LSI tester. It will be possible.

By outputting the test sequence completion signal g, the pause time measurement point is set to L.
It is possible to inform the SI tester. in this way,
By adding the circuit for outputting the test sequence completion signal g to the hold signal generation circuit 34, when the expected value mismatch of the memory outputs occurs, the test sequence completion signal g causes a failure in any test sequence on the LSI tester. It is possible to easily grasp whether or not it is occurring, and it is also possible to specify a location where the pause time of each memory controlled by different BIST circuits can be measured at the same time. (Third Embodiment) FIG. 4 is a block diagram of a memory pause test circuit in the case where a plurality of BIST circuits are mounted on the semiconductor integrated circuit according to the third embodiment of the present invention.
The memory pause test circuit of the first embodiment (FIG. 1)
The same configurations as those of the above are given the same reference numerals and the description thereof will be omitted. The wiring of the normal system input signals xa and xb is omitted.

A hold signal control unit 42 is provided in the preceding stage of the BIST circuit unit 41 that executes the inspection of the memory under test E and the memory under test F (an example of a plurality of memories) having the same size in the address direction.

In the expected value comparator 6 in the BIST circuit section 41, the expected value comparison itself is carried out for each of the inspected memories E and F even if there are a plurality of inspected memories E and F. Therefore, when the expected value mismatch occurs, it is possible to specify in which of the memories E and F to be inspected the expected value mismatch occurs. When the expected value mismatch occurs, in the case of the memory under test E, the error flag signal h is set to the output signal of the flip-flop 43 (memory E error flag signal),
In the case of the memory F to be inspected, the error flag signal j is output as the output signal of the flip-flop 44 (memory F error flag signal) after being retimed by the flip-flop for each of the memories E and F to be inspected. There is. As a result, even if a plurality of memories to be inspected E and F are mounted, it is possible to specify in which memory the defect has occurred on the LSI tester.

When the output pins cannot be output to the outside due to the limitation of the package pins, the flip-flops 43, 44 are completed after each test sequence is completed.
Latch with and output the signal serially,
This function can be realized simply by increasing the number of pins.

Further, the error flag signals h and j of the memories to be inspected E and F are inputted to the control signal generating circuit 45 newly added to the hold signal control section 42. The control signal generation circuit 45 activates only the inspected memories E or F to which the error flag signal h or j is input (only the memory in which a defect has occurred), and the other inspected memories F or E. The control signal generating circuit 4 is a circuit for forming a disable signal k for deactivating (normal memory).
5 indicates the generated disable signal k by the BIST circuit unit 41.
It is output to the control signal generation unit 7 inside.

When the control signal generating section 7 receives the disable signal k, the control signal generating section 7 causes the address generating section 4, the pattern generating section 5 and the expected value comparator 6 to output only the signal to the inspected memory E or F in which the defect has occurred. Is controlled so as to be in an active state, and at the same time, a control signal for directly controlling each of the inspected memories E and F, that is, a control signal m is output to the inspected memory E and a control signal n is output to the inspected memory F. Then, only the inspected memory E or F in which the defect has occurred is activated, and the others are set to the disabled state. As a result, only the inspected memory E or F in which the defect has occurred is continuously inspected.

In this way, BIST for executing the inspection of the inspected memory E and the inspected memory F (plural memories) by one unit
The circuit section 41 recognizes in which inspected memory E or F the defect occurs when the expected value mismatch of the memory outputs occurs, and recognizes the inspected memory E or F in which the defect occurs. By providing the circuit that enables the test, that is, the expected value comparator 6, the flip-flops 43 and 44, the control signal generation circuit 45, and the control signal generation unit 7, a defect occurs in which memory E or F to be inspected. It is possible to easily identify on the LSI tester whether or not the test is being performed, and by enabling the BIST only on the inspected memory E or F in which a defect has occurred, debugging on the LSI tester ( DEBUG) becomes easier and the tester analysis man-hours can be significantly reduced.

[0045]

As described above, according to the present invention, the execution of the test sequence of each of the other memories is delayed by the respective difference times from the start of the test sequence of the memory having the maximum size in the address direction. It is possible to complete the test sequence of the memory at the same time, and it is possible to obtain an advantageous effect that the pause time can be accurately measured with a small number of circuits.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a memory pause test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a test sequence diagram in the memory pause test method for the semiconductor integrated circuit.

FIG. 3 is a circuit configuration diagram of a memory pause test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a memory pause test circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

[Explanation of symbols]

1 BIST circuit section 2 BIST circuit 4 Address generator 5 pattern generator 6 Expected value comparator 7 Control signal generator 8, 9 selector 11, 33, 42 Hold signal controller 12, 34 Hold signal generation circuit 35,37 AND gate 36,43,44 flip-flops 45 Control signal generation circuit xa Normal system input signal of arbitrary memory under test A xb Normal system input signal of arbitrary memory under test B a BIST test mode input signal b Reset input signal c BIST clock input signal d, da, db hold control signal Data output signal from memory f Expected value comparison result output signal g Test sequence completion signal h Error flag output signal of memory under test E j Error flag output signal of inspected memory F k Control control signal m Control signal for memory under test E n Control signal for memory under test F

Claims (6)

[Claims] 1. A semiconductor integrated circuit in which a plurality of memories having different address direction sizes are mounted, and a BIST circuit for testing each memory is provided for each of the memories or each of the plurality of memories having the same address direction size. A method for testing a memory pause of a semiconductor integrated circuit, comprising: a time required for one test sequence required for a memory having a maximum address direction size among the memories mounted on the semiconductor integrated circuit; The difference time from the time required for one test sequence is obtained in advance in each of the other memories, and the test sequence of each of the other memories is obtained from the start of the test sequence of the memory having the maximum size in the address direction. A memory pause of a semiconductor integrated circuit characterized in that each differential time is waited for and executed. Strike method. 2. The memory pause test method for a semiconductor integrated circuit according to claim 1, wherein the test sequence completion is output each time one test sequence is completed. 3. A BIST circuit for testing a plurality of memories having the same size in the address direction, when an expected value mismatch of memory outputs is detected, it is recognized which memory is in trouble and the trouble occurs. 3. A memory pause test method for a semiconductor integrated circuit according to claim 1 or 2, wherein only the memory unit that is being tested is tested. 4. A BIS for testing each memory in a semiconductor integrated circuit in which a plurality of memories having different address direction sizes are mounted, or for each memory or each of a plurality of memories having the same address direction size.
T circuit, one test sequence required for the memory having the largest address direction size among the memories mounted on the semiconductor integrated circuit, and one test sequence required for the other memories Difference time of each of the other memories is calculated in advance, and execution of the test sequence of each of the other memories is waited for each calculated difference time from the start of the test sequence of the memory having the maximum size in the address direction. A memory pause test circuit for a semiconductor integrated circuit, further comprising a hold signal generating circuit for outputting a hold signal for causing the BIST circuit of each of the other memories. 5. The memory pause test circuit for a semiconductor integrated circuit according to claim 4, wherein a circuit for outputting a completion signal of one test sequence is added to the hold signal generation circuit. 6. A BIST circuit for testing a plurality of memories having the same size in the address direction recognizes which memory is in failure when an expected value mismatch of memory outputs occurs and causes a failure. 6. A memory pause test circuit for a semiconductor integrated circuit according to claim 4 or 5, further comprising a circuit that enables a test to be performed on a single memory.