JP2003233495A - Microprocessor - Google Patents

Abstract

(57) Abstract: Provided is a microprocessor capable of decoding a 32-bit length instruction in one clock in a 16-bit instruction set architecture having a 32-bit length instruction. A queue selector that selects and outputs a 16-bit instruction code to be decoded according to a first selection signal, and a first decoder that decodes the selected instruction code. When the content of the selected 16-bit instruction code corresponds to a 32-bit instruction, a second selection signal is output, and the selected 16-bit instruction code is linked to a continuous instruction code on a program to form a 32-bit instruction. Provide a function to generate code. A second decoder for decoding a 32-bit instruction code is provided, and when the second selection signal is enabled, a decoding result of the second decoder is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor such as a 16-bit instruction set architecture, and more particularly to a microprocessor having a mechanism for improving throughput in an instruction set having a 32-bit length instruction.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 11, in a microprocessor having eight 16-bit instruction queues Q1 to Q8 in a 16-bit instruction set architecture, an instruction queue selector 13 assigns to each instruction queue Q1 to Q8. In addition to inputting the stored instruction code, the decode queue select signal control circuit 114 inputs the decode queue select signal S1 for selecting the instruction queue in which the instruction code to be decoded is stored.

Then, the instruction queue selector 13 outputs the selected 16-bit instruction code to the 16-bit instruction decoder 18, and the instruction decoder 18 which received it decodes it and executes the instruction.

In such a conventional system, as shown in FIG. 12, five stages of instruction fetch (F), decode (D), execution (E), memory access (M), and register write back (W) are performed. In a microprocessor having a pipeline stage, decoding a 32-bit length instruction divides the instruction into 16-bit first half and second half
The clock decodes the first 16-bit code,
The instruction was completed in two clocks in total by the method of decoding the latter half 16-bit code in the second clock. A 16-bit length instruction can be decoded in 1 clock.

[0005]

As described above, in the conventional microprocessor, although the 32-bit length instruction is one instruction, the decoding is performed in two clocks as if there were two instructions. , Was a factor that lowered the throughput.

The present invention has been made to solve the above-mentioned conventional problems, and its object is to decode a 32-bit length instruction in one clock in a 16-bit instruction set architecture having a 32-bit length instruction. Is to provide a microprocessor that can.

[0007]

To achieve the above object, in a microprocessor according to a first aspect of the present invention, N (N ≧ 4) instruction queues for storing instruction codes of predetermined bits and decoding are performed. N received from each of the instruction queues according to a first selection signal designating an instruction code to be performed.
In a microprocessor including a selection circuit that selects and outputs an instruction code to be decoded from the individual instruction codes, and a first decoder that decodes the instruction code of the predetermined bit selected by the selection circuit, When the content of the instruction code of the predetermined bit selected according to the first selection signal corresponds to a part of an instruction having a bit length larger than the predetermined bit, the second selection signal is output and the selection is performed. A first control circuit for generating and outputting an instruction code corresponding to the instruction by taking out and concatenating an instruction code continuous with the generated instruction code from the N instruction codes, and the first control circuit. A second decoder that decodes the instruction code output from the second decoder, and the second selection signal is the decoding result of the second decoder or the first decoder. Characterized by comprising a decoding result selecting circuit for selecting and outputting the result of decoding of da.

In the microprocessor according to the second aspect of the present invention, N pieces (N ≧) for storing 16-bit instruction codes are stored.
4) an instruction queue, and a selection circuit for selecting and outputting an instruction code to be decoded from N instruction codes received from each of the instruction queues in accordance with a first selection signal designating an instruction code to be decoded. A first decoder for decoding the 16-bit instruction code selected by the selection circuit, the content of the 16-bit instruction code selected according to the first selection signal corresponds to a 32-bit length instruction In the case of performing, a second selection signal is output, and an instruction code that is consecutive in program with the selected 16-bit instruction code is taken out from the N instruction codes and connected to generate a 32-bit instruction code. A first control circuit for outputting, and a second decoding circuit for decoding the 32-bit instruction code output from the first control circuit. And da, the second selection signal, characterized in that a decoding result selecting circuit for selecting and outputting the decoded result of the decoding result of the second decoder and the first decoder.

In the microprocessor according to the third aspect of the invention, there are N (N) units for storing instruction codes of predetermined bits.
A selection circuit for selecting and outputting an instruction code to be decoded from N instruction codes received from each of the instruction queues in accordance with an instruction queue of ≧ 4) and a first selection signal designating an instruction code to be decoded. And a first decoder for decoding the instruction code of the predetermined bit selected by the selection circuit, wherein the content of the instruction code of the predetermined bit selected according to the first selection signal is When it corresponds to a part of an instruction having a bit length larger than a predetermined bit, a second selection signal is output, and an instruction code consecutive in program with the selected instruction code among the N instruction codes is output. A first control circuit for extracting and outputting an instruction code corresponding to the instruction by connecting in accordance with an external signal indicating endian; A second decoder that decodes the instruction code output from the first control circuit, and the second selection signal selects the decoding result of the second decoder or the decoding result of the first decoder. And a decoding result selection circuit for outputting.

In the microprocessor according to the fourth aspect of the invention, N pieces (N ≧) for storing a 16-bit instruction code are stored.
4) an instruction queue, and a selection circuit for selecting and outputting an instruction code to be decoded from N instruction codes received from each of the instruction queues in accordance with a first selection signal designating an instruction code to be decoded. A first decoder for decoding the 16-bit instruction code selected by the selection circuit, the content of the 16-bit instruction code selected according to the first selection signal corresponds to a 32-bit length instruction In the case of performing, the second selection signal is output, and the instruction code that is continuous in program with the selected 16-bit instruction code is taken out from the N instruction codes and connected according to the external signal indicating the endian. First control circuit for generating and outputting a 32-bit instruction code, and the 32 bit command output from the first control circuit. A second decoder that decodes an instruction code and a decode result selection circuit that selects and outputs the decode result of the second decoder or the decode result of the first decoder by the second selection signal. It is characterized by that.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the arrangement of a microprocessor according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a microcomputer chip equipped with the microprocessor shown in FIG.

In FIG. 1, the microprocessor includes eight 16-bit instruction codes for storing 16-bit instruction codes.
Bit instruction queue Q1, Q2, Q3, Q4, Q5, Q
6, Q7, Q8, each output side of which is connected to the instruction queue selector 13A via eight 16-bit buses 12.

The instruction queue selector 13A has a select signal control circuit 114 for designating an instruction code to be decoded.
A decode queue select signal S1 output from A,
In addition to the function of inputting the 16-bit instruction code from the instruction queues Q1 to Q8 and outputting the instruction code which is the contents of the 16-bit bus 12 selected by the signal S1,
It has the following functions (first control circuit). That is, when it is determined that the selected instruction code corresponds to a 32-bit length instruction, the enable decode result select signal S2 is output, and the selected 16
16-bit bus 12 that outputs a bit instruction code
Has a function of generating and outputting a 32-bit instruction code in which the output content of the above is connected to the output content of the 16-bit bus 12 in which a 16-bit instruction code continuous to this instruction code is output.

The instruction queue designated by the select signal control circuit 114A (second control circuit) is the instruction queue Q.
1 → Q2 → Q3 → Q4 → Q5 → Q6 → Q7 → Q8 → Q1
The transition is made in the order of.

On the output side of the instruction queue selector 13A,
Decode the generated and output 32-bit instruction code 3
A 2-bit length instruction decoder 17 and a 16-bit instruction decoder 18 for decoding the selected 16-bit instruction code are connected via a 32-bit bus 15 and a 16-bit bus 16, respectively.

Further, the decoding result output buses 19 and 11 are provided on the output sides of the two decoders 17 and 18, respectively.
The decode result selector 112 is connected via 0. The decode result selector 112 is a circuit that selects the decode results of the two decoders 17 and 18 according to the decode result select signal S2.

In FIG. 2, a microcomputer chip 100 includes a microprocessor 10 of the present embodiment shown in FIG.
1 is mounted, the microprocessor 101 is connected to the memory 103 and the bus bridge circuit 104 via the system bus 102, and the output side of the bus bridge circuit 104 is connected to the I / O unit 105.

The 32-bit length instruction is arranged on a word boundary on the memory 103. For example, as shown in FIG. 3A, the first half portion and the second half portion of the 32-bit long instruction a are arranged in a 32-bit one word area without crossing word boundaries.

Next, the operation of this embodiment will be described.

The microprocessor 101 is the same as that shown in FIG.
The 32-bit long instruction a of the memory arrangement shown in (a) is fetched, and the first half and the second half of the 32-bit long instruction a are respectively placed in the instruction queues Q1 and Q2 without crossing word boundaries as shown in FIG. 4 (a). Store.

The instruction queue selector 13A shown in FIG.
A decode queue that receives a 16-bit instruction code from each of the instruction queues Q1 to Q8 via the 16-bit bus 12 corresponding to each queue, and specifies the instruction queue Q1 in which the instruction to be decoded is stored from the select signal control circuit 114A. Receive select signal S1.

According to the value of the decode queue select signal S1, the instruction queue selector 13A transfers the 16-bit instruction code stored in the instruction queue Q1 to the 16-bit bus 16
To the 16-bit instruction decoder 18 via the 32-bit bus, and a 32-bit instruction code obtained by combining the instruction code of the instruction queue Q1 and the instruction code of the instruction queue Q2 to be decoded next is 32-bit long via the 32-bit bus 15. Output to the instruction decoder 17.

At the same time, the instruction queue selector 13A has an instruction queue Q designated by the decode queue select signal S1.
When the instruction code of 1 coincides with the code indicating that it is the first half 16-bit code of the 32-bit length instruction a, the decode result select signal S2 is output.

The 32-bit length instruction decoder 17 receives the 32-bit instruction code output from the instruction queue selector 13A and outputs the decoding result to the decoding result output bus 1
Output to 9. The 16-bit instruction decoder 18 receives the 16-bit instruction code output from the instruction queue selector 13A and outputs the decoding result to the decoding result output bus 1
Output to 10.

The decoding result selector 112 uses the above 32
Bit length instruction decoder 17 and 16-bit instruction decoder 1
8 and the decode result select signal S2 output by the instruction queue selector 13A, and when the decode result select signal S2 is enabled, the decode result of the 32-bit length instruction decoder 17 is selected. Then, the result is output to the decoding result output bus 113, the decoding is completed, and the result is passed to the execution stage.

When the decode result select signal S2 is enabled when the decoding is completed, the select signal control circuit 114A changes the designation of the instruction queue to be decoded next from the instruction queue Q1 to the instruction queue Q3, and the decoding is performed. Output to the cue select signal S1.

As described above, the microprocessor 101
Has a 32-bit length instruction decoder 17, generates a decode result select signal S2, and outputs 32 as a result of the signal S2.
By selecting the result of the bit length instruction decoder 17, the 32-bit length instruction a can be decoded in one clock as shown in FIG.

In this embodiment, the 32-bit length instruction a
Can be realized even in the case where the word straddles a word boundary as shown in FIGS. 3B and 4B.

[Second Embodiment] In the above first embodiment,
An example in which a 32-bit length instruction can be accommodated on a word boundary or across words, and the endian is fixed to little endian (however, it can be realized in the first embodiment even if it is fixed to big endian). ) Has been described, the second embodiment will describe an example of a processor in which the endian is not fixed and can be switched regardless of whether the 32-bit length instruction is within the word boundary or straddling it.

FIG. 6 is a block diagram showing the structure of the microprocessor according to the second embodiment of the present invention. Figure 7
FIG. 7 is a block diagram showing a schematic configuration of a microcomputer chip on which the microprocessor shown in FIG. 6 is mounted. In addition,
The same parts as those in FIG. 1 and FIG.

As in the first embodiment, this microprocessor has eight 16-bit instruction queues Q1 to Q8.
And a 32-bit length instruction decoder 17, a 16-bit instruction decoder 18, and a decoding result selector 112. The difference from the first embodiment is that the instruction queue selector 1
The endian-compatible instruction queue selector 21 is provided in place of 3A, and the endian-compatible select signal control circuit 23 is provided in place of the select signal control circuit 114A.

The instruction queue selector 21 has a decode queue select signal S1 output from a select signal control circuit 23 for designating an instruction code to be decoded, and an endian signal supplied from the outside of the microcomputer chip 100 as shown in FIG. ED (indicating little endian / big endian) and 1 from instruction queues Q1 to Q8
In addition to the function of inputting a 6-bit instruction code and outputting the instruction code that is the contents of the 16-bit bus 12 selected by the signal S1, it has the following function (first control circuit). That is, when it is determined that the selected 16-bit instruction code corresponds to a 32-bit length instruction, the enable decode result select signal S2 is output, and further, the 16-bit bus 12 outputting the selected 16-bit instruction code is output. And the output content of the 16-bit bus 12 in which a 16-bit instruction code consecutive to this instruction code is output in accordance with the endian signal ED is generated and output as a 32-bit instruction code. Have

The endian-compatible select signal control circuit 23 (second control circuit) receives the endian signal ED and the decode result select signal S2 and determines the instruction queue to be decoded.

Next, the operation of this embodiment will be described.

When the endian signal ED designates little endian, the instruction queue designated by the endian-compatible select signal control circuit 23 is the instruction queue Q1 → Q.
2 → Q3 → Q4 → Q5 → Q6 → Q7 → Q8 → Q1 ... On the other hand, when the big endian is designated, the instruction queue designated by the endian corresponding select signal control circuit 23 is the instruction queue Q2 → Q1 → Q4 → Q.
3 → Q6 → Q5 → Q8 → Q7 → Q2 ...

In the case of the little endian, the arrangement of the instruction on the memory 103, the storage position in the instruction queue by the instruction fetch, and the operation of the microprocessor are the same as those in the first embodiment, and the description thereof will be omitted.

When the endian signal ED specifies big endian, the 32-bit length instruction b is arranged on the memory 103 so as to cross the word boundary as shown in FIG. 8 (a).

As shown in FIG. 6, the microprocessor has eight 16-bit instruction queues Q1, Q2, Q3, Q.
4, Q5, Q6, Q7 and Q8, and as shown in FIG.
The 32-bit long instruction in the memory arrangement shown in FIG. 9 is fetched, and the first half and the second half of the 32-bit long instruction b are stored in the instruction queues Q5 and Q8 so as to cross the word boundary as shown in FIG.

The endian-compatible instruction queue selector 21 shown in FIG. 6 includes an endian signal ED and a 16-bit bus 12 corresponding to each queue from each instruction queue.
The 16-bit instruction code is received via the end code and the decode queue select signal S1 designating the instruction queue Q5 in which the instruction to be decoded is stored is received from the endian corresponding select signal control circuit 23. Depending on the value of the decode queue select signal S1, the endian-compatible instruction queue selector 21 stores the 16 bytes stored in the instruction queue Q5.
16 bit bit instruction code via 16 bit bus 16
Output to the bit instruction decoder 18. At the same time, as shown in FIG. 10, the instruction code of the instruction queue Q5 and the instruction code of the instruction queue Q8 to be decoded next are combined 32.
The bit instruction codes are rearranged so as to correspond to the 32-bit length instruction decoder 17, and output to the 32-bit length instruction decoder 17 via the 32-bit bus 15. At the same time, when the instruction code of the instruction queue Q5 designated by the decode queue select signal S1 matches the code indicating that the first half 16-bit code of the 32-bit length instruction, the endian-compatible instruction queue selector 21 decodes the decode result select signal. Outputs S2.

The 32-bit length instruction decoder 17 outputs 3 bits output from the endian-compatible instruction queue selector 21.
It receives a 2-bit instruction code and outputs the decoding result to the decoding result output bus 19.

The 16-bit instruction decoder 18 outputs the 16-bit instruction output from the endian-compatible instruction queue selector 21.
It receives the bit instruction code and outputs the decoding result to the decoding result output bus 110.

The decoding result selector 112 uses the above 32
Bit length instruction decoder 17 and 16-bit instruction decoder 1
8 and the decode result select signal S2 output from the endian-compatible instruction queue selector 21. When the decode result select signal S2 is enabled, the decode result of the 32-bit length instruction decoder 17 is received. Is selected and output to the decoding result output bus 113 to end the decoding, and is passed to the execution stage.

The endian-corresponding select signal control circuit 23 receives the endian signal ED designating big endian, and when the decoding is completed and the decode result select signal S2 is enabled, the instruction queue of the instruction queue to be decoded next. The designation is changed from the instruction queue Q5 to the instruction queue Q7 and output to the decode queue select signal S1.

As described above, in the second embodiment, the microprocessor having the 32-bit length instruction decoder 17 generates the decoding result select signal S2 and selects the result of the 32-bit length instruction decoder 17 by the signal S2. Further, an endian-compatible instruction queue selector 21 having a function of rearranging and outputting 32-bit length instructions corresponding to endian, and an endian-compatible select signal control circuit 23 for deciding an instruction queue to be decoded corresponding to endian Since it has, the 32-bit length instruction can be decoded in one clock in both little endian and big endian.

In each of the above embodiments, eight instruction queues are described as an example, but the number of instruction queues may be four or more, and the present invention can be applied to a microprocessor having four or more instruction queues. .

In this embodiment, the 32-bit length instruction b
Can be realized even when the word boundaries do not cross as shown in FIGS. 8 (b) and 9 (b).

[0048]

As described above in detail, according to the present invention, for example, a microprocessor of a 16-bit instruction set architecture, which conventionally decodes a 32-bit length instruction with two clocks, is used for a 32-bit length instruction. Since the second decoder and the mechanism for selecting the result of the second decoder by the second selection signal are provided, for example, a 32-bit length instruction can be decoded in one clock,
Increases processor throughput.

Further, a mechanism for inputting an external signal indicating an endian and controlling a first selection signal for selecting an instruction queue according to the endian, and a 32-bit instruction code to be passed to the second decoder according to the endian, for example, By adding the shaping mechanism, it is possible to decode, for example, a 32-bit length instruction in one clock in both little endian and big endian.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor according to a first embodiment of the present invention.

2 is a block diagram showing a schematic configuration of a microcomputer chip in which the microprocessor shown in FIG. 1 is mounted.

FIG. 3 is a diagram showing an example of a memory layout of a little endian 32-bit instruction.

FIG. 4 is a diagram showing an instruction queue storage position when a 32-bit length instruction according to the first embodiment is arranged in a memory as in FIG.

FIG. 5 is a pipeline stage diagram showing an execution cycle of a 32-bit length instruction according to the present invention.

FIG. 6 is a block diagram showing a configuration of a microprocessor according to a second embodiment of the present invention.

7 is a block diagram showing a schematic configuration of a microcomputer chip on which the microprocessor shown in FIG. 6 is mounted.

FIG. 8 is a diagram showing an example of a memory arrangement of a 32-bit length instruction in big endian.

FIG. 9 is a diagram showing an instruction queue storage position when a 32-bit length instruction according to the second embodiment is arranged in the memory as in FIG.

FIG. 10 is a conceptual diagram showing an instruction code rearrangement process of an endian compatible instruction queue selector 21 according to the second embodiment.

FIG. 11 is a block diagram showing a configuration of a conventional microprocessor.

12 is a pipeline stage diagram showing an execution cycle of a 32-bit length instruction in the microprocessor shown in FIG.

[Explanation of symbols]

Q1 to Q8 16-bit instruction queue 12 16-bit bus 13A Instruction queue selector 15 32-bit bus 16 16-bit bus 17 32-bit instruction decoder 18 16-bit instruction decoder 19,110,113 Decode result output bus 21 Endian-compatible instruction queue selector 23 Endian-compatible select signal control circuit 112 Decode result selector 114A select signal control circuit S1 Decode cue select signal S2 Decode result select signal ED endian signal

Claims (5)

[Claims] 1. N (N ≧ 4) instruction queues for storing instruction codes of predetermined bits, and N instruction queues received from each instruction queue according to a first selection signal designating an instruction code to be decoded. A selection circuit for selecting and outputting an instruction code to be decoded from among the instruction codes, and a first decoder for decoding the instruction code of the predetermined bit selected by the selection circuit, When the content of the instruction code of the predetermined bit selected according to the first selection signal corresponds to a part of the instruction having a bit length larger than the predetermined bit, the second selection signal is output and the selection is performed. The instruction code continuous with the instruction code in the program is extracted from the N instruction codes and connected to generate an instruction code corresponding to the instruction. A first control circuit, a second decoder for decoding the instruction code output from the first control circuit, the second selection signal, the decoding result of the second decoder or the first A decode result selection circuit for selecting and outputting a decode result of a decoder. 2. N (N ≧ 4) instruction queues for storing 16-bit instruction codes and N number of instruction queues received from each instruction queue according to a first selection signal designating an instruction code to be decoded. A microprocessor comprising: a selection circuit that selects and outputs an instruction code to be decoded from the instruction codes; and a first decoder that decodes the 16-bit instruction code selected by the selection circuit. When the content of the 16-bit instruction code selected according to the selection signal corresponds to a 32-bit length instruction, a second selection signal is output, and the instruction code consecutive to the selected 16-bit instruction code is programmed. A first control circuit for extracting and concatenating from N instruction codes to generate and outputting a 32-bit instruction code; and the first control circuit. A second decoder for decoding the 32-bit instruction code output from the second decoder, and a decoding result for the second selection signal to selectively output the decoding result of the second decoder or the decoding result of the first decoder A microprocessor having a selection circuit. 3. N (N ≧ 4) instruction queues for storing instruction codes of predetermined bits, and N instruction queues received from each of the instruction queues according to a first selection signal designating an instruction code to be decoded. A selection circuit for selecting and outputting an instruction code to be decoded from among the instruction codes, and a first decoder for decoding the instruction code of the predetermined bit selected by the selection circuit, When the content of the instruction code of the predetermined bit selected according to the first selection signal corresponds to a part of the instruction having a bit length larger than the predetermined bit, the second selection signal is output and the selection is performed. The instruction code that is continuous with the instruction code on the program is extracted from the N instruction codes and connected in accordance with the external signal indicating the endian. A first control circuit that generates and outputs an instruction code corresponding to an instruction; a second decoder that decodes the instruction code output from the first control circuit; and the second selection signal is the second And a decoding result selection circuit for selecting and outputting the decoding result of the decoder or the decoding result of the first decoder. 4. N (N ≧ 4) instruction queues for storing 16-bit instruction codes and N number of instruction queues received from each of the instruction queues according to a first selection signal designating an instruction code to be decoded. A microprocessor comprising: a selection circuit that selects and outputs an instruction code to be decoded from the instruction codes; and a first decoder that decodes the 16-bit instruction code selected by the selection circuit. When the content of the 16-bit instruction code selected according to the selection signal corresponds to a 32-bit length instruction, a second selection signal is output, and the instruction code consecutive to the selected 16-bit instruction code is programmed. It takes out from N instruction codes and concatenates them according to the external signal indicating endian to generate and output a 32-bit instruction code. A first control circuit, a second decoder that decodes a 32-bit instruction code output from the first control circuit, and the second selection signal is the decoding result of the second decoder or the second decoder. A decode result selection circuit for selecting and outputting a decode result of one decoder. 5. The microprocessor according to claim 1, further comprising a second control circuit which outputs the first selection signal based on a second selection signal.
2. The microprocessor according to 2, 3 or 4.