JP2003228480A - Interface device for image display device of pachinko game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface device for an display device of a pachinko game machine in which data is transferred in high-speed using a low-speed CPU and various images can be drawn thereby. <P>SOLUTION: An interface device 3 interfaces a CPU 4 with a circuit for a display 7 having a data bus width larger than the data bus width of this CPU. The interface device 3 comprises; an address register 10 to designate a write address A1 to write data on the circuit for the display 7 from the CPU; a write register 20 to store a write data D1 temporarily to write the data on the address for the circuit for the display 7 designated by the address register 10; a write signal generation part 12 to generate a write signal 11 for directing a write instruction to write data D1 to the circuit for the display 7 when the data D1 is written into the write register 20; and an address increment part 13 to increment an address value inside the address register 10 when the write data D1 is written on the circuit for the display. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device in an image display device of a pachinko machine, and more particularly to an image display device of a pachinko machine capable of high speed data transfer while using a low speed CPU. Interface device.

[0002]

2. Description of the Related Art Conventionally, in a high-performance display LSI such as for 3D drawing, only an interface with a high-performance and high-speed CPU is possible. However, such a high-performance and high-speed CPU is expensive, and further, a peripheral device of the CPU such as a program memory is also expensive.

In recent years, a pachinko machine is required to have a high level of display content, but due to the conditions such as cost and delivery time, it is not possible to use a high-performance and high-speed CPU. Therefore, it is possible to connect to an inexpensive CPU. A display LSI, which has a relatively poor ability, was used. Therefore, in order to perform highly versatile drawing, as shown in FIG. 14, since all the circuits are configured by circuits that operate at high speed, there is a drawback that the manufacturing cost becomes high.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and, in particular, to enable high-speed data transfer of image data while using a slow CPU. The present invention provides an interface device for an image display device of a new pachinko machine that enables a variety of drawings.

[0005]

In order to achieve the above-mentioned object, the present invention basically adopts the technical constitution as described below.

That is, the first aspect of the interface device in the image display device of the pachinko machine according to the present invention is C
An interface device in an image display device of a pachinko machine that interfaces a PU and a display circuit having a data bus width different from the data bus width of the CPU, for writing data from the CPU to the display circuit. An address register for designating a data write address of the display circuit, a write register for temporarily storing write data in order to write data to the address of the display circuit designated by the address register, and the write When data is written to the register,
A write signal generation unit that generates a write signal for instructing the display circuit to write the write data, and an address value in the address register when the write data is written to the display circuit. And an address increment unit for incrementing. In the second aspect, the write register is composed of a plurality of write registers, and the write register is predetermined among the plurality of write registers. When the write data is written in the write register of the specified address, the write signal generation unit, based on the address data designating the address of the write register,
The write start is output to the display circuit, and the address increment unit is configured to increment the address value of the address register after the write data is written in the display circuit. The third aspect is a CPU
An interface device in an image display device of a pachinko machine that interfaces a display circuit having a data bus width different from the data bus width of the CPU, wherein the interface device is provided for reading data from the display circuit to the CPU. An address register for designating a data read address of the display circuit and read data read from the display circuit are temporarily stored in order to read data from the address of the display circuit designated by the address register. A read register, a read signal generator that generates a read signal for reading the next data to the display circuit when the read data stored in the read register is read, and the read register. When the stored read data is read, the address in the address register is And an address increment unit that increments the address value. In the fourth aspect, the read register is composed of a plurality of read registers. When the read data is read from the read register of the predetermined address, the read signal generation unit outputs a read signal for reading the next read data to the display circuit, and further, the address increment. The section is configured to increment the address value of the address register after the read data is transferred from the display circuit to the read register. Further, the fifth aspect is ,
The interface device is provided with a wait signal generation unit, and while the read data is being transferred from the display circuit to the read register, the wait signal generation unit is provided to the CPU and the address increment unit. The sixth aspect is characterized in that it is configured to output a wait signal, and the sixth mode interfaces a CPU and a memory with a display circuit having a data bus width different from the data bus widths of the CPU and the memory. An interface device in an image display device of a pachinko machine, which is provided with a DMA device,
Data is transferred from the memory to the display circuit, and the seventh mode is the address bus of the memory, the data bus is the address bus of the CPU,
The eighth aspect is characterized in that each of them is connected to a data bus, and the eighth aspect is that the address bus of the memory and the data bus are different from the address bus of the CPU and the data bus. The CPU is configured to hold the bus right while the DMA device transfers data from the memory to the display circuit. The ninth aspect is characterized in that the CPU and the display circuit have different access speeds.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION A specific example of an interface device in an image display device of a pachinko machine according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the overall structure, and FIG.
The low speed operation unit 1 and the high speed operation unit 2 are connected via an interface circuit 3.

The low-speed operation unit 1 is composed of a low-speed CPU 4, a memory 5, and a CG memory 6 for storing image data, and the high-speed operation unit 2 is a high-speed LSI 7 for display and image data for display. And a display unit 9 such as a liquid crystal display device. Also, FIG.
FIG. 6B is a diagram showing a configuration in which a high speed CG memory is used and the CG memory is provided on the high speed operation unit 2 side.

As described above, according to the present invention, the low speed operation unit 1 and the high speed operation unit 2 are connected through the interface circuit 3 so that the high speed image drawing can be controlled by the low speed CPU.

(First Specific Example) FIG. 1A, FIGS. 2 to 4
FIG. 4 is a diagram showing a specific example of an interface device that transfers data from a low-speed CPU side to a display circuit that operates at high speed. In these figures, the data bus width is larger than the data bus widths of the CPU 4 and this CPU. An interface device 3 in an image display device of a pachinko machine that interfaces with a display circuit 7, wherein a data write address A1 of the display circuit 7 is written in order to write data from the CPU to the display circuit 7. An address register 10 for designating, a write register 20 for temporarily storing write data D1 in order to write data to the address of the display circuit 7 designated by the address register 10, and data in the write register 20. When D1 is written, the write data D1 is written to the display circuit 7. A write signal generation unit 12 for generating a write signal 11 for instructing a write operation, and an address increment unit 13 for incrementing an address value in the address register 10 when the write data D1 is written in the display circuit 7. An interface device in an image display device of a pachinko machine is shown, and the write register 20 is provided.
Is composed of a plurality of write registers (Write data registers 3 to 0), and among the plurality of write registers, a write register (Wri of a predetermined address is written.
te data register 0), when the write data is written, a register write signal W1 designating writing of the write register (Write data register 0)
Based on the above, the write signal generation unit 12 outputs the write signal 11 to the display circuit 7, and the address increment unit 13 further includes the write data D.
An interface circuit in an image display device of a pachinko machine is shown in which the address value of the address register 10 is incremented after 1 is written in the display circuit 7.

The first specific example will be described in more detail below.

The data of the CPU shown in FIG. 2 has an 8-bit structure, and the address of this CPU has a 16-bit structure. On the other hand, the data of the display circuit 7 has a 32-bit structure and an address. Has a 24-bit structure.

Therefore, as shown in FIGS. 2 and 3, the address register 10 for designating the address of the display circuit 7 has three 8-bit address registers, that is, Wr.
The write register 20 configured by a 24-bit address register composed of the ite address registers 2 to 0 temporarily stores the write data D1. The write register 20 is four 8-bit write registers, that is, the Write data registers 3 to 0.
Is a 32-bit write register consisting of

Reference numeral 15 is an address decoder for decoding the address of each of the address register 10 and the write register 20, which is Wr in FIG.
In order to write write data to the ite data register 0, the register write signal W from the address decoder 15 is written.
When 1 is output, the write signal generator 12 outputs the write signal 11 to the display circuit 7 based on the register write signal W1.
Then, after the write data D1 is written in the display circuit 7, the address value of the address register 10 is incremented so that the above-mentioned data writing can be continuously performed.

FIG. 4 is a flow chart showing a procedure for writing write data to the display circuit 7. First,
Address data for designating the data write address of the display circuit 7 is written in the address register 10 (step S1). Next, Write data register 3
Write data to 0 to 0 in order (step S2
~ S5). Then, when the data is written to the write data register 0 (step S6), the data of the write data registers 3 to 0 is written to the display circuit 7 (step S7). When the writing of the write data D1 is completed, the address value of the address register 10 is incremented (step S8), and the incremented address value is written in the address register 10 (step S99). In this way, the data is continuously written in the display circuit 7.

(Second Specific Example) FIG. 1A, FIG. 5 to FIG.
FIG. 4 is a diagram showing a specific example of an interface device that transfers data from a high-speed operating display circuit to a low-speed CPU side. In these figures, the data bus width is larger than the data bus widths of the CPU 4 and this CPU. An interface device 3A in an image display device of a pachinko machine that interfaces with the display circuit 7, and in order to read data from the display circuit 7 to the CPU 4, a data read address A2 of the display circuit 7 is set. An address register 11 for designating and a read register for temporarily storing the read data D2 read from the display circuit 7 in order to read data from the address A2 of the display circuit 7 designated by the address register 11. 21,
Read data D2 stored in the read register 21
Is read, the read signal generator 22 for generating the read signal 25 for the next data read and the read data D2 stored in the read register 21 are read to the display circuit 7. An interface device in an image display device of a pachinko machine is shown, which comprises an address increment unit 23 that increments the address value in the address register 11 when the read register 21 is read. Is composed of a plurality of read registers (Read data registers 3 to 0), and when read data is read from the read register (Read data register 3) of a predetermined address among the plurality of read registers. The read signal generator 22 is a read-out circuit for reading the read data from the display circuit 7. The signal 25 is output to the display circuit 7, and the address increment unit 23 further transfers the read data D2 from the display circuit 7 to the read register 21 and then outputs the address value of the address register 11. The interface device in the image display device of the pachinko machine is characterized in that it is configured to increment, and the interface device 3A is provided with a weight signal generator 27.
While the read data D2 is being transferred from the display circuit 7 to the read register 21, the wait signal generator 27 outputs a wait signal 28 to the CPU 4 and the address incrementer 23. An interface device in an image display device of a pachinko machine is shown.

The second specific example will be described in more detail below.

The data of the CPU 4 shown in FIG. 5 has an 8-bit structure as in FIG. 2, and the address of this CPU is 1
The data of the display circuit 7 has a 32-bit structure, and the address has a 24-bit structure.

Therefore, as shown in FIGS. 5 and 6, the address register 11 for designating the address of the display circuit 7 has three 8-bit address registers, that is, Re.
The read register 21 configured by a 24-bit address register including the ad address registers 2 to 0 and temporarily storing the read data D2 includes four 8-bit read registers, that is, the Read data registers 3 to 32. It is a bit write register.

Reference numeral 15 is an address decoder which decodes the address of each of the address register 11 and the read register 21, and in FIG.
When the address of the Read data register 3 is decoded to read the data of the ad data register 3, the read signal generation unit 22 outputs the read signal 25 for reading the read data of the display circuit 7 to the display circuit 7.
Further, the address increment unit is configured to increment the address value of the address register 11 after the read data is transferred from the display circuit 7 to the read register 21.

Further, the interface device 3A includes
A wait signal generation unit 27 is provided, and the read data D2
However, while being transferred from the display circuit 7 to the read register 21, the wait signal generator 27 outputs a wait signal 28 to the CPU 4, and during this time, the CPU 4 does not read data from the read register 21. I have to. Further, the wait signal generator 27 outputs a wait signal 28 to the address incrementer 23,
During this period, the increment operation is not performed.

FIG. 7 is a flow chart showing the procedure for reading data from the display circuit 7. The left side of the figure is C
The procedure of reading data from the read register 21 by the PU 4 is shown, and the right side of the figure shows the data read operation of the display circuit 7 performed in parallel with the read operation of the CPU 4.

First, address data for designating the data read address of the display circuit 7 is written in the address register 11 (step S11). Next, CPU
4 reads the data from the display circuit 7 into the Read data register 3 (step S12). At this time, the wait signal generator 27 receives the Rea from the address decoder 15.
The address signal of the d data register 3 is received, the wait signal 28 is output to the CPU 4 and the address increment unit 23 based on this signal, and the CPU 4 and the address increment unit 23 are put in the wait state (step S13). At the same time, the read signal generation unit 22 receives the address signal of the Read data register 3 from the address decoder 15 and writes the next read data into the read registers 3 to 0 for the display circuit 7 based on this signal. A read signal for instructing the display circuit 7 is output to the display circuit 7 (step S14).
To the read registers 3 to 0 are transferred (step S15). Then, when the data transfer from the display circuit 7 to the read registers 3 to 0 is completed, the wait signal is released (step S16), the read operation from the read register 21 of the CPU 4 is restarted, and the data of the read registers 2 to 0 is restarted. Is read by the CPU 4 (steps S19 to S21).

On the other hand, after the wait signal is released (step S16), the address of the address register 11 is incremented and the updated address value is written in the address register 11 (steps S17, S1).
8).

When one cycle of the transfer operation is completed in this way, the next data transfer cycle starts (step S22).

(Third Concrete Example) FIG. 1 (a), FIG. 8 to FIG.
0 is a diagram showing a third specific example of the present invention. In these figures, a pachinko that interfaces the CG memory 3 and the display circuit 7 having a data bus width larger than the data bus width of the CG memory is shown. Which is an interface device 3B in an image display device of a machine, wherein a DMA device 31 is provided, and data is transferred from the CG memory 30 to the display circuit 7 via the DMA device 31. An interface device in an image display device is shown.

The third specific example will be described in more detail below.

The data of the CPU 4 and the CG memory 30 shown in FIG. 8 have an 8-bit structure as in FIG.
The addresses of the U4 and CG memory 30 have a 16-bit configuration, whereas the data of the display circuit 7 has a 32-bit configuration and the address has a 24-bit configuration.

Interface device 3B of the third specific example
Includes a DMA device 31, and the DMA device 31
DMA timing control unit 32, transfer source address, that is, transfer source address counter 33 that indicates the address of CG memory 30, transfer destination address, that is, transfer destination address counter 34 that indicates the address of display circuit 7, and transfer count And a DMA start register 36 for instructing the start of DMA.

The interface device 3B has a C
The transfer source address register 37 that stores the transfer start address of the G memory 30, the transfer destination address register 38 that stores the transfer start address of the display circuit 7, the transfer number register 39 that stores the transfer number, and the DMA transfer The data buffer 40 is configured to start DMA transfer from the CG memory 30 to the display circuit 7 when predetermined data is set in the DMA start register 36.

In the interface circuit 3B shown in FIG. 8, the transfer source address register 37 is composed of two 8-bit address registers, that is, a 16-bit address register including the DMA transfer source address registers 1 and 0, The transfer destination address register 38 is composed of three 8-bit address registers, that is, a 24-bit address register consisting of DMA transfer destination address registers 2 to 0, and the transfer number register 39 is two 8-bit address registers, that is, It is composed of a 16-bit address register consisting of DMA transfer number registers 1 and 0.

FIG. 9 is a flow chart showing the operation of the third specific example using DMA, and FIG. 10 is a flow chart showing the data transfer operation of FIG. 9 in detail.

As shown in FIGS. 9 and 10, the CG memory 3 is stored in the transfer source address register 37 before the data transfer.
Write the transfer start address of 0 (step S31),
Next, the transfer start address of the display circuit 7 is written to the transfer destination address register 38 (step S32), the transfer number is written to the transfer number register 39 (step S33),
Finally, when predetermined data is written in the DMA start register 36 (step S34), the DMA timing control unit 3
The CPU 2 outputs a bus request signal 41 to the CPU 4 so as to give up the bus. If the CPU 4 can pass the bus use right, the CPU 4 transfers the bus use right to the
The DMA transfer is possible under the control of the DMA timing control unit 32 by sending it to the DMA device 31 side (step S35). The data in the registers 37, 38, 39 are set in the counters 33, 34, 35, respectively (step S36), and the DMA transfer is performed via the DMA data buffer 40 (step S37). When the data transfer is completed, the bus request signal is released, and the bus use right is converted to the CPU 4, whereby the CPU 4 can be controlled (step S38) and the next DMA transfer can be executed. (Step S39).

FIG. 10 is a flow chart showing step S37 in detail. During the transfer, the DMA timing control unit 32 receives the address of the CG memory 30 from the transfer source address counter 33 (step S41), and outputs a read signal C for reading the data of the received address.
The read data is output to the G memory 30, the read data is stored in the DMA data buffer 40, and when the data buffer is full (step S42), the address to be written in the display circuit 7 is received from the transfer destination address counter 34. (Step S43), a write signal is output to the display circuit 7, and the data stored in the DMA data buffer 40 is written into a predetermined address of the display circuit 7 (step S44). Then, the transfer source address counter 33 and the transfer destination address counter 34 are incremented, the transfer number counter 35 is decremented (step S45), and if the transfer number counter is not "0", the next address is transferred. , The number of data set in the transfer number register 39 is transferred (step S46).

(Fourth Concrete Example) FIGS. 11 to 13 are views showing a fourth concrete example of the present invention. In these figures, C is shown.
The address bus and data bus of the G memory 50 are the CPU 4
Is not connected to the address bus and the data bus, and the CPU 4 is configured to retain the bus use right even while the DMA device 31A transfers data from the CG memory 50 to the display circuit 7. The interface device in the image display device of the pachinko machine is shown.

This configuration corresponds to FIG. 1 (b). The interface circuit 3C of the fourth specific example also includes a DMA device 31A similar to that of the third specific example.

In the third specific example, the address bus and the data bus of the CG memory 30 are connected to the address bus and the data bus of the CPU 4, respectively. However, the CG memory 50 of the fourth specific example is connected. The configuration is the same as that of the third specific example except that a high-speed CG memory is used, and therefore, both the address bus and the data bus of the CG memory 50 have a 16-bit configuration.

Further, in the fourth specific example, as shown in FIG. 12, the CPU 4 is configured to be able to perform other processing during the DMA transfer. However, the DMA transfer method is the same as the third specific example. Is the same.

FIG. 13 is a flow chart showing an example in which the DMA processing is performed by the interrupt processing. Also in the case of this example, the CPU 4 is configured to be able to perform other processing during the DMA transfer. The present invention is a basic architecture that is compatible with various application software.

[0041]

Since the interface device in the image display device of the pachinko machine according to the present invention is constructed as described above, the CPU and its peripheral circuits can be constructed inexpensively as in the conventional case and the high speed data transfer can be achieved. By making it possible, more versatile drawing became possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of a first specific example.

FIG. 3 is a diagram showing a configuration of a register shown in FIG.

FIG. 4 is a flowchart showing the operation of the first specific example.

FIG. 5 is a block diagram showing a configuration of a second specific example.

6 is a diagram showing a configuration of a register in FIG.

FIG. 7 is a flowchart showing the operation of the second specific example.

FIG. 8 is a block diagram showing a configuration of a third specific example.

FIG. 9 is a flowchart showing the operation of the third specific example.

10 is a flowchart showing details of a DMA transfer unit in FIG.

FIG. 11 is a block diagram showing a configuration of a fourth specific example.

FIG. 12 is a flowchart showing the operation of the fourth specific example.

FIG. 13 is a flowchart showing another operation of the fourth specific example.

FIG. 14 is a block diagram showing a conventional configuration.

[Explanation of symbols]

3, 3A, 3C interface circuit 4 CPU 10 address register 11 Write signal 12 Write signal generator 13, 23 Address increment unit 15 Address recorder 20 write register 21 read register 22 Read signal generator 25 Read signal 27 Weight signal generator 28 weight signal 31, 31A DMA device 32 DMA timing controller 33 Transfer source address counter 34 Transfer destination address counter 35 Transfer counter 36 Transfer Start Register 37 Transfer source address register 38 Transfer destination address register 40 DMA data buffer 39 Transfer Count Register

Claims (9)

[Claims] 1. An interface device in an image display device of a pachinko machine for interfacing a CPU and a display circuit having a data bus width different from the data bus width of the CPU, wherein data is transferred from the CPU to the display circuit. An address register for designating a data write address of the display circuit for writing, and a write for temporarily storing write data for writing data to the address of the display circuit designated by the address register. A register, a write signal generator that generates a write signal for instructing the display circuit to write the write data when data is written in the write register, and the write circuit writes the write signal in the display circuit. When I wrote the data,
An interface device in an image display device of a pachinko machine, comprising: an address increment unit that increments an address value in the address register. 2. The write register comprises a plurality of write registers, and when the write data is written to a write register of a predetermined address among the plurality of write registers, an address of the write register The write signal generation unit outputs the write start to the display circuit, and the address increment unit further includes the address increment unit after the write data is written to the display circuit. The interface device in an image display device of a pachinko machine according to claim 1, wherein the interface device is configured to increment the address value of the address register. 3. An interface device in an image display device of a pachinko machine for interfacing a CPU and a display circuit having a data bus width different from the data bus width of the CPU, the data being transferred from the display circuit to the CPU. Address register for designating a data read address of the display circuit for reading, and read data read from the display circuit for reading data from the address of the display circuit designated by the address register. And a read signal generation unit that generates a read signal for the next data read to the display circuit when the read data stored in the read register is read. When the read data stored in the read register is read, And address increment unit increments the address value in the address register, in in interface device to the image display device of the pinball machine, characterized by being configured. 4. The read register comprises a plurality of read registers, and when read data is read from a read register of a predetermined address among the plurality of read registers, the read signal generation unit Is
A read signal for reading the next read data is output to the display circuit, and further, the address increment unit, after the read data is transferred from the display circuit to the read register, The interface device in the image display device of a pachinko machine according to claim 3, wherein the interface device is configured to increment the address value. 5. The interface device is provided with a wait signal generator, and while the read data is being transferred from the display circuit to the read register,
The interface device in an image display device of a pachinko machine according to claim 4, wherein the wait signal generation unit is configured to output a wait signal to the CPU and the address increment unit. 6. An interface device in an image display device of a pachinko machine for interfacing a CPU and a memory with a display circuit having a data bus width different from the data bus width of the CPU and the memory, wherein a DMA device is provided. An interface device in an image display device of a pachinko machine, wherein data is transferred from the memory to a display circuit via the DMA device. 7. The interface device in an image display device of a pachinko machine according to claim 6, wherein an address bus and a data bus of the memory are connected to an address bus and a data bus of the CPU, respectively. . 8. The address bus and the data bus of the memory are connected to the interface device by a bus different from the address bus and the data bus of the CPU, and the DMA device displays from the memory. 7. The interface device in the image display device of a pachinko machine according to claim 6, wherein the CPU is configured to hold the bus use right even during the data transfer to the circuit for use. 9. The interface device in an image display device for a pachinko machine according to claim 1, wherein the CPU and the display circuit have different access speeds.