JP2003224778A - Image pickup device and image pickup method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image pickup device and an image pickup method by which sampling signals can individually and properly be adjusted for pixels constituting an imaging element. <P>SOLUTION: In a digital camera 10 including an electric charge coupled device (CCD) type image pickup part 16 and a correlational dual sampling part (CDS part) 22 in which an image signal 16a detected by the image pickup part 16 is inputted and that samples the image signal 16a, sampling signals 20b, 20c for sampling are inputted in the CDS part 22. The sampling signals 20b, 20c are generated according to a cycle of the image signal 16a and a cycle of a clock of a digital signal processing system 32 different from the cycle of the image signal 16a and inputted in the CDS part 22. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device such as a charge coupled device.
e: Corresponding Double Sampling (hereinafter referred to as CDS), which receives an image signal read by a CCD in an image sensor and removes noise.

[0002]

2. Description of the Related Art Solid-state image pickup devices include CCD type image pickup devices and XY address type image pickup devices. In CCD type image sensor,
As is well known, when the imaging cell array is horizontally scanned, a CCD output signal including a reset component, a feedthrough signal and a pixel signal is output for one pixel period. The output circuit for solid-state imaging devices that receives this CCD output signal and outputs a video signal with minimized noise outputs a video signal from which noise that is correlated to the feedthrough signal included in the pixel signal has been removed There is a sampling (CDS) method. CD
The S method may also be used in an XY address type image sensor.

In the CDS system, the output circuit for the solid-state image pickup device requires two kinds of sampling pulses in order to extract the feedthrough signal and the pixel signal from the output signal of the solid-state image pickup device. Some conventional solid-state imaging devices take into consideration variations in individual ICs and solid-state imaging devices when adjusting sampling positions.

For example, a technique has been disclosed in which the chroma signals of all the pixels included in one field are integrated and the sampling position is controlled for each field so that the integrated value becomes maximum (see Patent Document 1).

[0005]

[Patent Document 1] JP-A-6-225222.

[0006]

In the case of the above prior art,
Since the integrated value over one field is used, the sampling position can be determined in consideration of the average characteristics of the entire image sensor. That is, in the case of the conventional technique, the sampling position is uniformly corrected for all the pixels forming the image sensor. However, it is not possible to determine the sampling position of the pixels forming the image pickup device on a pixel-by-pixel basis at an appropriate position for the pixel.

It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide an image pickup apparatus and method capable of individually and appropriately adjusting sampling signals for pixels constituting an image pickup element.

[0008]

In order to solve the above problems, the present invention inputs an image pickup device and an image signal detected by the image pickup device, and samples the image signal.
In an imaging device including a CDS unit, a CDS unit receives a sampling signal for sampling, and the sampling signal follows a first cycle of the image signal and a second cycle different from the first cycle. It is generated and input to the CDS section. According to the present invention, the sampling signals of the pixels forming the image pickup device can be individually adjusted.

In the present invention, the second cycle may be the cycle of the reference clock of the digital processing system of the image pickup device. According to this, the sampling signal can be generated in consideration of the reference clock of the digital processing system. For example, when the image signal includes noise synchronized with the reference clock, the image signal can be sampled while avoiding the noise.

The second cycle is a cycle of the horizontal synchronizing signal, and the timing of inputting the sampling signal to the CDS section may change at a predetermined position on the horizontal line. In this case, the sampling signal can be generated in consideration of the horizontal synchronizing signal. For example, when the image signal includes noise synchronized with the horizontal synchronizing signal, the image signal can be sampled while avoiding the noise.

Further, the second cycle is a cycle of the vertical synchronizing signal, and the timing of inputting the sampling signal to the CDS section may change at a predetermined position on the vertical line. According to the present invention, the sampling signal can be generated in consideration of the vertical synchronization signal.

In any of the above cases, the sampling signal can be generated by changing the phase of the signal having the first period.
According to this, the present invention can be achieved only by adding a small-scale circuit.

Further, in any of the above cases,
The sampling signal may be generated so as to avoid the position of noise included in the image signal and having the second period. According to the present invention, it becomes possible to perform noise removal for each individual pixel.

Further, in order to solve the above-mentioned problems, the image pickup method according to the present invention uses an image signal detected by the image pickup device as a CD.
In an imaging method of inputting to an S section and sampling an image signal, a sampling signal for sampling the image signal is supplied in accordance with a first cycle of the image signal and a second cycle different from the first cycle. The method is characterized by including a step of generating and a step of inputting the generated sampling signal to the CDS unit. According to this method
Similar to the above-described image pickup apparatus, the sampling signals of the pixels forming the image pickup element can be individually adjusted.

In the above-mentioned image pickup method, the second cycle may be a cycle of the reference clock of the digital processing system of the image pickup apparatus including the image pickup device and the CDS section.

Further, in the above-mentioned imaging method, the second cycle is a cycle of the horizontal synchronizing signal, and this method is
The method may include changing the timing of inputting the sampling signal to the CDS unit at a predetermined position on the horizontal line.

Further, in the above-mentioned imaging method, the second cycle is a cycle of the vertical synchronizing signal, and this method comprises a step of changing the timing of inputting the sampling signal to the CDS section at a predetermined position on the vertical line. Can be included.

In any of the above image pickup methods,
The method may include generating the sampling signal by changing the phase of the signal having the first period.

In any one of the above-mentioned image pickup methods,
The method may include generating the sampling signal so as to avoid the position of noise included in the image signal and having the second period.

In the image pickup apparatus including the image pickup device according to the present invention and the CDS unit that receives the image signal detected by the image pickup device and samples the image signal, the CDS unit is a sampling signal for sampling. The sampling signal may be generated according to the pixel position and input to the CDS unit. According to this device, the sampling signals of the pixels forming the image sensor can be individually and appropriately adjusted.

Further, in this image pickup apparatus, the apparatus may include storage means having information for generating a sampling signal according to a pixel position, and the sampling signal may be generated according to the information.

Further, in this image pickup apparatus, it is preferable that the sampling signal is generated in consideration of noise included in the image signal corresponding to the pixel position. As a result, an image with less noise can be obtained.

Further, in the image pickup apparatus, when the noise included in the image signal corresponding to the pixel position is larger than a predetermined value, the sampling signal may not be generated.

By the way, the above-mentioned problem is to reduce noise contained in an image signal in an image pickup apparatus including an image pickup element and a CDS section for sampling the image signal by inputting the image signal detected by the image pickup element. In the target noise reduction mode, a frequency reduction unit that lowers the frequency of the drive signal supplied to the image pickup device, and a signal generation unit that generates a sampling signal so that sampling is performed while avoiding the position of noise included in the image signal. And the CDS section is also achieved by inputting the sampling signal generated by the signal generating means.

In appropriately adjusting the sampling signals individually for the pixels forming the image pickup device, in the noise reduction mode, for example, in the high-sensitivity shooting mode or the processing time unlimited mode, the drive signal supplied to the image pickup device is changed. It is possible to reduce the frequency. When the frequency of the drive signal decreases, the pulse width of the image signal increases. On the other hand, the time width of noise included in the image signal is irrelevant to the frequency of the drive signal, and the time width of noise does not change even if the frequency of the drive signal is reduced. Therefore, the period in which the image signal is free of noise is relatively increased, which facilitates sampling of the image signal while avoiding the position of the noise.

In the high-sensitivity shooting mode of the digital still camera, noise countermeasures are more important than in the low-sensitivity shooting mode. This is because noise is amplified because the gain is high in the high-sensitivity shooting mode. According to the present invention, in the high-sensitivity shooting mode or the like, the image pickup element driving frequency is lowered to reduce the noise included in the sampled image signal, and a noise countermeasure is taken. Since the driving frequency is lowered, the operating speed of the camera or the like is slowed down, but there are few problems because it is limited to the high-sensitivity shooting mode and the like.

In the processing time unlimited mode, regardless of whether it is high-sensitivity shooting or normal shooting, for example, the shooting interval between the first shooting time and the second shooting time is long, This is a case where there is time to process the captured image data. The image data processing includes image data sampling, image processing, storage processing on a recording medium, and the like. Even in the processing time non-limitation mode, it is possible to lower the imaging element drive frequency, and by lowering it, noise can be easily removed, and a good image with less noise can be obtained.

Further, the above-mentioned problem is to reduce the noise contained in the image signal in the image pickup method in which the image signal detected by the image pickup device is input to the CDS section to sample the image signal. In the mode, a step of lowering the frequency of the drive signal supplied to the image sensor, a step of generating a sampling signal for sampling the image signal, and a sampling signal for performing sampling while avoiding the position of noise included in the image signal And the generated sampling signal
It is also achieved by including the step of inputting to the CDS section.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an image pickup device according to the present invention will be described in detail with reference to the accompanying drawings.

The image pickup apparatus of the present embodiment sets the phase of the sampling pulse of the CDS section according to the pixel position in one field in order to remove the influence of noise caused by the reference clock of the digital signal processing system in the image pickup apparatus. It is to adjust (change).

Although a digital still camera using a CCD type image pickup device will be described in the following embodiments, the present invention is also applicable to an image pickup apparatus using an XY address type image pickup device having a CDS section. . In the following embodiments, the image pickup apparatus is a digital still camera, but the present invention is not limited to the digital still camera.
For example, it can be applied to a digital video camera and an analog video camera having a digital processing circuit.

The noise is generated in synchronization with the reference clock of the digital signal processing system, spills into the analog signal processing system in the image pickup apparatus, and is a part of the analog signal processing system.
It is added to the output of the CCD image sensor and the output changes. Therefore, the noise component of the image quality increases. This phenomenon remarkably appears when the gain of the automatic gain control circuit (AGC) is large, for example, when photographing darkness.

Since noise is superimposed on the output of the CCD type image pickup device, that is, the input signal of the CDS section, in this embodiment,
The phase of the sampling pulse of the CDS section is adjusted so as to avoid the position of noise superimposed on the input signal. As a result, a low noise image can be obtained.

The cycle of the reference clock of the analog signal processing system (first cycle) may be different from the cycle of the reference clock of the digital signal processing system (second cycle). Further, noise is often generated when the reference clock signal of the digital signal processing system rises. The present embodiment is an example of avoiding noise that occurs at the rise of the reference clock signal of the digital signal processing system. The phase of the sampling pulse of the CDS section is determined in consideration of the first cycle and the second cycle.

FIG. 1 shows the configuration of a digital still camera 10 of the embodiment to which the present invention is applied. In the following, illustration and description of parts that are not directly related to the present invention will be omitted. Here, the reference numbers of signals are represented by the reference numbers of the connecting lines in which they appear. The present invention can also be applied to a video camera.

In the digital still camera 10 shown in FIG. 1, incident light from a subject enters the optical lens system 12. Optical lens system
Although not shown in FIG. 12, the zoom mechanism that adjusts the angle of view of the screen by adjusting the arrangement of these optical lenses and the subject and camera
AF (Automatic Focu
s: Automatic focus) adjustment mechanism is included. The optical lens system 12 includes an analog timing generator described later.
A drive signal (not shown) for operating these mechanisms is supplied from the (analog system TG) 20.

This drive signal is a signal for a photographing operation performed under the control of the system controller 14. The system controller 14 photoelectrically converts the A / D converter 18 in the imaging unit 16.
In addition to performing AF processing based on the signal charge 18a that has been converted into a digital signal, the aperture and exposure time are calculated as AE (Automatic Exposure) processing.

In the image pickup section 16, an image pickup element (light receiving element) for photoelectric conversion is arranged so as to form a plane (image pickup surface) orthogonal to the optical axis of the optical lens system 12. Further, a color filter for color separation is arranged on the incident light side of the image sensor.

A CCD type solid-state image pickup device is used as the image pickup element. In the image pickup unit 16, the signal charge obtained by photoelectric conversion in accordance with the timing signal 20a supplied from the analog TG 20 is subjected to a predetermined timing, for example, by field shift during the off period of the electronic shutter in the signal reading period. Read to the vertical transfer path. The signal charges line-shifted from the vertical transfer path are supplied to the horizontal transfer path. The signal charge that has passed through this horizontal transfer path is converted into an analog voltage signal 16a by current / voltage conversion by an output circuit (not shown), and is output to the CDS unit 22.

The CDS unit 22 is the output signal 16a of the CCD image pickup device.
Clamp circuit that clamps the feed-through level of C with the timing signal 20b from the analog TG 20 and C
The signal level of the output signal 16a of the CD type image sensor is set to the analog type T
And a sample and hold circuit for holding by the timing signal 20c from G20. The CDS unit removes noise components contained in the output signal 16a of the CCD image pickup device and sends the analog output signal 22a to the gain control amplifier (GCA) 24. GCA
24 adjusts the gain of the signal 22a and sends it to the A / D converter 18 as an analog signal 24a.

The A / D conversion section 18 receives the analog signal 2
It has an A / D converter which quantizes the signal level of 4a by a predetermined quantization level and converts it into a digital signal 18a. A
The / D converter 18 outputs the converted digital signal 18a to the signal processor 26 according to the timing signal 20d.

Although not shown, the signal processing unit 26 includes a gamma correction circuit for correcting colors, an AWB (Automatic White Balance) circuit for automatically adjusting white balance, and the like. The plane processing unit that creates plane data for the entire screen for each color is also included in the signal processing unit 26.

The RGB pixel data at each pixel position thus obtained is converted into a signal 26a, which is converted into a signal processing unit 26.
Is output to a memory or the like (not shown). Signal processing unit 26
Signal processing from the digital timing generator (digital TG) 28
Processing is performed in synchronization with 28a.

The system control unit 14 is, for example, a CPU (Cent
ral Processing Unit: Central processing unit).
The system control unit 14 has a ROM (Read Only Memory) in which the operation procedure of the digital still camera 10 is written. The system control unit 14 uses the information in the ROM and the like to generate control signals and the like for controlling the operation of each unit.

That is, the system control unit 14 calculates information about focusing and aperture / exposure time as AF / AE processing based on the signal 26a, and sends the obtained information and the calculated value to the analog system TG 20, The analog TG 20 generates a drive signal necessary for AF / AE processing.

Incidentally, the system control unit 14
A signal (not shown) for instructing the start of processing is output to each unit of the camera. Further, the system control unit 14 outputs a reset signal 40 to the digital system TG 28, the analog system TG 20, and the CG 34 to synchronize them, when the power of the digital camera 10 is turned on. . Further, data regarding the delay amounts of the timing signals 20b and 20c is sent to the analog TG 20 via the serial control line 60 when the power of the digital camera 10 is turned on. Details of the delay amount and the reset signal 40 will be described later.

The clock generator 34 has a built-in oscillator and outputs the generated clock signal 34a to the analog TG 20 and the digital TG 28. The analog TG 20 is a circuit that receives the clock signal 34a and generates a drive signal and a timing signal for synchronizing the operation of the entire analog signal processing system 30. As described above, this circuit outputs the timing signals 20a, 20b, 20c, 20d to the image pickup unit 16, the CDS unit 22, and the A / D conversion unit 18, respectively.

On the other hand, the digital TG 28 uses the clock signal 3
4a is a circuit for inputting 4a and generating a timing signal for synchronizing the operation of the entire digital signal processing system 32.

Of the above-mentioned respective parts of the digital camera 10, the image pickup part 16, the CDS part 22, the GCA 24, the A / D conversion part 18, and the analog TG 20 constitute an analog signal processing system 30, and the signal processing part 26, The digital system TG 28 and the system control unit 14 form a digital signal processing system 32.

The analog signal processing system 30 is, for example, 16.36M.
It operates according to a reference clock with a clock frequency of Hz. The reference clock is generated by the analog TG 20 in response to the clock signal 34a from the clock generator 34. On the other hand, the digital signal processing system 32 operates according to the reference clock 28a having a clock frequency of 24.54 MHz. The reference clock is generated by the digital system TG 28 in response to the clock signal 34a from the clock generator 34.

Next, the phase adjustment of the sampling signal of the CDS unit 22 in this embodiment will be described. When noise occurs at the rising edge of the digital reference clock 28a, noise is periodically generated in the analog signal processing system 30 according to the ratio of the analog reference clock frequency to the digital reference clock 28a frequency. To do. In the case of this example, this ratio is an integer ratio of 2: 3.

When the analog reference clock and the digital reference clock 28a are synchronized with each other, the timing of noise generation is constant and the noise is periodically generated. Therefore, the phase (position) of the noise due to the clock of the digital system is uniquely determined, so that the phases of the sampling timing signals 20b, 20c supplied to the CDS unit 22 are periodically adjusted so as to be less susceptible to the noise. To do.

When the analog reference clock and the digital reference clock 28a are not synchronized, for example, every time the power of the digital camera 10 is turned on, the analog reference clock and the digital reference clock are The phase relationship of is different. As a result, the position of noise generated in the output 22a of the CDS unit 22 changes every time the power of the digital camera 10 is turned on. This will be described with reference to FIG.

FIG. 2 is a timing chart showing the phase relationship between the analog reference clock and the digital reference clock. FIG. 2A shows that when the rising edge of the analog reference clock (iv) and the rising edge of the digital reference clock (v) match at time t1, the CDS unit 22
The position of the noise 36 that occurs at the input 16a of (Fig. 2 (a) (i
i)).

FIG. 2B shows the input 16a of the CDS unit 22 when the rising edge of the analog reference clock (iv) and the falling edge of the digital reference clock (v) match at time t1. Shows the position of the noise 38 generated in (Fig. 2 (b) (i
i)). 2 (a) and 2 (b), the CD before applying the present invention.
The sampling positions of the S portion are indicated by arrows 42, 44, 46, 48 in FIGS. 2 (a) (iii) and 2 (b) (iii). 2 (a) (i) and FIG. 2 (b) (i) show horizontal synchronizing signals.

Comparing FIG. 2 (a) and FIG. 2 (b), it is necessary to keep the phase relationship between the analog reference clock and the digital reference clock constant at all times.
It can be seen that the position of the noise that occurs in 1 changes with respect to the horizontal synchronizing signal.

In this embodiment, in order to keep the phase relationship between the analog reference clock and the digital reference clock constant, the system controller 14 sends the reset signal 40 to the clock generator 34 as shown in FIG. , Analog
Send to TG 20, digital TG 28. Then, the phase relationship between the analog reference clock and the digital reference clock is always set to, for example, the relationship shown in FIG. 2 (a). To achieve this, if the power of the digital camera 10 is turned on at time t1, the reset signal is sent at time t1.
40 may be output from the system control unit 14 so that the rising edges of the analog reference clock and the digital reference clock pulse coincide with each other.

In the case of FIG. 2A, the noise generation pattern is repeated in the section from t1 to t2. Of the sampling positions 42, 44, 46, 48 in this section, the sampling positions may be changed for the positions 44, 46 affected by noise caused by the digital reference clock. In this embodiment, positions 44 and 46 are delayed to positions 50 and 52 so as to avoid noise. Positions 42 and 48 remain unchanged.

The sampling positions 42 and 46 are the sampling positions of the clamp circuit timing signal 20b,
The sampling positions 44 and 48 are the sampling positions of the timing signal 20c for the sample hold circuit.

Generation of sampling positions 42, 50, 52, 48,
That is, the timing signals 20b and 20c are generated in the analog system.
Performed by TG 20. Timing signal 20b of analog TG 20
The part related to the generation of 20c will be described with reference to FIG.

FIG. 3 is a block diagram of a portion of the analog TG 20 involved in generating the timing signals 20b and 20c. As shown in FIG. 3, the analog TG 20 receives the clock 34a from the clock generator 34, and also receives the delay amounts of the timing signals 20b and 20c from the system control unit 14 via the 3-wire serial control line 60. To be done. Analog system TG20
Is the reference (delayless) timing signal 20b, 20c
And timing signals 20b and 20c which are delayed by a designated delay amount, and timing signals without delay and delayed timing signals are alternately output.

In FIG. 3, each timing signal is
For 20b and 20c, the case where there is one type of delay will be explained.
When there are two or more types of delay amounts for each of the timing signals 20b and 20c, a plurality of delay circuit stages described later may be provided.

Further, in this figure, the timing signals having different sampling positions are generated by using the delay circuit. However, a plurality of pulses having different sampling positions are directly generated without using the delay circuit and these timing signals are generated. An appropriate pulse may be sequentially selected and output.

The clock 34a is the reference clock generating means 62.
Entered in. The reference clock generation means 62 uses the clock 34
An analog reference clock (FIGS. 2 (a) and (iv)) is generated from a and output to the pulse generating means A 54 and the pulse generating means B 56. The pulse generating means A 54 generates a timing signal 20b without delay from the analog system reference clock (a signal having the sampling positions 42 and 46 in FIG. 2 (a) (iii)) and outputs the signal.
It is output to the delay circuit A 58 as 54a.

The delay circuit A 58 receives the signal 54a,
A signal 58a delayed from the signal 54a is generated. Signal 58a
Is a signal corresponding to the sampling position 52 in FIGS. 2 (a) (iii). The delay circuit A 58 is specifically realized by using a delay line, a buffer, an inverter, or the like. The signal 58a is input to the terminal 66 of the selector 64. The signal 54a is input to the terminal 68 of the selector.

The selector 64 outputs the signal 58 input to the terminal 66.
A and the signal 54a input to the terminal 68 are selected according to the selection signal 70a from the control means 70 and output as the timing signal 20b.

The timing signal 20c is similarly generated by the pulse generating means B 56, the delay circuit B 74 and the selector 76.

The delay amount is input to the serial interface (serial I / F) 72 via the signal line 60 as described above. The serial signal line 60 composed of three lines includes a data line for inputting data, an enable line indicating that the data is valid, and a clock line indicating the timing of fetching the data. The data is the data corresponding to the delay amount of the timing signal 20b (for example, "001"), the timing signal 2
The data (for example, "011") corresponding to the delay amount of 0c is input in this order. The data corresponds to the amount of delay,
"1" is equivalent to the delay amount after passing one stage through the delay circuit, and "0"
"11" corresponds to the delay amount after passing through three stages of the delay circuit.
FIG. 3 shows a case in which the delay amount when passing one stage through the delay circuit is designated as data.

The data is set in the system controller 14 as an initial setting when the power of the digital camera 10 is turned on.
Sent to the analog TG 20. In this embodiment, the data is input to the analog TG 20 at the time of initial setting, but it is written in the ROM (Read Only Memory) as a part of the data required by the analog TG at the manufacturing stage. It is also possible that the analog TG directly reads the data from the ROM and does not input the data from the system control unit 14.

The serial interface 72 sends the input data to the sampling adjustment register 78. The sampling adjustment register 78 transfers the data to the timing signal 20.
It is stored in the storage area provided for each b and 20c. The data is read by the control means 70 when the power is turned on.

The control means 70 reads the data. Then, from the data, it is determined that the delay amount when delaying the timing signals 20b and 20c is one that has passed through the delay circuit. As can be seen from FIGS. 2 (a), (iii), and (iv), the timing for delaying the timing signals 20b, 20c is counted at the analog reference clock 62a for the timing signal 20b and reset at t1. This is when the even-numbered clock 62a is high level, counting from. The timing signal 20c is when the odd-numbered clock 62a is at the high level, counting from the analog reference clock 62a and counting from the reset time t1. The control means 70 has an analog system reference clock 62a for performing this counting and a counter (not shown) to which the reset signal 40 is input and which counts the analog system reference clock 62a.

The control means 70 counts the clock 62a, switches the terminals 66 and 68 of the selector 64 by the switching signal 70a for the timing signal 20b, and outputs either the signal 54a or the signal 58a to the selector 64. In addition, the switching signal 70b for the timing signal 20c causes the terminal 8 of the selector 76 to
Either 0 or 82 is switched to output either the signal 56a or the signal 74a to the selector 76.

The timing signal 20b thus generated,
Since 20c is input to the CDS unit 22, the CDS unit 22 avoids the position of noise caused by the digital reference clock,
The image signal can be sampled. As a result,
The quality of the finally obtained image is improved.

Next, another embodiment of the present invention will be described with reference to FIGS. In the following description, components having the same functions as those of the components of the embodiment of FIG. 1 will be designated by the same reference numerals, and the description thereof will be partially omitted.

In this embodiment, the image data generated by the signal processing unit 26 in the digital signal processing system is stored in SRAM (Static Random A).
This is to avoid noise that occurs when storing the image data in the ccess Memory) or reading the stored image data from the SRAM.

FIG. 4 shows a digital camera according to this embodiment.
The overall configuration of 110 is shown. As shown in FIG. 4, the image data generated by the signal processing unit 26 in the digital signal processing system 132 is sent to the compression / decompression unit 88 via the bus line 86, compressed, and then stored in the SRAM 90. It In addition, the stored image data is sent from the SRAM 90 to the compression / decompression unit 88, is decompressed, and is then decompressed via the interface unit 92.
It is sent inside or outside 110.

Noise generated by accessing the SRAM is synchronized with the horizontal synchronizing signal. This will be described with reference to FIG. FIG. 5 is a timing chart showing the timing of the horizontal synchronizing signal 94, the access period 96 to the SRAM, and the like.
As shown in FIG. 5, the timing 96 at which the image data is stored in the SRAM 90 is synchronized with the horizontal synchronizing signal 94, which is a specific period within one horizontal period, and this is repeated during one vertical period. At this time, SRA from the digital signal processing system 132
Address signals are output to M 90. Noise is generated from the digital signal processing system 132 during this timing 96 period, and the noise is added to the input signal of the CDS unit. Since noise is generated in a specific period within one horizontal period,
It appears as a vertical stripe 200 on the screen 98 of (C).

Since the timing of occurrence of the noise generated in synchronization with the horizontal synchronizing signal 94 is known in this way, during that period, the influence of the noise is affected by adjusting the phase of the sampling signal of the CDS section. It can be reduced. CDS in Figure 6
3 shows a positional relationship between a sampling signal of a part and noise. FIG. 6 is a timing chart showing timings of a sampling signal and noise.

FIG. 6A shows an input signal 216 to the CDS section. Figure
6 (b) shows the timing of the sampling signal to the CDS block. Figure 6 (c) shows the access period 212 for SRAM 90 and SRAM 9
The period 214 in which 0 is not accessed is shown.

It is assumed that noise appears in the signal level 218 of the input signal 216 to the CDS section during the access period 212 to the SRAM 90. CD during 214 without SRAM 90 access
It is assumed that no noise appears in the signal level 218 of the input signal 216 to the S section.

The sampling point 220 of the pulse that clamps the feedthrough level does not change its phase in the periods 212 and 214. The sampling points 222 and 224 of the timing signal 120c that samples and holds the signal level are
The phases of 212 and the period 214 are changed as shown in FIG. 6 (b).

A circuit for changing the phase of the timing signal 120c will be described with reference to FIG. The timing signal 120c is generated by the analog TG 120 of the analog signal processing system 130.

The analog TG 120 has a clock from the CG 34.
34a is input. The clock 34a is input to the reference clock generation means 62. The reference clock generation means 62 generates an analog reference clock (FIGS. 2 (a) (iv)) from the clock 34a and outputs it to the pulse generation means 156. Pulse generation means 1
56 generates a timing signal 120c (a signal corresponding to the sampling position 222 in FIG. 6B) without delay from the analog reference clock, and outputs it as a signal 156a to the delay circuit 174.

The delay circuit 174 receives the signal 156a,
A signal 174a delayed from the signal 156a is generated. Traffic light 174a
Is a signal corresponding to the sampling position 224 in FIG. 6 (b). The signal 174a is input to the terminal 180 of the selector 176.
The signal 156a is input to the terminal 182 of the selector.

The selector 176 outputs the signal input to the terminal 180.
174a and the signal 156a input to the terminal 182 are selected according to the control signal 84 from the digital system TG 128 of the digital signal processing system 132 and output as the timing signal 120c.
As shown in FIG. 5D, the control signal 84 is a signal that is at a low level while the SRAM 90 is being accessed and is at a high level during the other periods. Selector 176 has control signal 84
Is at a low level, terminal 182 is selected, and at a high level, terminal 180 is selected.

In this way, it is possible to generate a timing signal in which noise synchronized with the horizontal synchronizing signal is avoided, and the image quality is improved.

Next, another embodiment of the present invention will be described with reference to FIGS. In the following description, components having the same functions as those of the components of the embodiments of FIGS. 1 and 4 will be designated by the same reference numerals, and the description thereof will be partially omitted.

The embodiment shown in FIG. 4 is a method for reducing the influence of noise synchronized with the horizontal synchronizing signal.
This is a method of reducing the influence of noise synchronized with the vertical synchronization signal. The effect of noise synchronized with the vertical synchronizing signal will be described with reference to FIG. FIG. 8 shows that when noise appears in a specific period 230 within one vertical period of the vertical synchronizing signal 246, one image 2
On 31 it is shown that the influence appears as a horizontal line 232. FIG. 8 is an example in which noise does not occur in the period 228 other than the period 230.

A specific case where the horizontal stripe appears is when a moving image is reproduced. This example will be described with reference to the timing chart shown in FIG. When the digital camera is in the movie playback mode, the digital camera processes the image signal taken by the image pickup unit in the CDS unit and the image data already processed in the CDS unit in the same vertical period. The work of sending to the monitor and playing is performed in parallel. In the reproducing system for reproducing on the liquid crystal monitor, the image data stored in the SRAM is read using the vertical synchronizing signal 236 having a half cycle of the vertical synchronizing signal 234 of the CDS section. The reading period 238 is shown in FIG. 9 (c).

Therefore, in the present embodiment, the sampling phase is adjusted in the period 238 by using the control signal 240 (FIG. 9 (d)), which has the low level in the period 238 and the high level in the other periods. The control signal 240 is the digital system T as in FIG.
From G to the analog TG, within the analog TG,
Timing signals having different sampling phases may be generated using a delay circuit and a selector.

According to this embodiment, the influence of noise synchronized with the vertical synchronizing signal can be reduced.

Of course, it is possible to combine the above embodiments. That is, the sampling position can be determined so as to avoid all or some of the noise that appears in the embodiments of FIGS. 1, 4, and 8. At that time, in addition to the method of adjusting the phase of the sampling signal as described above, a memory for storing information about the sampling phase of each pixel is provided, the information stored in the memory is read, and each pixel is read according to this information. A method of adjusting the sampling phase is also possible.

The sampling phase adjustment amount (sampling position) can be determined at the design stage.
A test may be performed for each camera at the manufacturing stage, and the adjustment amount of the sampling phase may be determined for each camera.

When the noise included in the sampling signal is larger than a predetermined value, the sampling signal may not be generated. If the noise is too loud,
This is because it may be preferable not to sample.

Further, the image pickup device may be provided with a detecting means for detecting the noise position in the image pickup device and a position determining means for determining the sampling position so as to avoid the noise generation position based on the detection result.

Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the following description, components having the same functions as those of the components of the above-described embodiment will be designated by the same reference numerals, and the description thereof will be partially omitted.

In this embodiment, in the noise reduction mode intended to reduce the noise contained in the image signal, the frequency reducing means for reducing the frequency of the drive signal supplied to the image pickup device, and the noise contained in the image signal. The analog system TG 60 which is a signal generating means for generating a sampling signal for avoiding the position of (3) is included, and the sampling signal generated by the signal generating means is input to the CDS section 22. Consider the high-sensitivity shooting as the noise reduction mode. The frequency lowering means includes an input unit 310, a system control unit 314, and a clock generator 334, which will be described later.

The principle of noise suppression in this embodiment is shown in FIG.
Will be described. FIG. 10 is a diagram showing a timing at which noise is generated. FIG. 10 (a) shows an output signal 16a output by the imaging unit 16 during normal shooting. Jump noise 300 is included in the output signal 16a. Jump noise 300 is shown in
It occurs due to the rising of the clock signal 302 of the digital signal processing system shown in 10 (b). When the frequency of the reference clock of the entire digital camera is reduced to 1/2 in order to reduce the CCD drive frequency to, for example, 1/2,
As shown in (d), output signal 16a and clock signal 302
Is twice as long as that in FIGS. 10 (a) and 10 (b). However, the width of the jump noise hardly changes.

That is, when the frequency of the drive signal decreases, the pulse width of the image signal increases. On the other hand, the time width of noise included in the image signal is irrelevant to the frequency of the drive signal, and the time width of noise does not change even if the frequency of the drive signal is reduced. Therefore, the period in which the image signal is free of noise is relatively increased, which facilitates sampling of the image signal while avoiding the position of the noise.

FIG. 11 shows the timing relationship between the sampling signal and noise when the output signal 16a is sampled. FIG. 11 (a) shows a drive signal having a normal drive frequency as C
Output signal 16a when added to CD and sampling position 304
a, 304b are shown. Sampling position 304a is the sampling position by the clamp circuit timing signal 30b,
The sampling position 304b is the sampling position based on the timing signal 20c for the sample hold circuit. In this example, the noise on the feedthrough component 308a is 30
6a and the noise 306b on the signal component 308b.
Sampling position 30 to avoid noise 306a, 306b
Adjusting the phases of 4a and 304b is difficult in the case of FIG. 11 (a) in which the widths of the noises 306a and 306b are relatively larger than the widths of the feedthrough component 308a and the signal component 308b.

FIG. 11B shows an output signal 1 when a drive signal having a drive frequency of 1/2 of the normal drive frequency is applied to the CCD.
6a and sampling positions 310a and 310b are shown. The sampling position 310a is the sampling position by the clamp circuit timing signal 20b, and the sampling position 310b is the sampling position by the sample and hold circuit timing signal 20c. If the drive frequency is low, noise 306a,
It is easy to adjust the phases of the sampling positions 310a and 310b so as to avoid 306b because the widths of the noises 306a and 306b are relatively smaller than the widths of the feedthrough component 308a and the signal component 308b. .

There are various methods for supplying two kinds of high-speed and low-speed drive signals to the image pickup device. In the present embodiment, in the digital still camera of FIG. 1, a clock generator (CG) that determines the operation speed of the entire digital camera has a clock signal of a normal frequency and a slower speed than that on one signal line 34a. Frequency clock signal,
It is output to the entire camera in response to an instruction from the system control unit.

The analog signal processing system 30 and the digital signal processing system 32 receive the clock signal 34a and perform various processing. When the frequency of the clock signal 34a is normal, the analog signal processing system 30 and the digital signal processing system 32 perform processing at a normal speed. When the frequency of 34a is low, the processing is performed at low speed. Therefore, the configurations of the analog signal processing system 30 and the digital signal processing system 32 of this embodiment are the same as those of the embodiment of FIG.

However, since the system controller in the digital signal processing system 32 has the function of changing the frequency of the clock signal output from the CG to the clock generator (CG), the configuration of the embodiment shown in FIG. Is different from.

Below, a portion peculiar to this embodiment will be explained with reference to FIG. When the user of the camera performs high-sensitivity shooting, he operates a shooting mode selection unit (not shown) of the input unit 310 to set the high-sensitivity shooting mode. Input section
Reference numeral 310 is for the user to make various settings for the camera. The shooting mode selection unit is, for example, the input unit 31.
It is composed of a liquid crystal display unit provided at 0 and a key for performing a selection operation on the screen displayed on the liquid crystal display unit. The user can select high-sensitivity shooting by key operation from a plurality of shooting mode displays such as normal shooting, high-sensitivity shooting, and unlimited processing time displayed on the liquid crystal display.

When the high-sensitivity shooting is selected, the input unit 310
Outputs, to the system control unit 314, mode information indicating that high-sensitivity imaging has been selected by the data line 310a provided between the input unit 310 and the system control unit 314.

System control unit 31 to which mode information is input
In addition to the function of the system control unit 14 described above, 4 determines the content of the mode information and, in the case of normal shooting, causes the CG 334 to output a clock signal of a normal frequency for high-sensitivity shooting and unlimited processing time. In this case, the CG 334 has a function of outputting a clock signal having a frequency half the normal frequency. Specifically, the system control unit 314 outputs a low-level frequency setting signal 312 to the control line 312 for normal shooting, and a high-level frequency setting signal 312 for high-sensitivity shooting and unlimited processing time. Is output.

The timing of outputting the high level frequency setting signal 312 will be described with reference to FIG. FIG. 13A shows the vertical drive signal 316. As shown in FIG. 13B, the AE process 318a, the AF process 318b, the exposure process 318c, the high-sensitivity shooting 318d, and the moving image shooting 318e are sequentially performed for each vertical period. The horizontal axis of FIG. 13 is time. The exposure process 318c is the period determined in the AE process 318a,
High-sensitivity shooting 31
In 8d, the charge accumulated in the image sensor and image processing are performed. In the moving image shooting 318e, a moving image shooting with a reduced image resolution is performed.

In the high-sensitivity shooting mode, the system controller 314 outputs the high-level frequency setting signal 312 only during the actual high-sensitivity shooting 318d, and the other AE processing 318a and AF processing 318a.
During the period of b, the exposure process 318c, and the moving image shooting 318e, a low level frequency setting signal is output. High level frequency setting signal 31
In the period 318d in which 2 is output, the length of one vertical period is twice that of the other periods 318a, 319b, 318c, 318e. In the normal shooting mode, the low level frequency setting signal 312 is output for the entire period of the AE processing 318a, the AF processing 318b, the exposure processing 318c, the high sensitivity shooting 318d, and the moving image shooting 318e.

CG 334 to which the frequency setting signal 312 is input
Depending on the frequency setting signal 312, the normal frequency clock signal 34a and the normal 1/2 frequency clock signal 34a.
And are output to the entire camera. The reset signal 40 described above is also input to the CG 334 from the system control unit 314. The CG 334 has an oscillator 316 that produces a clock signal 316a of normal frequency. The clock signal 316a is output to the flip-flop (FF) 318 and the selector 320.

The FF 318 to which the clock signal 316a is input is
The clock signal 318a having a frequency half that of the input clock signal 316a is generated. FF 318
Is, for example, a T-type flip-flop (FF). T type FF
Is for inverting the output 318a of the T-type FF when the clock signal 316a input to the T-type FF rises.
18a can be generated. The generated clock signal 318a is output to the selector 320.

The selector 320, to which the clock signal 316a and the clock signal 318a are input, selects either the normal frequency clock signal 316a or the normal 1/2 frequency clock signal 318a in accordance with the frequency setting signal 312. Is selected, and the selected signal is output from the terminal 320c as the clock signal 334a. The clock signal 316a is input to the terminal 320b of the selector 320, and the clock signal 318a is input to the terminal 320a.

When the frequency setting signal 312 is low level,
When the clock signal 316a is selected and the frequency setting signal 312 is at high level, the low speed clock signal 318a is selected. The clock signal 334a is the digital system TG 28 shown in FIG.
Is output to the analog TG 20. As a result, in the high-sensitivity shooting mode, the entire camera operates at low speed.

According to the present embodiment, the period in which noise is not included in the image signal increases, so that it becomes easy to sample the image signal while avoiding the position of noise. Therefore, noise in the high sensitivity shooting mode can be reduced, and good image quality can be obtained even in the high sensitivity shooting.
Furthermore, by reducing the operating speed during high-sensitivity shooting,
There is also an effect that the noise of the circuit in a place other than the CCD is reduced. As a result, noise can be reduced in the entire image pickup system.

Although the frequency of the output signal of the clock generator 334 is lowered in this embodiment,
The present invention is not limited to this, and a method of slowing down only the analog system or a method of slowing down only CCD and CDS is possible. A buffer memory, for example, may be provided to coordinate the delivery of signals between the low speed part and the high speed part.

Also in the processing time unlimited mode, the same processing as in the high sensitivity photographing mode is performed. That is, when the user selects the processing time unlimited mode with the input unit 310, the system control unit 314 causes the high level frequency setting signal 3
12 is output during the shooting period 318d in FIG. In this case also, the operating speed is reduced.

The processing time unlimited mode can be selected in both normal shooting and high-sensitivity shooting. The processing time unlimited mode can be selected when the shooting time is not a concern.
According to this mode, good image quality with less noise can be obtained even in normal shooting.

[0118]

As described above, according to the present invention, it is possible to provide an image pickup apparatus and method capable of individually and appropriately adjusting sampling signals for pixels constituting an image pickup element.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a digital still camera according to an embodiment of the present invention.

FIG. 2 is a timing chart of sampling signals and the like in the embodiment of FIG.

FIG. 3 is a configuration diagram of an analog TG in the embodiment of FIG.

FIG. 4 is an overall configuration diagram of a digital still camera according to another embodiment of the present invention.

5 is a timing chart of control signals and the like in the embodiment of FIG.

FIG. 6 is a timing chart of sampling signals and the like in the embodiment of FIG.

7 is a configuration diagram of a portion related to generation of a sampling signal in the embodiment of FIG.

FIG. 8 is an explanatory diagram of the influence of noise according to another embodiment of the present invention.

9 is a timing chart of control signals and the like according to the embodiment of FIG.

FIG. 10 is an explanatory diagram showing a timing at which noise is generated according to still another embodiment of the present invention.

11 is an explanatory diagram showing a timing relationship between a sampling signal and noise in the embodiment of FIG.

12 is a block diagram showing a method of generating a reference clock in the embodiment of FIG.

FIG. 13 is an explanatory diagram showing timings for lowering the speed of the reference clock in the embodiment of FIG.

[Explanation of symbols]

10 digital camera 20 analog TG 20a, 20b, 20c, 20d Timing signal 22 CDS Department 30 Analog signal processing system 32 Digital signal processing system 36, 38 noise 42, 44, 46, 48, 50, 52 Sampling position 54 Pulse generation means A 56 pulse generation means B 58 Delay circuit A 64, 76 selector 74 Delay circuit B 78 Sampling adjustment register

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M118 AA05 AB01 BA10 FA06 GC07                       GD03 GD07                 5C024 BX01 CX06 GY01 HX02 HX13                 5C051 AA01 BA02 DA06 DB01 DB08                       DC03 DC07 DE05

Claims (20)

[Claims] 1. An imaging device comprising an image sensor and a correlated double sampling section (CDS section) which receives an image signal detected by the image sensor and samples the image signal, wherein the CDS section is a sampling unit. A sampling signal for inputting the sampling signal, the sampling signal is generated according to a first cycle of the image signal and a second cycle different from the first cycle, and is input to the CDS unit. An imaging device characterized by. 2. The imaging device according to claim 1, wherein the second cycle is a cycle of a reference clock of a digital processing system of the imaging apparatus. 3. The image pickup apparatus according to claim 1, wherein the second cycle is a cycle of a horizontal synchronization signal. 4. The image pickup apparatus according to claim 1, wherein the second cycle is a cycle of a vertical synchronization signal. 5. The imaging device according to claim 1, wherein the sampling signal is the first signal.
An image pickup apparatus, which is generated by changing a phase of a signal having a period of. 6. The image pickup device according to claim 1, wherein the sampling signal is generated so as to avoid a position of noise included in the image signal and having a second period. A characteristic imaging device. 7. The image pickup device according to claim 1, wherein the device supplies the image pickup device in a noise reduction mode for reducing noise included in the image signal. An image pickup apparatus, wherein the sampling signal is generated so that sampling is performed while avoiding a position of noise included in the image signal. 8. An image pickup method for inputting an image signal detected by an image pickup device to a CDS section to sample the image signal, the first image signal having a sampling signal for sampling the image signal. An imaging method comprising: a step of generating a cycle and a second cycle different from the first cycle; and a step of inputting the generated sampling signal to the CDS unit. 9. The image pickup method according to claim 8, wherein the second period is a period included in a reference clock of a digital processing system of an image pickup apparatus including the image pickup device and the CDS unit. Imaging method. 10. The imaging method according to claim 8, wherein
The second cycle is a cycle of the horizontal synchronizing signal,
The method is for the CD at a predetermined position on a horizontal line.
An imaging method comprising a step of changing a timing of inputting the sampling signal to the S section. 11. The imaging method according to claim 8, wherein
The second cycle is a cycle of the vertical synchronizing signal,
The method is for the CD at a predetermined position on a vertical line.
An imaging method comprising a step of changing a timing of inputting a sampling signal to the S section. 12. The imaging method according to claim 8, wherein the method includes a step of generating the sampling signal by changing a phase of a signal having the first period. A characteristic imaging method. 13. The image pickup method according to claim 8, wherein the method generates a sampling signal so as to avoid a position of noise included in the image signal and having the second period. An imaging method comprising steps. 14. An image sensor and a CDS which receives an image signal detected by the image sensor and samples the image signal.
In the imaging device including a unit, the CDS unit receives a sampling signal for sampling, the sampling signal is generated according to a pixel position, and is input to the CDS unit. 15. The imaging device according to claim 14, wherein:
The imaging device includes a storage unit having information for generating the sampling signal according to the pixel position, and the sampling signal is generated according to the information. 16. The image pickup apparatus according to claim 14, wherein the sampling signal is generated in consideration of noise included in the image signal according to the pixel position. 17. The image pickup device according to claim 14, wherein when the noise included in the image signal corresponding to the pixel position is larger than a predetermined value, the sampling signal is not generated. Image pickup device. 18. An image sensor and a CDS that receives an image signal detected by the image sensor and samples the image signal.
An image pickup device including a section, the device, in a noise reduction mode for the purpose of reducing noise included in the image signal, a frequency lowering unit that lowers a frequency of a drive signal supplied to the image pickup element, A signal generation unit for generating the sampling signal so as to avoid the position of noise included in the image signal for sampling, and the CDS unit receives the sampling signal generated by the signal generation unit. An imaging device characterized by the above. 19. The image pickup apparatus according to claim 18,
The image pickup apparatus, wherein the noise reduction mode is at least one of a high sensitivity shooting mode and a processing time unlimited mode. 20. In an imaging method of inputting an image signal detected by an imaging device to a CDS section and sampling the image signal, in a noise reduction mode intended to reduce noise contained in the image signal, Reducing the frequency of a drive signal supplied to the image sensor, generating a sampling signal for sampling the image signal, and performing sampling while avoiding the position of noise included in the image signal An image pickup method comprising: a step of generating a signal; and a step of inputting the generated sampling signal to the CDS section.