JP2003218698A - Parallel AD converter - Google Patents

Abstract

(57) [Problem] To use a chopper type amplifier as a preamplifier, if the AD conversion frequency increases, the reset time and the amplifier time are shortened. As a result, power consumption increases. SOLUTION: In a parallel type AD converter using a chopper type amplifier as each preamplifier of a preamplifier array 13, a chopper amplifier is divided into an odd-numbered amplifier and an even-numbered amplifier, and a reset operation and an amplifier are performed. In addition to the interleaving operation that alternately repeats the operation, the output signals of the preamplifier that cannot be obtained during the reset operation are interpolated by the comparators in the comparator row 14 from the output signals of two preamplifiers adjacent to the preamplifier. The obtained interpolation signal is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel AD converter, and more particularly to a parallel AD converter using a chopper type amplifier as a preamplifier.

[0002]

2. Description of the Related Art FIG. 8 shows a basic structure of a parallel AD converter. The parallel AD converter is basically composed of a sample hold (S / H) circuit 101, a reference voltage (reference voltage) generation circuit 102, a comparator array 103, and an encode circuit 104. The sample hold circuit 101 samples the input analog signal and holds the sampled value for a certain period. The reference voltage generation circuit 102 has a configuration in which resistors R are connected in series, and generates a plurality of reference voltages having different voltage values at each connection node of the resistors R.

In the comparator array 103, the number of comparators arranged is the number corresponding to the resolution, and the sample hold circuit 101 is provided.
Then, the hold voltage according to (4) and the plurality of reference voltages generated by the reference voltage generation circuit 102 are simultaneously compared. At this time, among the comparators in the comparator array 103, the comparators whose reference voltage is the hold voltage or more are all set to the logic “0” level with the comparator to which the reference voltage closest to the hold voltage is given as a boundary. All comparators that output and the reference voltage is lower than the hold voltage output a logic "1" level.

Although not shown, the comparator array 103
A logic processing circuit is usually provided in the subsequent stage. This logic processing circuit performs a logic processing to obtain the exclusive OR of the outputs of the adjacent comparators of the comparator array 103. Encoding circuit 1
Reference numeral 04 encodes the logic processing result in the logic processing circuit and performs digital conversion to obtain a digital signal.

Here, in each of the comparators in the comparator array 103, usually, a sufficient gain cannot be obtained by one amplification stage. Therefore, two amplification stages are provided as shown in FIG.
In many cases, a configuration in which a latch circuit is arranged at the final stage is adopted.
Therefore, for example, in the case of 6 bits, 63 1st preamplifiers, 2nd preamplifiers and latch circuits are required for each.

In the case of the basic parallel AD converter described above, since the comparator array is composed of comparators having only the resolution of the comparator array 103, the circuit scale exponentially increases as the resolution increases. As a result, the power consumption increases and the chip size also increases.

On the other hand, by using the interpolation technique, an interpolating parallel AD converter capable of preventing an increase in circuit scale and operating at high speed with low power consumption is reported in the following document. Reference: "A Dual-Mode 700Msps 6bit 200Msps 7bit ADC
in a 0.25um Digital CMOS '' (IEEE Journal of Solid-St
ate Circuits, Vol.35, No12, Dec. 2000)

FIG. 9 shows the configuration of the interpolation parallel AD converter. This interpolation parallel AD converter includes a sample hold circuit 111, a reference voltage generation circuit 112, a first preamplifier row 113, a second preamplifier row 114, and a latch circuit row 1.
15 and an encoding circuit 116. The basic operation for AD conversion is the same as that of the basic parallel AD converter described above.

However, in this interpolation parallel type AD converter, 1
While the number of preamplifiers in the st preamplifier array 113 is thinned to 1/2, an interpolation signal is generated from two adjacent preamplifier outputs of the 1st preamplifier array 113 in the 2nd preamplifier array 114 so as to obtain a comparator output for resolution. There is. In this way, the number of preamplifiers in the 1st preamplifier array 113 can be reduced to ½ by generating the comparator outputs decimated by the 2nd preamplifier array 114 by interpolation, thus reducing the circuit scale and power consumption. Will be an effective approach to.

In the 1st preamplifier array 113, when a transistor having a small size is used to form a circuit, the characteristics of the transistor are likely to vary, and an offset occurs due to the variation, so that the offset is canceled. A chopper type amplifier will be used as each preamplifier.

[0011]

However, in the interpolation parallel type AD converter according to the above-mentioned conventional example, when the AD conversion frequency increases, that is, when the cycle of the clock serving as the reference of the AD conversion operation becomes short, the 1st preamplifier string is reduced. There is a problem that the reset time and the amplifier time of the chopper type amplifier in 113 are shortened.

Here, the fact that the reset time is short means that offset cancellation, which is one of the characteristics of the chopper system, cannot be sufficiently performed. This is because in reset mode, the input and output potentials must be quickly set to the same potential to cancel the offset, but when the clock cycle becomes short, the next amplifier operation starts before the reset operation is completely completed. Because it will be.

From this, in order to realize offset cancellation with desired accuracy in a short reset time, 1 s is required.
It is required to flow a bias current more than necessary to each amplifier of the t preamplifier string 113. Similarly, since the shortage of the amplifier time is related to the minimum voltage that can be compared and determined, it is necessary to increase the bias current of each amplifier in order to ensure the desired accuracy of comparison and determination. As a result, the power consumption of the entire AD converter increases.

The present invention has been made in view of the above problems, and an object of the present invention is to perform parallel AD conversion using a chopper system amplifier without increasing power consumption. To provide a container.

[0015]

Parallel AD according to the present invention
The converter includes a reference voltage generating unit that generates a plurality of reference voltages and a differential output voltage that amplifies a difference between a corresponding reference voltage among the plurality of reference voltages generated by the reference voltage generating circuit and an input signal. Comparing the preamplifier array in which multiple preamplifiers to be converted into are arranged, and the odd-numbered preamplifiers and the even-numbered preamplifiers alternately perform the reset operation and the amplifier operation and the preamplifier output signal. A plurality of devices are arranged corresponding to each preamplifier in the preamplifier row, and the comparator corresponding to the preamplifier that is operating the amplifier outputs the determination result based on the output signal of the corresponding one preamplifier, and performs the reset operation. In the comparator corresponding to the preamplifier, the interpolation signal obtained by interpolating the output signals of the two preamplifiers adjacent to the corresponding preamplifier. A comparator array for outputting a determination result based on, has a configuration that includes a logical processing circuit for obtaining a digital conversion output a determination result of each comparator of the comparator array with logic processing.

In the parallel AD converter having the above-mentioned configuration, the odd-numbered preamplifiers and the even-numbered preamplifiers in the preamplifier row perform an interleave operation, so that the reset time and the cycle time of the AD conversion clock, which have conventionally been 1/2, The amplifier time can be set to double, that is, the time corresponding to the cycle of the AD conversion clock. An output signal cannot be obtained from the preamplifier performing the reset operation by this interleave operation, but each comparator in the comparator row is adjacent to the preamplifier performing the reset operation and interpolates the output signals of the two preamplifiers performing the amplifier operation. Then, the determination process is performed using the interpolation signal.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a parallel AD converter according to an embodiment of the present invention, and shows a case of 3 bits as an example. As is apparent from FIG. 1, the parallel AD converter according to the present embodiment has the input terminal 1
1, the reference voltage generating circuit 12, the preamplifier array 13, the comparator array 14, and the encoding circuit 15, and the interleaving operation in the preamplifier array 13 + the interpolation operation in the comparator array 14 is a feature of the present invention.

In the interpolating parallel AD converter having the above structure, the analog signal VIN to be AD-converted is input to the input terminal 11. The reference voltage generating circuit 12 has a configuration in which a plurality of resistors R for the resolution are connected in series between the upper reference voltage VRT and the lower reference voltage VRB, and a plurality of resistors having different voltage values are provided. The reference voltage (reference voltage) is generated at each connection node of the resistor R.

The preamplifier array 13 is composed of nine preamplifiers because it has a structure corresponding to the number of resolutions, in this example, 3 bits. Preamp row 1
Each of the preamplifiers 3 receives the analog signal VIN supplied via the input terminal 11 as a comparison input, and uses the corresponding reference voltage among the plurality of reference voltages generated at each connection node of the reference voltage generation circuit 12 as a reference. Input it. As these preamplifiers, chopper type amplifiers (hereinafter,
Chopper amplifier) is used. A specific circuit example of this chopper amplifier will be described in detail later.

In the preamplifier array 13, the nine chopper amplifiers are odd-numbered (odd) and even-numbered (e).
ven) amplifier. And, the two systems of chopper amplifier are AD conversion clock EX
TCK (This clock frequency becomes the ad conversion frequency)
An interleave operation in which a reset operation and an amplifier operation are alternately repeated in synchronism with two systems of clocks CKodd and CKeven having a frequency of ½ of the above and opposite phases to each other (see the timing chart of FIG. 2). ).

Similar to the preamplifier array 13, the comparator array 14 is composed of a number (9 in this example) of comparators corresponding to the resolution. As these comparators, comparators with a latch function are used. This comparator with a latch function outputs the determination result based on the output signal of the corresponding preamplifier or the adjacent preamplifier according to the operation mode of the corresponding preamplifier (chopper amplifier) of the preamplifier row 13 in the preceding stage. The output signals of the two preamplifiers are interpolated, and the determination result is output based on the interpolated signals.

The reason why each of the comparators in the comparator array 14 is provided with an interpolation function is as follows. That is, by interleaving each preamplifier in the preamplifier row 13, only these preamplifiers contribute to AD conversion when the odd-numbered preamplifiers are in the amplifier mode, and conversely, when these even-numbered preamplifiers are in the amplifier mode. Only the preamplifier contributes to AD conversion. This effectively halves the number of preamplifiers required for resolution, making it impossible to obtain digital data with the required resolution. Therefore, the interpolation operation in the comparator array 14 is combined to generate digital data having a required resolution.

The combined operation of the interleave operation and the interpolation operation will be specifically described with reference to the operation explanatory diagram of FIG.

In the preamplifier array 13, first, consider the case where the even-numbered chopper amplifiers are in the amplifier mode and the odd-numbered chopper amplifiers are in the reset mode (FIG. 3 (A)). In this case, since the output signal of the odd-numbered chopper amplifier cannot be used,
The odd-numbered comparators interpolate the output signals of the two even-numbered chopper amplifiers adjacent to the corresponding odd-numbered chopper amplifiers, and output the determination result based on the interpolated signals.
At this time, the even-numbered comparator outputs the determination result based on the output signal of the corresponding even-numbered chopper amplifier.

Similarly, in the preamplifier array 13, consider a case where the odd-numbered chopper amplifiers are in the amplifier mode and the even-numbered chopper amplifiers are in the reset mode (FIG. 3 (B)). In this case, since the output signal of the even-numbered chopper amplifier cannot be used,
The even-numbered comparators interpolate the output signals of the two odd-numbered chopper amplifiers adjacent to the corresponding even-numbered chopper amplifiers, and output the determination result based on the interpolated signals.
At this time, the even-numbered comparator outputs the determination result based on the output signal of the corresponding even-numbered chopper amplifier.

The encoding circuit 15 is a logic processing circuit that logically processes the determination result of each comparator of the comparator array 14, and encodes the determination result and digitally converts it to a required resolution, in this example, 3 bits. To generate digital data.

As described above, in the parallel type AD converter using the chopper type amplifier as each preamplifier in the preamplifier array 13, the chopper amplifier is divided into two systems, an odd numbered amplifier and an even numbered amplifier, By performing the interleave operation in which the reset operation and the amplifier operation are alternately repeated, the reset time and the amplifier time are twice as long as the conventional one, that is, as is clear from the timing chart of FIG. 2, the AD conversion clock (clock of the AD conversion frequency) EXTCK. The time is equivalent to the cycle.

As described above, since the reset time can be set long, the offset cancel function, which is one of the features of the chopper amplifier, is fully exerted even if an excessive bias current is not supplied to each preamplifier in the preamplifier row 13. You can do it. Similarly, since the amplifier time can be set long, a desired comparison / determination accuracy can be ensured without increasing the bias current of each preamplifier in the preamplifier array 13.
As a result, AD conversion using a chopper amplifier is possible without increasing power consumption.

Moreover, since the reset time and the amplifier time can be set to a time corresponding to the cycle of the ad conversion clock EXTCK, the frequency (A
Even if the D conversion frequency) is increased, the reset time and the amplifier time can be secured sufficiently longer than those in the conventional technique, so that a faster conversion operation can be realized without increasing the power consumption.

[Example Circuit of Chopper Amplifier] FIG. 4 is a circuit diagram showing an example of a specific circuit configuration of a chopper amplifier used as each preamplifier in the preamplifier array 13.
As is clear from FIG. 4, the chopper amplifier according to the present circuit example includes the input circuit 131, the differential circuit 132, and the load circuit 13.
3 and a common mode feedback circuit 134, which is a fully differential type configuration.

The input circuit 131 includes a switch S to which analog voltages VINP and VINN to be compared are applied to one end thereof.
W11p and SW11n, and switches SW12p and SW12n to which the reference voltages VRP and VRN are given to one ends, respectively.
A capacitor C11p having one end connected to the other end of each of the switches SW11p and SW12p and switches SW11n and S
A capacitor C11 having one end connected to the other end of W12n
n and switches SW13p and SW connected between the other ends of the capacitors C11p and C11n and a predetermined common potential.
13n.

The differential circuit 132 includes a differential pair MOS transistor Q11 having sources connected in common and performing a differential operation.
Q12, current sources I11 and I12 connected between the drains of these MOS transistors Q11 and Q12 and the power supply VDD, and MOS transistors Q11 and Q12.
And a current source MOS transistor Q13 connected between the source common connection point 12 and the ground GND,
The gates of the differential pair MOS transistors Q11 and Q12 are connected to the other ends of the capacitors C11p and C11n, respectively.

The load circuit 133 includes cascode-connected MOS transistors Q14, Q16, Q18 between one output end (drain of the MOS transistor Q11) of the differential circuit 132 and the ground GND, and the other output end (M).
OS transistor Q12 drain) and ground GND
MOS transistor Q1 connected in cascode between
5, Q17, Q19 and MOS transistors Q18, Q
Capacitors C12 and C13 connected between each gate of 19 and ground GND, drains of MOS transistors Q16 and Q17, and MOS transistor Q, respectively.
The switches SW14 and SW15 are respectively connected between the gates of Q18 and Q19.

In this load circuit 133, a predetermined bias voltage Vgn is applied to the gates of MOS transistors Q14 and Q15, and similarly, MOS transistor Q1.
A predetermined bias voltage Vgp is applied to the gates of 6 and Q17. The switches SW14 and SW15 switch between a diode load and a cascode load, which will be described later, according to a control clock CLK given from the outside. The capacitors C12 and C13 hold the voltage when the diode is loaded. Then, the drain outputs of the MOS transistors Q14 and Q15 are supplied to the comparator row 14 of the next stage.

As is apparent from the above description, the differential circuit 132 having the above-described configuration and the load circuit 133 having the above-described configuration.
The main body of the amplifier is composed of a folded cascode amplifier of NMOS transistors.
The common mode feedback circuit 134 is a means for determining the output operating point in the amplifier mode of the amplifier body, as will be described later.

In the chopper amplifier having the above-mentioned configuration, in the reset mode, the switches SW11p and SW11n are turned on, so that the analog voltage VINP to be compared,
VINN is supplied to the capacitors C11p and C11n,
Further, since the switches SW13p and SW13n are turned on, the input end of the amplifier body, that is, the MOS transistor Q
A common potential is applied to the bases of 11 and Q12. At this time, the switches SW14 and SW15 of the load circuit 133
Is also on. As a result, the MOS transistor Q
Since the gates and drains of 18 and Q19 are short-circuited, the MOS transistors Q18 and Q19 are diode-connected and serve as a diode load.

In the amplifier mode, the switches SW11p, SW11n, SW13p, and S that have been in the ON state until then.
W13n, SW14, SW15 are all off,
Instead, the switches SW12p and SW12n are turned on so that the reference voltages VRP and VRN are changed to the capacitor C11.
p, C11n. As a result, the difference between the analog voltages VINP and VINN and the reference voltages VRP and VRN, that is, the variation is amplified by the amplifier main body and output to the comparator row 14 at the next stage.

Here, since the amplifier main body has a structure in which the folded cascode amplifier is adopted, a sufficient gain can be obtained even in one stage, so that it is not necessary to provide an additional amplification stage, and the number of circuit parts can be reduced. It is very convenient for me.

In this chopper amplifier, the determination of the operating point of the amplifier body differs between the reset mode and the amplifier mode. 4, in the reset mode, as described above, since the load transistors (MOS transistors Q18 and Q19) of the amplifier main body are diode loads, the output potential is determined by the size of the load transistor and the flowing current, and is relatively higher than the ground level. Low potential, specifically the gates of MOS transistors Q18 and Q19
It becomes the inter-source potential Vgs.

On the other hand, in the amplifier mode, it is necessary to properly set the DC operating point so as to obtain a high gain. Usually D
Generally, the C operating point is set to half the power supply voltage VDD to increase the output range. In this circuit example, the common mode field back circuit 134 performs feedback so that the operating point in the amplifier mode becomes the predetermined common potential VCMN.

Here, a concrete circuit example of the common mode fieldback circuit 134 and its circuit operation will be described.

Common Mode Fieldback Circuit 134
FIG. 5 shows a specific circuit example of the above. As is clear from the figure, the common mode field back circuit 134 includes a common terminal 21, input terminals 22 and 23, a control terminal 24, a switched capacitor circuit 25, and a reference bias circuit 26.
It is configured to have. The common voltage VCMN is externally applied to the common terminal 21. Input terminal 22,
23 is an output terminal of the amplifier body, that is, the load circuit 13 of FIG.
3 are connected to the drains of the MOS transistors Q14 and Q15. The control terminal 24 is the differential circuit 1 of FIG.
It is connected to the gate of the NMOS transistor Q13 in 32.

The switched capacitor circuit 25 includes a switch SW2 whose one end is commonly connected to the common terminal 21.
1, SW22, switches SW23 and SW24 each having one end separately connected to the input terminals 22 and 23, and a switch S.
A capacitor C21 having one end commonly connected to the other ends of W21 and SW23, a capacitor C22 having one end commonly connected to the other ends of the switches SW22 and SW24, and one end commonly connected to the control terminal 24. Switch SW2
5, SW26, switches SW27 and SW28 respectively connected between the other ends of the capacitors C21 and C22 and the other end of the switch SW25, and capacitors C21 and C2.
The switch SW29 and the switch SW30 are connected between the other end of the switch 2 and the other end of the switch SW26.

The reference bias circuit 26 has a current source I21 and a diode-connected NMOS transistor Q21 connected in series between the power supply VDD and the ground GND, and the reference bias potential point O is a switch of the switched capacitor circuit 25. It is connected to the other ends of SW25, SW27, and SW28.

The common mode field back circuit 134 having the above-described configuration operates at the timings of the odd-numbered chopper amplifier and the even-numbered chopper amplifier.
Then, in the switched capacitor circuit 25, the switches SW21, SW22, SW25, SW27, SW2
8 is in the ON state in the reset mode and is in the OFF state in the amplifier mode. Conversely, the switches SW23, SW24,
SW26, SW29, and SW30 are turned off in the reset mode and turned on in the amplifier mode.

Next, a specific circuit operation of the common mode field back circuit 134 will be described. First,
In the reset mode, the capacitors C21 and C22 are precharged. That is, the switch SW
When 21, SW22, SW25, SW27, and SW28 are turned on, the common voltage V with respect to the reference bias potential (potential at the point O) given by the reference bias circuit 26.
The capacitors C21 and C22 are charged with CMN.

At this time, the gate of the NMOS transistor Q13 (see FIG. 4) which is the current source of the differential circuit 132 and the gate / drain of the NMOS transistor Q21 of the reference bias circuit 26 are connected via the switch SW25, and both of them are connected. Since the MOS transistors Q13 and Q21 form a current mirror circuit, the current flowing through the reference bias circuit 26 directly flows through the differential circuit 132.

On the other hand, in the amplifier mode, the switch SW
21, SW22, SW25, SW27 and SW28 are turned off, and switches SW23, SW24 and S are used instead.
W26, SW29, and SW30 are turned on. As a result, the capacitors C21 and C2 are connected between the input terminals 22 and 23.
2 is a switch SW23, SW24 and a switch SW2
9 and SW30 are connected in series, and the common connection point of the capacitors C21 and C22 is connected to the control terminal 24 via the switch SW26.

Due to this connection, the common mode fieldback circuit 134 is connected between the output terminals of the amplifier body and is fed back to the gate of the NMOS transistor Q13 of the differential circuit 132 by feeding back the intermediate potential between the two output levels. A local loop is formed that determines the operating point. That is, by using the common mode fieldback circuit 134, the output operating point of the amplifier body can be set to the potential of the common voltage VCMN. As a result, in the amplifier mode, the DC operating point can be set so that the gain is high.

In the amplifier circuit, it is unavoidable that an offset occurs due to variations in the characteristics of the MOS transistors, and it is necessary to cancel this offset in order to realize an accurate amplifier operation. . To cancel this offset,
In the reset mode, the input / output of the amplifier is short-circuited by a switch, the bias is automatically biased to the highest gain position, and the input signal is sampled with respect to the potential.

However, in the chopper amplifier according to the present circuit example, as is clear from FIG.
After 1p and C11n, switch SW13
p, SW13n are provided, and these switches SW13p, S
The input terminal (gates of the MOS transistors Q11 and Q12) of the amplifier body is connected to the common potential via W13n. If such a form is adopted, the offset canceling function at the input end of the amplifier body, which is originally provided, is lost.

Therefore, the chopper amplifier according to the present circuit example has a configuration in which the offset cancel operation is realized by compressing the offset amount at the output end of the amplifier body. In this offset compression, the input conversion offset is reduced by utilizing the gain difference between the reset mode and the amplifier mode. That is, in the reset mode, as described above, the switches SW14 and SW15 in the load circuit 133 are turned on to turn on the MOS.
Transistors Q18 and Q19 are diode connected,
The gain is relatively low due to the diode load.

Assuming that the gain in the reset mode is Gr and the differential pair (MOS transistors Q11 and Q12) has an offset of Vos, the output voltage Vout.
r is Voutr = Vos * Gr.

On the other hand, in the amplifier mode, the load circuit 13
3, the switches SW14 and SW15 are both turned off, and the MOS transistors Q14, Q16 and Q1
8, MOS transistors Q15, Q17, Q19 are respectively cascode-connected, and the load of the amplifier main body becomes a cascode load, so that the gain is significantly increased. Since the capacitors C12 and C13 hold the voltage Voutr in the reset mode, that is, when the diode is loaded, D
The C-like operating point does not change.

When the input conversion offset Veq is calculated with the gain in the amplifier mode being Ga, Veq = Vos * Gr / Ga. Therefore, the effect of offset compression can be increased by setting a large gain difference between the gain Gr in the reset mode and the gain Ga in the amplifier mode.

[First Circuit Example of Comparator] FIG. 6 is a circuit diagram showing a first circuit example of the comparators forming the comparator array 14. In this circuit example, the case where the output signals of the (n + 1) th preamplifier, the nth preamplifier, and the (n-1) th preamplifier are input is shown as an example.

The comparator according to the present circuit example has a circuit configuration with a latch function, and in order to realize the interpolation function,
n + 1th preamplifier, nth preamplifier, n-1
Input each output signal of the th preamplifier 3
An input stage composed of a plurality of differential circuits 31, 32, 33, and a load circuit 34 serving as a load of these differential circuits 31, 32, 33.
It is configured to have and.

The differential circuit 31 is composed of differential pair transistors Q31 and Q32 whose sources are commonly connected, and n + is provided between the gates of these differential pair transistors Q31 and Q32.
The output signal of the first preamplifier is input. The differential circuit 32 includes differential pair transistors Q33 and Q34 whose sources are commonly connected.
The output signal of the nth preamplifier is input between the gates of 33 and Q34. The differential circuit 33 includes differential pair transistors Q35 and Q36 whose sources are commonly connected,
The output signal of the (n-1) th preamplifier is input between the gates of the differential pair transistors Q35 and Q36.

In these differential circuits 31, 32, 33, between the source common connection point and the ground GND,
A common current source I31 is connected to each circuit. Also,
One of the differential pair transistors (Q31, Q33, Q35)
Drains are commonly connected between each circuit, and the other (Q3
2, Q34, Q36) are commonly connected between the respective circuits.

The load circuit 34 includes a PMOS transistor Q.
37 and an NMOS transistor Q38, an inverter 341, and PMOS transistors Q39 and NM.
The inverter 342 including the OS transistor Q40 is configured by a positive feedback circuit in which the input terminal and the output terminal are connected to each other and the output terminal and the input terminal are connected to each other.
PMOS transistors Q41 and Q42 are connected in parallel to the PMOS transistors Q37 and Q39, respectively. The clock CKLAT is applied to the gates of the PMOS transistors Q41 and Q42.

Further, between the three differential circuits 31, 32 and 33 and the load circuit 34 thereof, specifically, the common drain connection point of the MOS transistors Q31, Q33 and Q35 and the MOS transistors Q32, Q34 and Q36. Between the drain common connection point and the sources of the MOS transistors Q38 and Q40, the NMOS transistors Q43 and Q4 are connected.
4 are connected to each other. A clock CKLAT is applied to each gate of these NMOS transistors Q43 and Q44.
Is given.

The comparator with a latch function having the above structure operates in two phases of the reset mode and the latch mode in synchronization with the clock CKLAT. First, the clock CKLAT
In the reset mode in which is low level, the NMOS transistors Q43 and Q44 are turned off, so that the three differential circuits 31, 32 and 33 and the load circuit 34 are disconnected. At this time, the PMOS transistor Q of the load circuit 34
Since 41 and Q42 are turned on, the load circuit 34 including the positive feedback circuit is forcibly reset to the power supply VDD.

On the other hand, in the latch mode in which the clock CKLAT is at the high level, the NMOS transistors Q43, Q
When 44 is turned on, the three differential circuits 31, 3
Since the load circuit 34 is connected to 2, 33, these differential circuits 31, 32, 33 become active,
A current corresponding to the input voltage (differential output voltage of each preamplifier in the preamplifier array 14) is generated. Then, the load circuit 34
Operates by sensing the difference in current according to the input voltage, performs positive feedback on the differential output voltage of the preamplifier, converts it into digital data, and outputs it through the output terminals 35 and 36.

Here, the three differential circuits 31, 32, 33
In (1), the differential circuit to be activated is determined by sensing the difference between the output operating point of the odd-numbered preamplifier and the output operating point of the even-numbered preamplifier in the preamplifier row 13 in the preceding stage. The mechanism is as follows. That is, since the three differential circuits 31, 32, and 33 have the current source I31 in common, the bias current flows only in the differential circuit having a high input signal level.

As described above, since the output operation points of the odd-numbered preamplifiers and the even-numbered preamplifiers differ depending on the operation mode, the three differential circuits 31, 32, and 33 are utilized by utilizing the difference of the operation points. , The output signal from the corresponding preamplifier (odd-numbered or even-numbered; nth in this example), or from the two preamplifiers (n + 1th and n-1th in this example) adjacent to the corresponding preamplifier It is automatically determined whether to take two output signals and perform interpolation processing.

Here, as is apparent from the circuit description of FIG. 4 described above, each odd-numbered / even-numbered preamplifier is locally fed back by the common mode feedback circuit 134 which determines the output operating point. Therefore, the output operating point does not deviate between the two adjacent preamplifiers. Therefore, the comparator with a latch function according to the present circuit example can reliably perform the interpolation processing based on the output signals of the two preamplifiers.

[Second Circuit Example of Comparator] FIG. 7 is a circuit diagram showing a second circuit example of the comparators forming the comparator array 14. In the figure, the same parts as those in FIG. It is attached. Also in this circuit example, the (n + 1) th preamplifier,
The case where the output signals of the n-th preamplifier and the (n-1) th preamplifier are input is shown as an example.

Like the comparator according to the first circuit example, the comparator according to the present circuit example has a circuit configuration with a latch function having three differential circuits 31, 32, 33 and its load circuit 34. ing. The configuration is different from the comparator according to the first circuit example in that the current source I31 is connected to the current sources I31A and I31.
31B and a differential pair transistor Q which forms a differential circuit 32 corresponding to the n-th preamplifier
33 and Q34 are each a half size transistor Q
33A and Q33B and transistors Q34A and Q34B are divided into two, and the current sources I31A and I31B are separately arranged.

Specifically, the sources of the differential pair transistors Q31 and Q32 of the differential circuit 31 and the transistors Q33A and Q34A of the differential circuit 32 'are commonly connected, and the common source connection point and the ground GND are connected. Current source between
31A is connected to form a first input stage, and transistors Q33B and Q3 of the differential circuit 32 'are formed.
4B and differential pair transistors Q35 and Q3 of the differential circuit 33
The sources are connected in common and the current source I31B is connected between the common source connection point and the ground GND to form the second input stage.

In the differential circuit 32 ', the gates of the transistors Q33A and Q33B are commonly connected to serve as one input terminal, and the transistors Q34A and Q3 are provided.
Gates of 4B are commonly connected to serve as the other input terminal. That is, the differential pair transistors Q33A and Q34A whose transistor size in the first input stage is half and the second pair
In the differential pair transistors Q33B and Q34B whose input stage transistor size is half, Q33A
And one Q33B, and the other Q34A and the other Q34B are connected in parallel.

The comparator with a latch function according to this circuit example is
The operation is basically the same as that of the comparator with a latch function according to the first circuit example, and the description of the operation is duplicated and therefore omitted. In FIG. 7, "1" attached to the transistors Q33A, Q33B, Q34A, Q34B and the transistors Q31, Q32, Q35, Q.
"2" attached to 36 represents the size ratio of the transistor.

However, in the case of the comparator with a latch function according to this circuit example, the current source I31 is divided into two, and the transistor size of one of the three differential circuits 32 'is set to two.
Since the current sources I31A and I31B are divided into two and arranged separately, for some reason, two preamplifiers (n + 1th and n-1th in this example) adjacent to the corresponding preamplifier are used. ), Even if the output operating point is deviated, the differential circuits 31, 33
Are operated by separate current sources I31A and I31B, it is possible to perform an interpolation operation.

[0074]

As described above, according to the present invention,
Each preamplifier in the preamplifier row is interleaved so that the reset operation and the amplifier operation are alternately repeated, and a signal that cannot be obtained by the preamplifier during the reset operation is obtained by interpolating the output signals of the two preamplifiers adjacent to the preamplifier. By doing so, the reset time of the preamplifier and the amplifier time can be set longer, so that AD conversion using a chopper amplifier can be performed without increasing power consumption. Moreover, even if the conversion frequency is increased, the reset time and the amplifier time can be sufficiently secured, so that the conversion operation can be performed at higher speed without increasing the power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration example of a parallel AD converter according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the circuit operation of the parallel AD converter according to the embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of a combined operation of an interleave operation and an interpolation operation.

FIG. 4 is a circuit diagram showing an example of a specific circuit configuration of a chopper amplifier used as each preamplifier in a preamplifier array.

FIG. 5 is a circuit diagram showing a specific circuit example of a common mode fieldback circuit.

FIG. 6 is a circuit diagram showing a first circuit example of a comparator with a latch function that constitutes a comparator array.

FIG. 7 is a circuit diagram showing a second circuit example of a comparator with a latch function that constitutes a comparator array.

FIG. 8 is a block diagram showing a basic configuration of a parallel AD converter.

FIG. 9 is a block diagram showing a configuration of an interpolation parallel AD converter according to a conventional example.

[Explanation of symbols]

12 ... Reference voltage generating circuit, 13 ... Preamplifier array, 14 ...
Comparator row, 15 ... Decoding circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5J022 AA06 BA03 BA05 BA06 CA08                       CA10 CB02 CB04 CD03 CE01                       CF01 CF02 CF04                 5J039 DD01 KK05 KK16 KK18 KK28                       MM03 MM04 MM08

Claims (6)

[Claims] 1. A reference voltage generating means for generating a plurality of reference voltages, and a differential amplifier configured to amplify a difference between a corresponding reference voltage among the plurality of reference voltages generated by the reference voltage generating circuit and an input signal. A plurality of preamplifiers for converting to an output voltage are arranged, and the preamplifier row in which the odd-numbered preamplifiers and the even-numbered preamplifiers perform an interleave operation in which the reset operation and the amplifier operation are alternately repeated, and the magnitude relationship between the output signals of the preamplifiers. A plurality of comparators for judgment are arranged corresponding to each preamplifier in the preamplifier row, and the comparator corresponding to the preamplifier in operation of the amplifier outputs the judgment result based on the output signal of the corresponding one preamplifier, The comparator corresponding to the preamplifier in reset operation interpolates the output signals of the two preamplifiers adjacent to the corresponding preamplifier. It is characterized by comprising a comparator array for outputting a determination result based on the obtained interpolation signal, and a logic processing circuit for logically processing the determination result of each comparator of the comparator array to obtain a digital conversion output. Parallel AD converter. 2. Each of the preamplifiers in the preamplifier array is composed of a chopper type amplifier, and includes a load transistor, switch means for selectively diode-connecting the load transistor in synchronization with the control clock, and the load. The parallel type AD converter according to claim 1, further comprising a capacitor that holds a voltage of the load transistor when the transistor is diode-connected. 3. A means for setting each output preamplifier in the preamplifier array to set an output operating point to a potential different from that during the reset operation by controlling a bias current of the preamplifier based on the differential output voltage during the amplifier operation. The parallel type AD converter according to claim 2, further comprising: 4. Each of the comparators in the comparator array fetches an output signal of the one preamplifier and performs a determination process based on an operating point of the output signal of the preamplifier, or
2. The parallel AD converter according to claim 1, further comprising means for automatically determining whether or not to perform determination processing by taking in output signals of one preamplifier. 5. Each of the comparators in the comparator array includes an input stage having three differential pair transistors whose sources are commonly connected and one current source connected to the common source connection point, and a reset mode. 5. The positive feedback circuit according to claim 4, further comprising: a positive feedback circuit for resetting an output potential in the latch mode and applying positive feedback to the differential output voltage supplied through the input stage in a latch mode to convert the differential output voltage into digital data. Type AD converter. 6. Each of the comparators in the comparator array has a first pair of two differential pair transistors having sources commonly connected and a current source connected to a common connection point of the sources.
Input stage, two differential pair transistors whose sources are commonly connected, and 1 connected to a common connection point of their sources.
A second input stage having two current sources, and a positive feedback circuit for resetting an output potential in a reset mode and for positively feeding the differential output voltage supplied through the input stage in a latch mode to convert it into digital data. And the size of one differential pair transistor in the first and second input stages is half the size of the other differential pair transistor, and the size of the first input stage is half the differential 5. A parallel pair according to claim 4, wherein one pair and one pair and the other pair and the other pair of the paired transistor and the differential paired transistor whose size of the second input stage is half are respectively connected in parallel. Type AD converter.