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JP2003218481A - Printed circuit boards and printed circuit boards for mounting multi-pin connectors - Google Patents

Printed circuit boards and printed circuit boards for mounting multi-pin connectors

Info

Publication number
JP2003218481A
JP2003218481A JP2002016001A JP2002016001A JP2003218481A JP 2003218481 A JP2003218481 A JP 2003218481A JP 2002016001 A JP2002016001 A JP 2002016001A JP 2002016001 A JP2002016001 A JP 2002016001A JP 2003218481 A JP2003218481 A JP 2003218481A
Authority
JP
Japan
Prior art keywords
line width
pin connector
printed circuit
signal line
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002016001A
Other languages
Japanese (ja)
Inventor
Yuichiro Murata
雄一郎 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002016001A priority Critical patent/JP2003218481A/en
Publication of JP2003218481A publication Critical patent/JP2003218481A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a multi-pin connector mounting printed board which suppresses signal reflections and minimums a distortion of a signal waveform. <P>SOLUTION: A signal line path near a region 11 on which a multi-pin connector is mounted is set as a part 6a of a narrow line path width and a signal line path of the other region 12 is set as a part 6b of a wide line path width. A dielectric 13 having a high dielectric constant is disposed in the region 11 on which the multi-pin connector is mounted, and a dielectric 14 having a low dielectric constant is disposed in the other region 12. An output reduction caused by a conductor loss is lessened and a change in characteristic impedance in a change part of the line path widths of the part 6a of the narrow line path width and the part 6b of the wide line path width can be mitigated, and it is possible to suppress reflections and suppress a distortion of a waveform. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、プリント基板お
よび多ピンコネクタ実装用プリント基板に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed board and a printed board for mounting a multi-pin connector.

【0002】[0002]

【従来の技術】図4は従来の多ピンコネクタ実装用プリ
ント基板を示す断面図であり、図において、1は多ピン
コネクタ、2はそのコネクタピン、3はピンピッチであ
る。また、4は多ピンコネクタ実装用プリント基板、5
はコネクタピン2が挿入されるスルーホール、6はその
スルーホール5に接続された信号線路、7はグランド、
8は信号線路6を挟むようにグランド7の間に設けられ
た誘電体である。図5は従来の多ピンコネクタ実装用プ
リント基板を示す平面図であり、図において、6aはス
ルーホール5に接続された信号線路6の線路幅の狭い部
分、6bは信号線路6の線路幅の広い部分である。図6
は周波数と導体損との関係を示す特性図である。
2. Description of the Related Art FIG. 4 is a sectional view showing a conventional printed circuit board for mounting a multi-pin connector. In the figure, 1 is a multi-pin connector, 2 is its connector pin, and 3 is a pin pitch. Further, 4 is a printed circuit board for mounting a multi-pin connector, 5
Is a through hole into which the connector pin 2 is inserted, 6 is a signal line connected to the through hole 5, 7 is a ground,
Reference numeral 8 is a dielectric provided between the grounds 7 so as to sandwich the signal line 6. FIG. 5 is a plan view showing a conventional printed circuit board for mounting a multi-pin connector. In the figure, 6a is a narrow portion of the signal line 6 connected to the through hole 5, and 6b is a line width of the signal line 6. It is a wide area. Figure 6
FIG. 4 is a characteristic diagram showing a relationship between frequency and conductor loss.

【0003】次に動作について説明する。多ピンのコネ
クタをプリント基板に実装する場合に、多ピン間に信号
線路を通す必要がある。このようなプリント基板は、例
えば、「High−SpeedDigtal Desi
ne:Howard Johnson著」に示されてい
る。図4は多ピンコネクタ1を、多ピンコネクタ実装用
プリント基板4に実装する方法を示したものである。多
ピンコネクタ1のコネクタピン2は、多ピンコネクタ実
装用プリント基板4に設けられたスルーホール5に直接
取り付けられる。従って、コネクタピン2のピンピッチ
3と、スルーホール5のピッチとは同じになる。基板の
実装密度を高めるには、コネクタピン2のピンピッチ
3、すなわち、スルーホール5のピッチを狭くする必要
があり、狭いもので2mmから1mmぐらいである。図
5において、狭いピッチのスルーホール5の間に、信号
線路6を通すためには、信号線路6の線路幅を狭くする
必要がある。一方、信号線路6の線路幅が狭くなると、
信号線路6の導体損が大きくなる。図6は周波数と導体
損との関係を示した特性図であり、周波数が低いと導体
損が小さいので、信号線路6の線路幅が狭くても問題に
はならないが、周波数が1GHzと高くなると導体損が
急激に大きくなり、信号振幅の低下に繋がるので、信号
線路6の線路幅は、広い方が望ましい。このようなこと
から、多ピンコネクタ1が実装されるスルーホール5の
近傍では、信号線路6の線路幅を狭い部分6aにし、そ
の領域以外では、信号線路6の線路幅を広い部分6bに
している。
Next, the operation will be described. When mounting a multi-pin connector on a printed circuit board, it is necessary to pass a signal line between the multi-pins. Such a printed circuit board is, for example, “High-Speed Digital Desi”.
ne: Howard Johnson ”. FIG. 4 shows a method of mounting the multi-pin connector 1 on the multi-pin connector mounting printed board 4. The connector pins 2 of the multi-pin connector 1 are directly attached to the through holes 5 provided in the multi-pin connector mounting printed board 4. Therefore, the pin pitch 3 of the connector pins 2 and the pitch of the through holes 5 are the same. In order to increase the mounting density of the board, it is necessary to narrow the pin pitch 3 of the connector pins 2, that is, the pitch of the through holes 5, and the narrow pitch is about 2 mm to 1 mm. In FIG. 5, in order to pass the signal line 6 between the through holes 5 having a narrow pitch, it is necessary to narrow the line width of the signal line 6. On the other hand, when the line width of the signal line 6 becomes narrow,
The conductor loss of the signal line 6 becomes large. FIG. 6 is a characteristic diagram showing the relationship between the frequency and the conductor loss. Since the conductor loss is small when the frequency is low, it does not matter if the line width of the signal line 6 is narrow, but when the frequency is as high as 1 GHz. It is desirable that the line width of the signal line 6 is wide, because the conductor loss rapidly increases and leads to a decrease in signal amplitude. For this reason, in the vicinity of the through hole 5 in which the multi-pin connector 1 is mounted, the line width of the signal line 6 is set to the narrow portion 6a, and in other regions than that, the line width of the signal line 6 is set to the wide portion 6b. There is.

【0004】[0004]

【発明が解決しようとする課題】従来の多ピンコネクタ
実装用プリント基板は以上のように構成されているの
で、取り扱う信号の周波数が高い場合には、多ピンコネ
クタ1が実装されるスルーホール5の近傍では、信号線
路6の線路幅を狭くし、その領域以外では、信号線路6
の線路幅を広くしている。しかしながら、一般に信号線
路6のインダクタンスは、線路幅に反比例し、線路幅の
狭い部分6aでは、インダクタンスが大きく、線路幅の
広い部分6bでは、インダクタンスが小さくなり、これ
ら線路幅の狭い部分6aと広い部分6bとの線路幅の変
化部分では、特性インピーダンスの変化により、信号が
反射して波形歪みが生じ、信号品質が劣化してしまうな
どの課題があった。
Since the conventional printed circuit board for mounting a multi-pin connector is constructed as described above, when the frequency of the signal to be handled is high, the through hole 5 in which the multi-pin connector 1 is mounted is mounted. The line width of the signal line 6 is narrowed in the vicinity of
The track width is wide. However, in general, the inductance of the signal line 6 is inversely proportional to the line width, and the inductance is large in the narrow line width portion 6a and small in the wide line width portion 6b. In the portion where the line width changes from the portion 6b, there is a problem that the signal is reflected and waveform distortion occurs due to the change in the characteristic impedance, and the signal quality deteriorates.

【0005】この発明は上記のような課題を解決するた
めになされたもので、線路幅が変化する部分での特性イ
ンピーダンスの変化を少なくし、信号の反射を抑え、信
号の波形歪みを最小限にするプリント基板および多ピン
コネクタ実装用プリント基板を得ることを目的とする。
The present invention has been made in order to solve the above problems, and reduces the change in characteristic impedance at the portion where the line width changes, suppresses signal reflection, and minimizes signal waveform distortion. It is intended to obtain a printed circuit board and a printed circuit board for mounting a multi-pin connector.

【0006】[0006]

【課題を解決するための手段】この発明に係るプリント
基板は、信号線路の線路幅の狭い部分を誘電率の大きい
誘電体に配置し、線路幅の広い部分を誘電率の小さい誘
電体に配置した基板を備えたものである。
In a printed circuit board according to the present invention, a portion having a narrow line width of a signal line is arranged on a dielectric having a large dielectric constant, and a portion having a wide line width is arranged on a dielectric having a small dielectric constant. It is equipped with a substrate.

【0007】この発明に係る多ピンコネクタ実装用プリ
ント基板は、多ピンコネクタが実装される領域近傍の線
路幅を狭くし、その領域以外の線路幅を広くした信号線
路と、信号線路の線路幅の狭い部分を誘電率の大きい誘
電体に配置し、線路幅の広い部分を誘電率の小さい誘電
体に配置した基板とを備えたものである。
The printed circuit board for mounting a multi-pin connector according to the present invention has a signal line in which the line width near the region where the multi-pin connector is mounted is narrowed and the line width outside the region is wide, and the line width of the signal line. And a substrate having a wide line width arranged on a dielectric having a small dielectric constant.

【0008】この発明に係る多ピンコネクタ実装用プリ
ント基板は、信号線路の線路幅を徐々に変化させるよう
にしたものである。
In the printed board for mounting a multi-pin connector according to the present invention, the line width of the signal line is gradually changed.

【0009】この発明に係る多ピンコネクタ実装用プリ
ント基板は、線路幅を徐々に変化させた信号線路を、誘
電率を徐々に変化させた誘電体に配置する基板を備えた
ものである。
A printed circuit board for mounting a multi-pin connector according to the present invention includes a board in which a signal line whose line width is gradually changed is arranged on a dielectric whose dielectric constant is gradually changed.

【0010】[0010]

【発明の実施の形態】以下、この発明の実施の一形態を
説明する。 実施の形態1.図1はこの発明の実施の形態1による多
ピンコネクタ実装用プリント基板を示す平面図であり、
図において、5はスルーホール、11は多ピンコネクタ
が実装される領域、12はその他の領域、6aは多ピン
コネクタが実装される領域11に設けられ、スルーホー
ル5に接続された信号線路の線路幅の狭い部分、6bは
その他の領域12に設けられた信号線路の線路幅の広い
部分である。また、13は多ピンコネクタが実装される
領域11に配置された誘電率の大きい誘電体(基板)、
14はその他の領域12に配置された誘電率の小さい誘
電体(基板)である。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a plan view showing a printed board for mounting a multi-pin connector according to Embodiment 1 of the present invention,
In the figure, 5 is a through hole, 11 is a region in which a multi-pin connector is mounted, 12 is another region, and 6a is a region 11 in which a multi-pin connector is mounted. A portion with a narrow line width, 6b is a portion with a wide line width of the signal line provided in the other region 12. Further, 13 is a dielectric (board) having a large dielectric constant arranged in the region 11 where the multi-pin connector is mounted,
Reference numeral 14 is a dielectric (substrate) arranged in the other region 12 and having a small dielectric constant.

【0011】次に動作について説明する。図1に示すよ
うに、多ピンコネクタが実装される領域11の信号線路
の線路幅を、その他の領域12の信号線路の線路幅より
も狭くし、線路幅の狭い部分の誘電率を、線路幅の広い
部分の誘電率よりも大きくする。この構成によれば、多
ピンコネクタが実装される領域11以外の大部分の領域
12の信号線路の線路幅を広くすることができ、信号周
波数が高くても導体損による出力低下を少なくすること
ができる。また、線路幅の狭い部分6aでは、インダク
タンスが大きく、線路幅の広い部分6bでは、インダク
タンスが小さくなる。しかしながら、線路幅の狭い部分
6aでは、誘電率の大きい誘電体によりグランドとの間
に大きなキャパシタンスが生じ、線路幅の広い部分6b
では、誘電率の小さい誘電体によりグランドとの間に小
さなキャパシタンスが生じる。従って、これらインダク
タンスとキャパシタンスとの相殺によって、線路幅の狭
い部分6aと広い部分6bとの線路幅の変化部分では、
特性インピーダンスの変化が緩和され、反射を抑え、波
形歪みを抑えることができる。なお、多ピンコネクタ実
装用プリント基板は、マイクロストリップ基板、トリプ
レート基板、その他の基板であっても良い。
Next, the operation will be described. As shown in FIG. 1, the line width of the signal line in the region 11 in which the multi-pin connector is mounted is made narrower than the line width of the signal line in the other region 12, and the dielectric constant of the narrow line width portion is It should be larger than the dielectric constant of the wide part. With this configuration, it is possible to widen the line width of the signal line in most of the region 12 other than the region 11 in which the multi-pin connector is mounted, and reduce the output decrease due to the conductor loss even if the signal frequency is high. You can Further, the inductance is large in the portion 6a where the line width is narrow, and the inductance is small in the portion 6b where the line width is wide. However, in the portion 6a where the line width is narrow, a large capacitance is generated between the portion 6a having a large dielectric constant and the ground, and the portion 6b where the line width is wide.
Then, a small dielectric constant causes a small capacitance to the ground. Therefore, due to the cancellation of the inductance and the capacitance, the line width changing portion between the narrow line width portion 6a and the wide line portion 6b is
Changes in the characteristic impedance are alleviated, reflection can be suppressed, and waveform distortion can be suppressed. The printed board for mounting the multi-pin connector may be a microstrip board, a tri-plate board, or another board.

【0012】実施の形態2.図2はこの発明の実施の形
態2による多ピンコネクタ実装用プリント基板を示す平
面図であり、図において、15は多ピンコネクタが実装
される領域11とその他の領域12との境界に設けれら
れ、信号線路の線路幅を徐々に変化させるテーパ部であ
る。その他の構成については、図1と同一である。
Embodiment 2. 2 is a plan view showing a printed board for mounting a multi-pin connector according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 15 is provided at a boundary between a region 11 where a multi-pin connector is mounted and another region 12. The tapered portion gradually changes the line width of the signal line. Other configurations are the same as those in FIG.

【0013】次に動作について説明する。上記実施の形
態1では、図1に示したように、信号線路の線路幅の狭
い部分6aと広い部分6bとの線路幅の変化部分は、急
激に線路幅が変化しているので、信号にモード変換が生
じ、高次モードが発生してしまうことが懸念される。そ
こで、信号線路の線路幅の狭い部分6aと広い部分6b
との線路幅の変化部分に、線路幅を徐々に変化させるテ
ーパ部15を設ける。この構成によれば、線路幅を徐々
に変化させたことによって、線路幅の変化部分における
インダクタンスの変化が緩和され、特性インピーダンス
の変化がさらに緩和され、反射を抑え、波形歪みを抑え
ることができる。また、信号のモード変換を緩和し、高
次モードの発生を少なくすることができる。
Next, the operation will be described. In the above-described first embodiment, as shown in FIG. 1, since the line width changes rapidly between the narrow line width portion 6a and the wide line portion 6b of the signal line, the line width changes to a signal. There is a concern that mode conversion will occur and a higher-order mode will occur. Therefore, the narrow portion 6a and the wide portion 6b of the signal line
A taper portion 15 that gradually changes the line width is provided at the part where the line width changes. According to this configuration, by gradually changing the line width, the change in the inductance in the changing portion of the line width is alleviated, the change in the characteristic impedance is further alleviated, reflection can be suppressed, and waveform distortion can be suppressed. . In addition, mode conversion of signals can be relaxed and occurrence of higher-order modes can be reduced.

【0014】実施の形態3.図3はこの発明の実施の形
態3による多ピンコネクタ実装用プリント基板を示す平
面図であり、図において、16は多ピンコネクタが実装
される領域11とその他の領域12との境界に配置さ
れ、誘電率を徐々に変化させた誘電体からなる誘電率変
化部である。その他の構成については、図2と同一であ
る。
Embodiment 3. 3 is a plan view showing a multi-pin connector mounting printed circuit board according to a third embodiment of the present invention. In the figure, 16 is arranged at the boundary between a region 11 where the multi-pin connector is mounted and another region 12. , A dielectric constant changing portion made of a dielectric material whose dielectric constant is gradually changed. Other configurations are the same as those in FIG.

【0015】次に動作について説明する。図3に示すよ
うに、信号線路の線路幅の狭い部分6aと広い部分6b
との線路幅の変化部分に、線路幅を徐々に変化させるテ
ーパ部15を設け、さらに、テーパ部15の線路幅の変
化に応じて、誘電率を徐々に変化させた誘電体からなる
誘電率変化部16を配置する。この構成によれば、線路
幅の変化に応じて誘電率を徐々に変化させたことによっ
て、特性インピーダンスの変化を極めて少なくすること
ができ、反射を抑え、波形歪みを抑えることができる。
また、信号の電磁界分布が徐々に変化するため、モード
変換を抑え、高次モードの発生を無くすことができる。
Next, the operation will be described. As shown in FIG. 3, the narrow portion 6a and the wide portion 6b of the signal line are provided.
A taper portion 15 for gradually changing the line width is provided at a portion where the line width changes with, and a dielectric constant made of a dielectric material having a dielectric constant gradually changed according to the change in the line width of the taper portion 15. The changing portion 16 is arranged. According to this configuration, since the dielectric constant is gradually changed according to the change of the line width, the change of the characteristic impedance can be extremely reduced, the reflection can be suppressed, and the waveform distortion can be suppressed.
In addition, since the electromagnetic field distribution of the signal gradually changes, mode conversion can be suppressed and generation of higher-order modes can be eliminated.

【0016】[0016]

【発明の効果】以上のように、この発明によれば、プリ
ント基板において、信号線路の線路幅の狭い部分を誘電
率の大きい誘電体に配置し、線路幅の広い部分を誘電率
の小さい誘電体に配置した基板を備えるように構成した
ので、線路幅が変化する部分での特性インピーダンスの
変化を少なくすることができ、反射を抑え、波形歪みを
最小限にすることができる効果がある。
As described above, according to the present invention, in the printed circuit board, the portion of the signal line having a narrow line width is arranged on the dielectric having a large dielectric constant, and the portion of the signal line having a wide line width has a small dielectric constant. Since it is configured to include the substrate arranged in the body, it is possible to reduce the change in the characteristic impedance at the portion where the line width changes, suppress reflection, and minimize the waveform distortion.

【0017】この発明によれば、多ピンコネクタ実装用
プリント基板において、多ピンコネクタが実装される領
域近傍の線路幅を狭くし、その領域以外の線路幅を広く
した信号線路と、信号線路の線路幅の狭い部分を誘電率
の大きい誘電体に配置し、線路幅の広い部分を誘電率の
小さい誘電体に配置した基板とを備えるように構成した
ので、多ピンコネクタが実装される領域近傍以外の大部
分の線路幅を広くすることができ、信号周波数が高くな
っても導体損による出力低下を少なくすることができ
る。また、線路幅が変化する部分での特性インピーダン
スの変化を少なくすることができ、反射を抑え、波形歪
みを最小限にすることができる効果がある。
According to the present invention, in the printed circuit board for mounting a multi-pin connector, the signal line in which the line width near the region where the multi-pin connector is mounted is narrowed and the line width outside the region is wide, and the signal line Since the part with the narrow line width is placed on the dielectric with a large dielectric constant and the part with the wide line width is placed on the dielectric with a small dielectric constant, it is configured near the area where the multi-pin connector is mounted. It is possible to widen most of the line width other than the above, and it is possible to reduce the output decrease due to the conductor loss even when the signal frequency becomes high. Further, it is possible to reduce the change in the characteristic impedance at the portion where the line width changes, suppress reflection, and minimize the waveform distortion.

【0018】この発明によれば、多ピンコネクタ実装用
プリント基板において、信号線路の線路幅を徐々に変化
させるように構成したので、線路幅が変化する部分での
特性インピーダンスの変化をさらに少なくすることがで
きると共に、高次モードの発生を少なくすることができ
る効果がある。
According to the present invention, since the line width of the signal line is gradually changed in the printed board for mounting a multi-pin connector, the change in the characteristic impedance at the portion where the line width changes is further reduced. In addition to that, it is possible to reduce the occurrence of high-order modes.

【0019】この発明によれば、多ピンコネクタ実装用
プリント基板において、線路幅を徐々に変化させた信号
線路を、誘電率を徐々に変化させた誘電体に配置する基
板を備えるように構成したので、線路幅および誘電率が
変化する部分での特性インピーダンスの変化をさらに少
なくすることができると共に、高次モードの発生を防ぐ
ことができる効果がある。
According to the present invention, in the printed board for mounting a multi-pin connector, the signal line whose line width is gradually changed is arranged on the dielectric whose temperature is gradually changed. Therefore, it is possible to further reduce the change in the characteristic impedance in the portion where the line width and the dielectric constant change, and it is possible to prevent the higher-order mode from occurring.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の実施の形態1による多ピンコネク
タ実装用プリント基板を示す平面図である。
FIG. 1 is a plan view showing a multi-pin connector mounting printed circuit board according to a first embodiment of the present invention.

【図2】 この発明の実施の形態2による多ピンコネク
タ実装用プリント基板を示す平面図である。
FIG. 2 is a plan view showing a multi-pin connector mounting printed circuit board according to a second embodiment of the present invention.

【図3】 この発明の実施の形態3による多ピンコネク
タ実装用プリント基板を示す平面図である。
FIG. 3 is a plan view showing a multi-pin connector mounting printed circuit board according to a third embodiment of the present invention.

【図4】 従来の多ピンコネクタ実装用プリント基板を
示す断面図である。
FIG. 4 is a cross-sectional view showing a conventional printed circuit board for mounting a multi-pin connector.

【図5】 従来の多ピンコネクタ実装用プリント基板を
示す平面図である。
FIG. 5 is a plan view showing a conventional printed circuit board for mounting a multi-pin connector.

【図6】 周波数と導体損との関係を示す特性図であ
る。
FIG. 6 is a characteristic diagram showing the relationship between frequency and conductor loss.

【符号の説明】[Explanation of symbols]

1 多ピンコネクタ、2 コネクタピン、3 ピンピッ
チ、4 多ピンコネクタ実装用プリント基板、5 スル
ーホール、6 信号線路、6a 狭い部分、6b 広い
部分、7 グランド、8 誘電体、11,12 領域、
13,14 誘電体(基板)、15 テーパ部、16
誘電率変化部。
1 multi-pin connector, 2 connector pins, 3 pin pitch, 4 multi-pin connector mounting printed circuit board, 5 through holes, 6 signal lines, 6a narrow part, 6b wide part, 7 ground, 8 dielectric, 11, 12 area,
13, 14 Dielectric (substrate), 15 Tapered part, 16
Dielectric constant changing part.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 線路幅の狭い部分と広い部分とを有する
信号線路と、 上記信号線路の線路幅の狭い部分を誘電率の大きい誘電
体に配置し、線路幅の広い部分を誘電率の小さい誘電体
に配置した基板とを備えたプリント基板。
1. A signal line having a narrow line width portion and a wide line portion, and a narrow line width portion of the signal line is disposed on a dielectric having a large dielectric constant, and a wide line width portion having a small dielectric constant. A printed circuit board having a substrate arranged on a dielectric.
【請求項2】 多ピンコネクタが実装される領域近傍の
線路幅を狭くし、その領域以外の線路幅を広くした信号
線路と、 上記信号線路の線路幅の狭い部分を誘電率の大きい誘電
体に配置し、線路幅の広い部分を誘電率の小さい誘電体
に配置した基板とを備えた多ピンコネクタ実装用プリン
ト基板。
2. A signal line having a narrow line width in the vicinity of a region where a multi-pin connector is mounted and a line width outside the region, and a dielectric having a large dielectric constant in a portion of the signal line having a narrow line width. And a printed circuit board for mounting a multi-pin connector, the printed circuit board having a wide line width arranged on a dielectric having a small dielectric constant.
【請求項3】 信号線路の線路幅を徐々に変化させたこ
とを特徴とする請求項2記載の多ピンコネクタ実装用プ
リント基板。
3. The printed board for mounting a multi-pin connector according to claim 2, wherein the line width of the signal line is gradually changed.
【請求項4】 基板は、線路幅を徐々に変化させた信号
線路を、誘電率を徐々に変化させた誘電体に配置したこ
とを特徴とする請求項3記載の多ピンコネクタ実装用プ
リント基板。
4. The printed circuit board for mounting a multi-pin connector according to claim 3, wherein the board has a signal line whose line width is gradually changed and which is arranged on a dielectric whose dielectric constant is gradually changed. .
JP2002016001A 2002-01-24 2002-01-24 Printed circuit boards and printed circuit boards for mounting multi-pin connectors Pending JP2003218481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002016001A JP2003218481A (en) 2002-01-24 2002-01-24 Printed circuit boards and printed circuit boards for mounting multi-pin connectors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002016001A JP2003218481A (en) 2002-01-24 2002-01-24 Printed circuit boards and printed circuit boards for mounting multi-pin connectors

Publications (1)

Publication Number Publication Date
JP2003218481A true JP2003218481A (en) 2003-07-31

Family

ID=27652197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002016001A Pending JP2003218481A (en) 2002-01-24 2002-01-24 Printed circuit boards and printed circuit boards for mounting multi-pin connectors

Country Status (1)

Country Link
JP (1) JP2003218481A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245291A (en) * 2005-03-03 2006-09-14 Nec Corp Transmission line and wiring formation method
EP1708550A1 (en) * 2005-03-31 2006-10-04 TDK Corporation Electronic circuit
WO2007102597A1 (en) * 2006-03-03 2007-09-13 Nec Corporation Broadband transition from a via interconnection to a planar transmission line in a multilayer substrate
US8476537B2 (en) 2007-08-31 2013-07-02 Nec Corporation Multi-layer substrate
JP2013179692A (en) * 2013-05-28 2013-09-09 Kyocer Slc Technologies Corp Wiring board
CN113015322A (en) * 2019-12-18 2021-06-22 谷歌有限责任公司 Transition packaging for printed circuit boards

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245291A (en) * 2005-03-03 2006-09-14 Nec Corp Transmission line and wiring formation method
EP1708550A1 (en) * 2005-03-31 2006-10-04 TDK Corporation Electronic circuit
WO2007102597A1 (en) * 2006-03-03 2007-09-13 Nec Corporation Broadband transition from a via interconnection to a planar transmission line in a multilayer substrate
US8013685B2 (en) 2006-03-03 2011-09-06 Renesas Electronics Corporation Broadband transition from a via interconnection to a planar transmission line in a multilayer substrate
US8085112B2 (en) 2006-03-03 2011-12-27 Nec Corporation Broadband transition from a via interconnection to a planar transmission line in a multilayer substrate
US8476537B2 (en) 2007-08-31 2013-07-02 Nec Corporation Multi-layer substrate
JP2013179692A (en) * 2013-05-28 2013-09-09 Kyocer Slc Technologies Corp Wiring board
CN113015322A (en) * 2019-12-18 2021-06-22 谷歌有限责任公司 Transition packaging for printed circuit boards
EP3840545A1 (en) * 2019-12-18 2021-06-23 Google LLC Package to printed circuit board transition
US11147161B2 (en) 2019-12-18 2021-10-12 Google Llc Package to printed circuit board transition
TWI858203B (en) * 2019-12-18 2024-10-11 美商谷歌有限責任公司 Multi-layer printed circuit board and method for fabricating the same

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