JP2003218211A - Method of manufacturing fuse element, fuse element, method of forming wiring structure, wiring structure, semiconductor device - Google Patents

Abstract

(57) Abstract: A method of manufacturing a fuse element, which can be easily cut as required, a fuse element, and a semiconductor device using the same are provided. SOLUTION: An interlayer insulating film 101 is formed on a substrate 100, and dry etching is performed based on a resist pattern formed on a photoresist layer 102 to form holes 32.
Form one. Interlayer insulating film 1 in which hole 321 is formed
01 on the aluminum film 103 by sputtering.
Is formed, a resist pattern 104 is formed at a portion where the bit line 13b is formed, and then anisotropic etching is performed using a dry etching process. In this dry etching process, the aluminum film 1 is formed only on the side wall of the hole 321.
03 is left, and the conductive layer 322 can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a fuse element used in a semiconductor device, a fuse element, a method of manufacturing a wiring structure, a wiring structure, and an improvement of a semiconductor device using these.

[0002]

2. Description of the Related Art Generally, in a semiconductor device, particularly in a semiconductor memory device such as a DRAM, a method of forming a redundant circuit in addition to a regular circuit is used in order to improve the yield in the manufacturing process. This is because a redundant circuit, which is a circuit that can replace part or all of a regular circuit, is formed together with the regular circuit in advance, and an operation test of the circuit is performed during the manufacturing process. When a defect such as a short circuit of a word line or a word line is detected, the defective portion is replaced with a normally operating redundant circuit. Conventionally, as a method of replacing such a redundant circuit, it is known to provide a fuse element on a semiconductor device. That is, a fuse element is provided in each of the normal circuit and the redundant circuit, and the fuse circuit is cut (blown) to select the normal circuit and the redundant circuit.
It is a replacement. For this type of fuse element, for example, a metal such as aluminum is used as a constituent material of the cut portion, and in order to cut the cut portion, for example, beam irradiation using a laser or the like, a method of passing a high current, etc. Is used.

[0003]

By the way, in recent years, as the performance and integration of semiconductor devices have been improved, a decrease in signal transmission speed (wiring delay) due to miniaturization of wiring has become a problem. ing. In order to solve such a problem, a technique of widening the film thickness of the wiring to secure the cross-sectional area of the wiring and preventing the wiring delay is widely adopted.

However, in the conventional fuse element, since a part of the wiring is used as it is, the thickness of the cutting portion becomes thicker as the film thickness of the wiring increases, and the cutting method described above is used. However, there were technical problems such as insufficient power supply, increased power required for cutting, and longer cutting time.

Further, in the field of semiconductor devices, as described above, there is a technical problem that the miniaturization of wiring is required in accordance with higher integration and higher performance.

The present invention has been made to solve the above technical problems, and an object thereof is to provide a method of manufacturing a fuse element and a fuse element which can be easily cut as required. And to provide a semiconductor device using the same.

Another object of the present invention is to provide a method of forming a wiring structure, a wiring structure, and a semiconductor device using the wiring structure, which can achieve miniaturization of the wiring.

[0008]

Based on the above object, the inventors of the present invention have made extensive studies and found that it is effective to reduce the thickness of the conductive layer provided in the cut portion of the fuse element. . Therefore, the method for manufacturing a fuse element of the present invention includes an insulating layer forming step of forming an insulating layer on a substrate,
The method is characterized by including a step forming step of forming a step on the surface of the insulating layer and a conductive layer forming step of forming a conductive layer as a fuse on a side wall of the formed step.

Here, the step forming step can be a hole forming step of forming a hole having a step on the surface of the insulating layer, for example. Further, in this hole forming step, it is preferable to simultaneously form a contact hole that exposes the lower layer wiring provided under the insulating layer.

Further, the conductive layer forming step includes a conductive film forming step of forming a conductive film on the surface of the insulating layer after the step is formed,
And a conductive film etching step of anisotropically etching the formed conductive film. Furthermore, in the conductive layer forming step, it is preferable to form a wiring that is electrically connected to the conductive layer at the same time as the conductive layer.

Further, the fuse element of the present invention is characterized by including an insulating layer provided on the substrate and having a step formed on the surface thereof, and a conductive layer as a fuse provided on the sidewall of the step. There is.

In such a fuse element, the step can be formed at the end of the hole provided on the surface of the insulating layer. Further, it is preferable that the hole is provided with a narrowed portion whose width is narrower in the longitudinal direction than in the front and rear thereof. The relationship between the width of the hole in the direction orthogonal to the longitudinal direction and the depth of the hole is preferably set in the range of 2: 3 to 2: 4. Further, it is preferable that the width of the hole in the direction orthogonal to the longitudinal direction is set to be larger than the width of the wiring electrically connected to the conductive layer at the longitudinal end portion of the hole.

Further, the fuse element of the present invention is a fuse element including a fuse having a cut portion which is cut as necessary, and a wiring electrically connected to the cut portion, and the cut portion is cut off. It is characterized in that the area is set smaller than the cross-sectional area of the wiring.

The present invention is also applicable to a semiconductor device having the above-mentioned fuse element. In such a semiconductor device, if the width of the fuse element in the direction orthogonal to the longitudinal direction is set larger than the width of the wiring connected to the conductive layer at the longitudinal end of the fuse element, the adjacent fuses are It is preferable to stagger the elements.

Further, the present inventor has noticed that a fine wiring structure can be formed by applying the method of the method of manufacturing the fuse element described above. Therefore, the method for forming a wiring structure of the present invention includes an insulating layer forming step of forming an insulating layer on a substrate, a groove forming step of forming a groove on the surface of the insulating layer, and a side wall portion of the formed groove. And a sidewall wiring forming step of forming a wall wiring.

Here, the sidewall wiring forming step includes a wiring film forming step of forming a wiring film on the surface of the insulating layer after the groove is formed, and a wiring film etching step of anisotropically etching the formed wiring film. , Can be provided. Further, it is preferable that the method further includes an inter-wiring insulating portion forming step of forming an insulating portion between the sidewall wirings.

Further, the wiring structure of the present invention is characterized by including an insulating layer provided on the substrate and having a groove portion formed on the surface thereof, and a sidewall wiring provided on a side wall of the groove portion.

In such a wiring structure, it is preferable to provide an insulating portion between the sidewall wirings.
Further, a semiconductor device having the above-described wiring structure is also an application target of the present invention.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail based on the embodiments shown in the accompanying drawings. First Embodiment FIG. 1 shows a first embodiment of a semiconductor device (DRAM) using the fuse element according to the present invention. In the present embodiment, the DRAM has a DRAM cell 1 in which data is stored, a sense amplifier 2 for amplifying an output voltage from the DRAM cell 1, and a defective normal circuit for replacement. It has a redundant circuit 3.

In the DRAM cell 1, reference numeral 11 is a memory cell arranged in a matrix, reference numeral 12 (12
a to 12j) are control signal lines (word lines) for selecting one column from the memory cells 11 arranged in a matrix,
Reference numeral 13 (13a to 13j) is a signal line (bit line) for taking out data from the memory cell 11. Here, each memory cell 11 includes a word line 12 and a bit line 13.
The data writing / reading can be executed by increasing the voltage of the word line 12 corresponding to the read / write address.

The sense amplifier 2 also has an amplifier section 21 to which each of the bit lines 13 is connected. Further, the redundant circuit 3 has fuse elements 32 (32a to 32j) respectively connected to the bit lines 13 via the circuit 31, and a power supply line 33 for applying a predetermined voltage to each bit line 13. ing.

FIG. 2A shows the fuse element 3 shown in FIG.
Of the two, the fuse elements 32a and 32b arranged adjacent to each other
2B is a partially enlarged view of the fuse element 32b. In the figure, reference numeral 101 indicates an interlayer insulating film, which is a substrate 100 described later.
(See FIG. 4). In addition, each fuse element 3
2 has holes 321 each having a concave opening, and the side wall thereof has a conductive layer 3 made of aluminum.
22 is provided. Further, the width of the hole 321 is set wider than that of the bit line 13 to be attached,
The bit line 13 is also made of aluminum.

Furthermore, in this embodiment, the convex portion 3211 formed at the end of the hole 321 of the fuse element 32b.
And a concave portion 3212 formed in the central portion of the hole 321 of the fuse element 32a face each other, and the convex portion 3211
Are arranged so that the tip ends of the two enter into the opposed concave portions 3212 side. The concave portion 3212 is a narrow constricted portion, and if necessary, the portion is irradiated with a laser beam and melted to form a cut portion 323. Note that FIG. 3A illustrates a state in which the cutting portion 323 is formed only in the fuse element 32a.

Next, taking the fuse element 32b as an example, FIG.
A method of manufacturing the fuse element 32 will be described with reference to FIG. 3 to 5, the same reference numeral (for example, (a))
Of the drawings show corresponding to the same process,
3 is a cross section taken along the line AA ′ of FIG. 2 (b), and FIG.
BB ′ cross section of FIG. 5 and FIG. 5 shows the plane of FIG.

In FIG. 3A and FIG. 4A, reference numeral 10
Reference numeral 0 denotes a substrate, and in a DRAM, for example, the semiconductor substrate is provided with elements such as transistors and memory capacitors, which are connected by wiring.
In the figure, detailed illustration of these semiconductor substrates, transistors, memory capacitors, wirings, etc. is omitted. Then, the interlayer insulating film 101 is formed on the substrate 100.
To form. This interlayer insulating film 101 is formed of, for example, SiO.
_It consists of ₂ and the film is deposited by plasma CVD. Next, a resist pattern is formed by the photolithography technique. That is, the interlayer insulating film 101
A photoresist is evenly applied on the photoresist to form a photoresist layer 102, and the photoresist layer 102 is exposed through a photomask (not shown) to print a pattern, and then a photoresist is applied with a predetermined chemical solution. Layer 1
By processing 02, the photoresist layer 102 in the exposed portion is removed, and a desired resist pattern is obtained. In addition, here, as shown in FIG. 5A, a concave pattern corresponding to the hole 321 of the fuse element 32b is formed. In this step, the substrate 1
Wiring (not shown) provided on the wiring layer 00 and the interlayer insulating film 101.
A pattern (not shown) for forming a contact hole is also formed at the same time for forming a hole in the interlayer insulating film 101 in order to connect with the bit line 13 formed thereon.

Next, dry etching is performed using the formed resist pattern. The etching conditions are as follows. <Etching conditions> Device: parallel plate plasma RIE (reactive ion etching) Device gas: C ₄ F ₈ / Ar / O ₂ = 11/400/8 cm ³ /
min Top power: 2000W (27MHz) Bottom power: 1200W (800kHz) Pressure: 4.0Pa Temperature: 20 ° C

By this dry etching, the portion of the interlayer insulating film 101 not covered with the resist pattern is removed, and the hole 321 having the same pattern as the resist pattern is formed in the interlayer insulating film 101 (FIGS. 3B and 4).
(B) and FIG. 5 (b)) are formed. Here, the hole 321 has a substantially rectangular cross section.
Then, ashing is performed to remove the remaining photoresist layer 102. The ashing conditions are as follows. <Ashing conditions> Device: ICP plasma ashing device Gas: O ₂ = 3750 cm ³ / min ICP power: 900 W (13.56 MHz) Pressure: 150 Pa Temperature: 250 ° C. As a result, FIG. 3 (b), FIG. The state is as shown in FIG. The contact hole (not shown) is also formed in the interlayer insulating film 101 by the above-described etching and ashing process. Therefore,
Since the hole 321 of the fuse element 32b can be formed in the contact hole forming process, the number of steps for forming the hole 321 does not increase.

Next, the aluminum film 1 is sputtered on the interlayer insulating film 101 having the holes 321 formed therein.
03 is formed (FIG. 3C, FIG. 4C, FIG. 5C).
reference). At this time, the aluminum film 103 is uniformly attached to the surface of the interlayer insulating film 101. Then, the resist pattern is formed again by the photography technique. However, here, the resist pattern 104 is formed on the aluminum film 103 corresponding to the formation portion of the bit line 13.
Are formed (see FIGS. 3C and 5C).

Next, the formed resist pattern 104
Is used to perform dry etching. The etching conditions are as follows. <Etching conditions> Device: ICP type plasma RIE (reactive ion etching) device, Step 1 Gas: Cl ₂ / BCl ₃ / CHF ₃ / Ar = 50/40 /
5/40 sccm ICP power: 700 W Bias power: 125 W Pressure: 0.75 Pa ・ Step 2 gas: Cl ₂ / BCl ₃ / CHF ₃ / Ar = 80/60 /
3/40 sccm ICP power: 900 W Bias power: 120 W Pressure: 1.25 Pa Step 3 gas: Cl ₂ / BCl ₃ / CHF ₃ / Ar = 50/40 /
3 / 40sccm ICP power: 700W Bias power: 125W Pressure: 1.25Pa

By this dry etching, the portion of the aluminum film 103 which is not covered with the resist pattern 104 is removed. However, since the dry etching process is so-called anisotropic etching, under the above-mentioned conditions, Part of the portion of the aluminum film 103 that was thicker when viewed from above (the sidewall of the hole 321) remains, and the conductive layer 322 is formed (FIG. 3D, FIG. d), see FIG. 5 (d). Then, ashing is performed again to remove the resist pattern 104, and the bit line 13 connected to the conductive layer 322 is formed. This ashing condition is the same as the above-mentioned ashing condition. By the above process, FIG.
In the state shown in FIGS. 4D and 5D, the fuse element 32b is formed.

As described above, in this embodiment, the fuse element 32 which can be easily cut can be manufactured by using the anisotropic etching process. Further, since the width of the fuse element 32 with respect to the bit line 13 is increased, there is a margin for the shift of the resist pattern 104, and the formation of the bit line 13 is easy. Then, by increasing the width of the fuse element 32, the conductive layer 3
22 can also be easily formed. Furthermore, hall 32
Since 1 is formed in a concave shape and the narrow constricted portion is irradiated with laser to form the cut portion 323, there is no need to shift the irradiation position when forming the cut portion 323, and Since the cross-sectional area of the conductive layer 322 is small, the cut portion 323 can be formed by laser irradiation for one short time. Furthermore, in the present embodiment, the cross-sectional area of the conductive layer 322 of the fuse element 32 can be made smaller than that of the bit line 13, so that the cut portion 323 is formed as compared with the mode in which the bit line 13 is used as a fuse as it is. Will be easier.

Further, in the present embodiment, the holes 321 of the fuse elements 32 are each formed in a concave shape and are arranged in combination, so that, for example, the mode shown in FIG. 6 (a) ( The wiring interval of the bit lines 13 can be made smaller than that of the fuse element 32 having the rectangular holes 321 which is simply arranged in parallel. It goes without saying that the arrangement shown in FIG. 6A may be used. Also, when the fuse elements 32 shown in FIG. 6A are used, the wiring intervals of the bit lines 13 can be reduced by alternately arranging them as shown in FIG. 6B. Further, for example, as shown in FIG. 6C, it is possible to use a fuse element 32 having a hole 321 in which a narrowed portion is formed by providing two concave portions on the side portion. Then, if the fuse elements 32 each having the hole 321 having the narrowed portion shown in FIG. 6C are arranged alternately as shown in FIG. 6B, the wiring of the bit line 13 is formed. The interval can be reduced, and the cut portion 323 can be easily formed by laser irradiation.

Here, the hole 321 of the fuse element 32
The relationship between the width in the direction orthogonal to the longitudinal direction and the depth will be described. Basically, since a current flows through the conductive layer 322, the larger the amount of current (the thicker the film thickness of the conductive layer 322) is, the higher the speed can be made. It cannot be washed away. Further, it is possible to operate even when the current flowing is made small by devising the circuit.

Therefore, the steps of the hole 321 in which the conductive layer 322 is formed will be examined. First, it is known from the past results that it is possible to stably form the cut portion 323 by laser irradiation if the thickness of the conductive layer 322 is 600 nm or less. And Hall 3
The film thickness of the conductive layer 322 formed on the side wall of 21 is determined by the above-described ratio (Aspect Ratio) of the width and the depth of the hole 321.

FIG. 7 shows the aspect ratio and the degree of peeling of the aluminum film 103 to the bottom of the hole 321 by the dry etching process.
Shows the relationship with the one represented by. For example, when the film thickness of the aluminum layer 103 is 1200 nm, the coverage is 50% because the aspect ratio is in the vicinity of 1.5 to 2.0. Therefore, a short margin between wirings (distance for preventing short circuit) is taken into consideration. , And the width is 1600 nm, the required depth is 2400 to 3200 nm.

However, when the cutting portion 323 is formed by applying a high current to the conductive layer 322 instead of forming the cutting portion 323 by laser irradiation, the conductive layer 322 should be formed as thin as possible. Specifically, it is preferably 400 nm or less.

Although the ashing process is used to remove the resist pattern 104 in the present embodiment, the present invention is not limited to this. For example, the ashing process is immersed in fuming nitric acid (HNO ₃ ) at 80 ° C. for 10 minutes. It is possible to remove it by dissolution. Further, although SiO ₂ is used as the interlayer insulating film 101 in the present embodiment, the present invention is not limited to this, and so-called SiOF-based material containing fluorine or SiO _x C _y H _z- based material containing organic material is used. Low-k materials can be used. Then, the above-mentioned l
When the ow-k material is adopted, from the viewpoint of preventing the deterioration of the interlayer insulating film 101, a condition containing no O ₂ (for example, a gas containing H ₂ O, H ₂ , N ₂ , NH ₄ or the like is used). It is preferable that the resist pattern 104 is removed by the process (construction). Further, although the conductive layer 322 is made of aluminum in the present embodiment, the conductive layer 322 is not limited to this, and Al-Cu (aluminum-copper alloy) may be used,
Alternatively, as the base layer of the aluminum film 103, Ti /
You may make it provide TiN.

Second Embodiment In this embodiment, the method for forming the conductive layer 322 of the fuse element 32 described in the first embodiment is shown in FIG.
It is applied to form the word line 12 of.
In the present embodiment, the same parts as those in the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted.

Next, a method of forming the word line 12 will be described with reference to FIG. In FIG. 8A, an interlayer insulating film 111 made of SiO ₂ is formed on the substrate 100 by plasma CVD. Next, a resist pattern is formed by the photolithography technique. That is, a photoresist is uniformly applied on the interlayer insulating film 111 to form a photoresist layer 112, and the photoresist layer 112 is exposed through a photomask (not shown) to print a pattern. By treating the photoresist layer 112 with a predetermined chemical solution, the exposed portion of the photoresist layer 112 is removed, and a desired resist pattern is obtained. Incidentally, here, the pattern corresponding to the two word lines 12 (however, the groove is one)
Shall be formed. In this step, the substrate 1
Wiring (not shown) and the interlayer insulating film 111
A pattern (not shown) for forming a contact hole is formed at the same time for forming a hole in the interlayer insulating film 111 in order to connect to another wiring (not shown) formed on the above.

Next, dry etching is performed using the formed resist pattern. The etching conditions are the same as those described in the dry etching process for the interlayer insulating film 101 of the first embodiment. By this dry etching, the portion of the interlayer insulating film 111 not covered with the resist pattern is removed, and as shown in FIG.
A groove 120 having the same pattern as the resist pattern is formed in the interlayer insulating film 111. Here, the groove 120 has a substantially rectangular cross section. Then, ashing is performed to remove the remaining photoresist layer 112.
The ashing conditions are the same as those described in the ashing process of the photoresist layer 102 described in the first embodiment.

Next, as shown in FIG. 8C, the groove 120
An aluminum film 113 is formed by sputtering on the inter-layer insulation film 111 on which is formed. At this time, the aluminum film 113 is uniformly attached to the surface of the interlayer insulating film 111.

Then, the aluminum film 113 attached on the interlayer insulating film 111 is dry-etched. The etching conditions are the same as those described in the dry etching process for the aluminum film 103 according to the first embodiment. Then, most of the aluminum film 113 is removed, but the portion where the film thickness is thick when viewed from above (the groove 1
Part of the side wall portion 20) remains, and word lines 12a and 12b are formed on both side walls, respectively (see FIG. 8D and FIG. 1).

Then, as shown in FIG. 8E, the protective film 1 is formed on the interlayer insulating film 111 and the word lines 12a and 12b.
14 is covered for protection and interlayer insulation, an insulating portion 114a is formed between the word lines 12a and 12b, and the series of processes is completed.

In this embodiment, the fine word line 12 can be formed by utilizing the anisotropic etching process. Further, as compared with a mode (a mode in which no hole is provided) in which the protective film 114 is formed after the word line 12 is formed on the interlayer insulating film 111 as shown in FIG. 9A, FIG. As shown, wiring (word line 1
Since the film attachment to the shoulder portion of 2a, 12b) is good, it is possible to form a stable wiring.

Other than the above, the configurations described in the above embodiments can be selected or changed to other configurations without departing from the gist of the present invention.

[0046]

As described above, according to the present invention,
Since the conductive layer as the fuse is formed on the step formed in the insulating layer, the conductive layer can be thinly formed, and as a result, the cutting can be easily performed when necessary.

Further, according to the present invention, since the side wall wiring is formed on the side wall of the groove formed in the insulating layer, the side wall wiring can be formed thinly, and as a result, the wiring can be formed. Can be miniaturized.

[Brief description of drawings]

FIG. 1 shows a semiconductor device (DRA according to the first embodiment.
It is explanatory drawing of M).

FIG. 2A is an enlarged view of adjacent fuse elements, and FIG. 2B is an enlarged view of one fuse element.

3 (a) to 3 (d) show a method of manufacturing the fuse element according to the first embodiment in the order of steps, and FIG.
FIG. 6 is a sectional view taken along line AA ′ of FIG.

4A to 4D show a method of manufacturing the fuse element according to the first embodiment in the order of steps, and FIG.
It is a BB 'sectional view of.

5 (a) to 5 (d) show a method of manufacturing the fuse element according to the first embodiment in the order of steps, and FIG.
It is a top view seen from the same direction.

6A to 6C are explanatory views showing another arrangement example of adjacent fuse elements.

FIG. 7 is a graph showing the relationship between the aspect ratio of holes of a fuse element and the coverage.

8A to 8E are cross-sectional views showing a method of forming a wiring according to the second embodiment in the order of steps.

FIG. 9A is a cross-sectional view of a conventional wiring structure,
FIG. 6B is a sectional view of the wiring structure according to the second embodiment.

[Explanation of symbols]

1 ... DRAM cell, 2 ... Sense amplifier, 3 ... Redundant circuit,
11 ... Memory cell, 12 ... Word line, 13 ... Bit line,
32 ... Fuse element, 100 ... Substrate, 101 ... Interlayer insulating film, 102 ... Photoresist layer, 103 ... Aluminum film, 104 ... Resist pattern, 111 ... Interlayer insulating film,
112 ... Photoresist layer, 113 ... Aluminum film,
114 ... Protective film, 114a ... Insulating part, 321 ... Hole,
322 ... Conductive layer, 323 ... Cutting part

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/04 G11C 11/34 371D 5M024 27/10 431 F term (reference) 5F033 HH08 HH09 HH18 HH33 PP15 QQ08 QQ09 QQ11 QQ16 QQ37 RR04 RR11 RR21 SS15 VV11 VV16 XX00 5F038 CD09 CD12 DF05 DT18 EZ15 EZ20 5F064 BB14 BB23 DD05 EE09 EE33 FF02 FF27 FF20 JA5 PR03 JA06A04 JA40AJA40A JA40AJA40AJA40A JA40AJA40A JA40A37A12A37A6A4A4A6A4A6A4A6A4A6A4A4A4A5A6A4A4A4A6A4A6A4A6A5A6A4A5A6A6A5A6A6A5A6A6A5A6A5A6A6A5A6A6A5A6A6A5A6A6A5A6A6A5A6A6A5A6A0A4 AA90 DD80 HH10 LL02 LL11 MM20 PP01 PP05

Claims (19)

[Claims] 1. An insulating layer forming step of forming an insulating layer on a substrate, a step forming step of forming a step on the surface of the insulating layer, and a conductive layer as a fuse formed on a sidewall of the formed step. And a step of forming a conductive layer for manufacturing the fuse element. 2. The method of manufacturing a fuse element according to claim 1, wherein the step forming step comprises a hole forming step of forming a hole having the step on the surface of the insulating layer. 3. The method of manufacturing a fuse element according to claim 2, wherein in the hole forming step, a contact hole for exposing a lower layer wiring provided under the insulating layer is formed. 4. The conductive layer forming step includes a conductive film forming step of forming a conductive film on the surface of the insulating layer after forming the step, and a conductive film etching step of anisotropically etching the formed conductive film. The method for manufacturing a fuse element according to claim 1, further comprising: 5. The method of manufacturing a fuse element according to claim 1, wherein in the conductive layer forming step, a wiring electrically connected to the conductive layer is formed. 6. A fuse element, comprising: an insulating layer provided on a substrate and having a step formed on a surface thereof; and a conductive layer as a fuse provided on a sidewall of the step. 7. The fuse element according to claim 6, wherein the step is formed at an end of a hole provided on the surface of the insulating layer. 8. The fuse element according to claim 7, wherein the hole is provided with a narrowed portion whose width is narrower in the longitudinal direction than in the front and rear thereof. 9. The method according to claim 7, wherein the relationship between the width of the hole in the direction orthogonal to the longitudinal direction and the depth of the hole is set in the range of 2: 3 to 2: 4. Fuse element. 10. The width of the hole in the direction orthogonal to the longitudinal direction is set to be larger than the width of the wiring electrically connected to the conductive layer at the longitudinal end of the hole. Item 8. The fuse element according to item 7. 11. A fuse element comprising a fuse having a cut portion that is cut as necessary, and a wiring electrically connected to the cut portion, wherein a cross-sectional area of the cut portion is equal to that of the wiring. A fuse element characterized by being set smaller than a cross-sectional area. 12. A semiconductor device comprising the fuse element according to claim 6. Description: 13. The width of the fuse element in the direction orthogonal to the longitudinal direction is set to be larger than the width of the wiring connected to the conductive layer at the longitudinal end of the fuse element, and
The semiconductor device according to claim 12, wherein the fuse elements adjacent to each other are arranged alternately. 14. An insulating layer forming step of forming an insulating layer on a substrate, a groove forming step of forming a groove on the surface of the insulating layer, and a sidewall wiring on a side wall portion of the formed groove. A sidewall wiring forming step, and a wiring structure forming method. 15. The sidewall wiring forming step comprises:
15. The wiring film forming step of forming a wiring film on the surface of the insulating layer after forming the groove, and the wiring film etching step of anisotropically etching the formed wiring film. A method for forming a wiring structure as described in 1. 16. The method of forming a wiring structure according to claim 14, further comprising an inter-wiring insulating portion forming step of forming an insulating portion between the sidewall wirings. 17. A wiring structure comprising: an insulating layer provided on a substrate and having a groove formed on a surface thereof; and a sidewall wiring provided on a sidewall of the groove. 18. The wiring structure according to claim 17, wherein an insulating portion is provided between the sidewall wirings. 19. A semiconductor device comprising the wiring structure according to claim 17 or 18.