JP2003218278A - Manufacturing method of wafer level chip scale package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer-level chip scale that can be implemented by a simple process and does not require expensive equipment.
Provided is a method for manufacturing a package. SOLUTION: In each chip portion of a silicon wafer W, a rewiring film 4 is selectively formed on an insulating film 3 by a screen printing method, and a chip electrode 2 is formed through an opening 3a.
A conductor for redistribution is formed in contact with. Next, the insulating sealing film 5 is formed by a screen printing method, and the conductor for rewiring is exposed through the opening 5 a of the sealing film 5. Thereafter, an external electrode 6 having a substantially columnar shape and having a stress relaxation function, which is in contact with the rewiring conductor through the opening 5a, is formed by screen printing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Chip scale (chip size) package (Wafer-
level chip-scale / size package (WL-CSP) manufacturing method, more specifically, a chip-scale package of a semiconductor device is manufactured at a wafer level, that is, in a state before a semiconductor wafer is divided into semiconductor chips. Regarding the method.

[0002]

2. Description of the Related Art In recent years, electronic devices have become smaller and smaller, and accordingly, large-scale integrated circuits (Large-Scale Integr
Semiconductor device packages such as integrated circuits (LSIs) are also becoming smaller. The "package" of a semiconductor device is generally referred to as a "package" in order to protect a semiconductor chip in which a fine circuit is formed and to mount the semiconductor chip on a printed wiring board or an electronic device. This is a container (container) in which the entire surface or part of a semiconductor chip is covered with a sealing material such as plastic or ceramic.

The package of a semiconductor device is usually larger than the internal semiconductor chip. However, the chip scale package has almost the same size as the internal semiconductor chip. This is to reduce the size of the package as close as possible to the size of the internal semiconductor chip.

Wafer level, chip scale,
The package does not perform a package forming operation for each semiconductor chip, but performs a package forming operation for each semiconductor chip in a state of a semiconductor wafer. Therefore, the semiconductor wafer is divided after forming the packages for all the formed chip parts on the semiconductor wafer, and each chip part becomes a semiconductor chip with a package.

In the wafer level chip scale package, a large number of aluminum electrodes (bonding pads) (hereinafter, also referred to as chip electrodes) arranged in a rectangular frame shape at a narrow pitch in a peripheral region of each chip portion are rearranged. Then, it is necessary to form a large number of external electrodes which are two-dimensionally arranged at a wider pitch (lattice or zigzag) on one surface of the package. Therefore, it is necessary to electrically connect the chip electrode and the external electrode. For that purpose, a conductive "rewiring film" is usually formed between the surface of the semiconductor substrate of the chip part and the package. It That is,
Each chip electrode is electrically connected to the corresponding external electrode via a conductor made of a patterned redistribution film.

The wafer level chip scale package and the manufacturing method thereof as described above are disclosed in, for example, Japanese Unexamined Patent Application Publication No.
It is disclosed in Japanese Patent Publication No. 001-144223.

On the other hand, when the semiconductor chip is mounted on the printed wiring board by soldering, the solder joint connecting the semiconductor chip and the printed wiring board may be broken due to the difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board. Therefore, in order to prevent breakage of the solder joint and ensure the connection reliability between the semiconductor chip and the printed wiring board, a technique of forming a columnar stress relaxation portion by an electrolytic copper plating method has been announced.
According to the technique, the height of this stress relaxation portion is about 0.1 mm.

Further, after the columnar stress relaxation portion is formed by the electroplating method, resin is applied to the upper end surface of the stress relaxation portion.
A technique for hardening and protecting the stress relaxation portion has also been announced.

[0009]

In the above-mentioned conventional wafer level chip scale package,
Thin film processes such as sputtering are used to form the "redistribution film". This contributes to an increase in the manufacturing cost of the package because the equipment for performing the thin film process requires a large investment. Therefore, the conventional method of manufacturing the package is difficult in terms of manufacturing cost.

In the case of the above-mentioned prior art in which the columnar stress relaxation portion is formed by the electrolytic copper plating method, it takes a considerably long time to form the stress relaxation portion having a height of about 0.1 mm by the electrolytic copper plating method. is there. In addition, to form a columnar stress relieving part by electrolytic copper plating, a conductor for plating,
Further steps such as resist formation and removal are required. Therefore, this conventional technique also has a manufacturing cost difficulty.

The present invention has been made to solve the above problems, and the object thereof is a wafer level chip which can be implemented by a simple process and does not require expensive equipment. It is to provide a manufacturing method of a scale package.

Another object of the present invention is to provide a method of manufacturing a wafer level chip scale package which can reduce the manufacturing cost.

Still another object of the present invention is to provide a method of manufacturing a wafer level chip scale package which can obtain high connection reliability when mounted.

Still another object of the present invention is to provide a method of manufacturing a wafer level chip scale package which uses materials efficiently.

Still other objects of the present invention not specified herein will be apparent from the following description and the accompanying drawings.

[0016]

(1) A first method for manufacturing a wafer level chip scale package according to the present invention comprises (a) a plurality of chip parts each having a predetermined circuit formed therein. A semiconductor wafer, wherein each surface of the chip portion is covered with a first insulating film,
A step of preparing a plurality of chip electrodes exposed from a plurality of openings of the first insulating film, and (b) a conductive paste on the first insulating film in each of the chip parts. A conductive rewiring film is selectively formed by a printing method used, and thus a plurality of rewiring conductors are respectively brought into contact with the chip electrodes through the plurality of openings of the first insulating film. And (c) in each of the chip parts, a second method is performed by a printing method using an insulating paste so as to cover the plurality of rewiring conductors.
An insulating film is selectively formed, and a plurality of rewiring conductors are formed through a plurality of openings of the second insulating film at positions different from the plurality of openings of the first insulating film. And (d) in each of the chip parts, by selectively forming a conductive film by a printing method using a conductive paste, the rewiring through the plurality of openings of the second insulating film. Forming a plurality of external electrodes in contact with the conductor for use, each of the external electrodes having a substantially columnar shape and having a stress relaxation function.

(2) The first wafer level of the present invention
In the method for manufacturing a chip scale package, the rewiring film is selectively formed on the first insulating film in each of the chip parts by a printing method using a conductive paste (step (b)). Then, the second insulating film having a plurality of openings is selectively formed by a printing method using an insulating paste (step (c)). The openings expose the plurality of rewiring conductors formed by the rewiring film. Further, a plurality of external electrodes that come into contact with the rewiring conductors through the plurality of openings of the second insulating film are formed by a printing method using a conductive paste (step (d)). Therefore, it is not necessary to use a thin film forming method such as a sputtering method for any of the redistribution film, the second insulating film, and the external electrode.

Therefore, the first wafer level
The manufacturing method of the chip scale package can be carried out by a simple process in the atmosphere, and does not require expensive equipment such as a thin film forming apparatus (for example, a sputtering apparatus) or special technology for operating the equipment. is there. Therefore,
The manufacturing cost of the package can be reduced.

The step (b) of forming the redistribution film
Is performed by a printing method using a conductive paste, the conductive paste (for example, A
The g-Pd paste) is hardly wasted. That is, the use efficiency of the material (conductive paste) is higher than that in the case where a conductive thin film is formed on the entire surface of the semiconductor wafer and then the thin film is selectively removed by etching.

Further, since each of the external electrodes is formed in a substantially columnar shape and has a stress relaxation function, when mounting the wafer level chip size package manufactured by the method of the present invention on a printed wiring board or the like. It is possible to directly solder the external electrodes to electrodes such as a printed wiring board using a solder paste or the like. Therefore, high connection reliability can be obtained.

(3) First wafer level of the present invention
In a preferred example of a method of manufacturing a chip scale package, Ag- is used as the conductive paste for the redistribution film.
A Pd paste, that is, a paste containing Ag (silver) and Pd (palladium) as main components is used. In this case, when the chip electrode is made of aluminum, there is an advantage that good electrical connection can be obtained with the chip electrode.

In another preferred example of the method for manufacturing the first wafer level chip scale package of the present invention,
The external electrodes are formed of a solderable material. In this case, there is an advantage that the external electrodes can be directly soldered to a mounting object without solder balls. Further, in this preferred example, it is preferable to use a Cu paste, that is, a paste containing Cu as a main component, as the conductive film for forming the external electrodes. This has an advantage that the conductive film, that is, the external electrode can be formed by a printing method.

In still another preferred example of the method for manufacturing the first wafer level chip scale package of the present invention, the opening of the second insulating film is formed so that the external electrode can directly contact a mounting object. Formed so as to project from the portion.

In still another preferred example of the method for manufacturing the first wafer level chip scale package of the present invention, the step of fixing the solder ball to the external electrode through the opening of the second insulating film ( e) included.

(4) Second wafer level of the present invention
The chip scale package manufacturing method uses a sputtering method instead of the "printing method using a conductive paste" in the step (b) of the first manufacturing method described above.

That is, (a) a semiconductor wafer having a plurality of chip parts each having a predetermined circuit formed therein, each surface of the chip parts being covered with a first insulating film, A step of preparing a plurality of chip electrodes exposed through a plurality of openings of the first insulating film;
(B) In each of the chip portions, a conductive rewiring film is selectively formed on the first insulating film by a sputtering method, so that the conductive redistribution film is formed through the plurality of openings of the first insulating film. Forming a plurality of rewiring conductors respectively brought into contact with the chip electrodes; and (c) forming a plurality of rewiring conductors by a printing method using an insulating paste in each of the chip parts. A second insulating film is selectively formed so as to cover the plurality of openings, and a plurality of the second insulating films are formed through a plurality of openings of the second insulating film at positions different from the plurality of openings of the first insulating film. Exposing the wiring conductor, and (d) in each of the chip portions,
A step of forming a plurality of external electrodes in contact with the rewiring conductor through a plurality of openings of the second insulating film by selectively forming a conductive film by a printing method using a conductive paste; And each of the external electrodes is substantially columnar and has a stress relaxation function.

(5) Second wafer level of the present invention
In the manufacturing method of the chip scale package, the sputtering method is used instead of the "printing method using the conductive paste" in the step (b) of the first manufacturing method of the present invention described above. It cannot be said that it can be carried out in the atmosphere by a simple process, and a sputtering apparatus is also required. Therefore, the degree of reduction in the manufacturing cost of the package is reduced as compared with the first manufacturing method of the present invention. However, in place of that, the rewiring conductor is replaced by the first embodiment of the present invention.
There is an advantage that it can be formed at a higher density than the manufacturing method of.

Further, since the printing method is used for the steps (c) and (d), the manufacturing cost reduction effect close to that of the above-described first manufacturing method of the present invention and the first manufacturing method of the present invention are obtained. The same effect of improving the connection reliability as in the case of the method can be obtained.

(6) Second wafer level of the present invention
In a preferred example of a method for manufacturing a chip scale package, the external electrodes are made of a solderable material. In this case, there is an advantage that the external electrodes can be directly soldered to a mounting object without solder balls. Further, in this preferred example, it is preferable to use a Cu paste, that is, a paste containing Cu as a main component, as the conductive film for forming the external electrodes. This way
There is an advantage that the conductive film, that is, the external electrode can be formed by a printing method.

In another preferred example of the method for manufacturing the second wafer level chip scale package of the present invention,
The external electrode is formed so as to project from the opening of the second insulating film so as to be able to directly contact the mounting target.

In still another preferred example of the second method for manufacturing a wafer level chip scale package according to the present invention, a step of fixing a solder ball to the external electrode through the opening of the second insulating film ( e) included.

(7) Note that the following techniques are related to the present invention, for example.

In Japanese Patent Laid-Open No. 2001-85559,
"Semiconductor device and manufacturing method thereof" are disclosed. This method is a method of manufacturing a semiconductor device at a wafer level, in which a semiconductor wafer having a plurality of chip electrodes exposed from a passivation film (final protective film) covering each chip portion is prepared, and the passivation film A plurality of wiring portions are formed on top of the chip electrodes by shifting their positions. Then, a conductive paste such as Ag, Ag-Pd, or Ag-Cu is selectively printed, or a metal film is selectively deposited or sputtered, or a binding wire is fixed to form a connection portion. And electrically connecting the wiring portion corresponding to each of the chip electrodes through the connecting portions. An insulating film is formed using photosensitive polyimide so as to cover the chip electrode, the wiring portion, and the connection portion, and the wiring portion is exposed through the opening of the insulating film. A solder ball is fixed to the exposed wiring portion through the opening of the insulating film to form an external terminal. The solder balls are formed by screen-printing a solder paste and then performing reflow.

As described above, in the method of Japanese Patent Laid-Open No. 2001-85559, the wiring portion is formed on the passivation film of the semiconductor wafer by a printing method or the like,
These wiring portions are connected to the chip electrodes via the connection portions, and solder balls are fixed to the wiring portions to form external terminals. An insulating film having an opening is formed using photosensitive polyimide so as to cover the chip electrode, the wiring portion, and the connection portion.

On the other hand, in the method for manufacturing a wafer level chip scale package according to the present invention, the rewiring film is formed by the printing method so that the rewiring conductive film corresponding to both the wiring portion and the connection portion is formed. The body is formed, and the second insulating film and the external electrode are also formed by the printing method. Therefore, the method of the present invention is clearly different from the method of Japanese Patent Laid-Open No. 2001-85559 in terms of the number of steps required and the effects obtained.

Further, Japanese Unexamined Patent Publication No. 1-114046 discloses "a method for forming Au and Ag-Pd bonding electrodes on a circuit board". This method prints a paste containing Au or Ag-Pd on a ceramic substrate.
After firing to form an electrode, a Ni or Cu layer is formed on the ceramic substrate and the electrode by an electroless plating method, and further Cu electrolytic plating is performed on the Ni or Cu layer as an electrode. To form a conductive layer. After that, the unnecessary portion is removed by etching, the IC bare chip is fixed to the removed portion, and wire bonding is applied to the electrodes arranged around the IC bare chip. Finally,
The surface is covered with a cover coat.

However, since this method mounts an IC bare chip on a ceramic substrate, it is based on an idea which is clearly different from that of the present invention relating to a chip scale package.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIGS. 1A to 1D show
FIG. 4 is a main-portion cross-sectional view showing each step of the method of manufacturing the wafer-level chip scale package of the first embodiment of the present invention with respect to one chip section.

First, a silicon wafer W having a structure as shown in FIGS. 1A and 3 is prepared. This silicon wafer W defines a predetermined number of rectangular chip portions 11 by forming a dicing region 12 in a lattice pattern on the surface of a substantially circular silicon substrate 1. A predetermined LSI is built in each of the chip portions 11.

In each chip portion 11, as clearly shown in FIG. 3, a predetermined number of aluminum electrodes 2 are formed on the surface of the silicon substrate 1. The entire surface of the silicon substrate 1 is covered with an insulating film, that is, a passivation film 3. The aluminum electrode 2 is exposed through the opening 3a provided in the passivation film 3. These aluminum electrodes 2 function as “chip electrodes” for making electrical connection with the integrated circuit in each chip portion 11, and are arranged in a peripheral region of the chip portion 11 in a frame shape at predetermined intervals.

Although not shown in the figure, it goes without saying that a diffusion region, a conductive film, an insulating film and the like necessary for forming a predetermined integrated circuit are formed inside the silicon substrate 1. Further, since a method of manufacturing such a silicon wafer W is well known, description thereof will be omitted.

Next, as shown in FIG. 1B, a silver-palladium (Ag-Pd) paste is applied on the passivation film 3 and the aluminum electrode 2 exposed from the passivation film 3.
The rewiring film 4 is obtained by selective application by a screen printing method using an appropriate mask and heating and curing at an appropriate temperature. At this time, the Ag-Pd paste is prevented from being applied to the dicing area 12. This is because, by doing so, the Ag-Pd paste does not adhere to the cutting jig (for example, a dicing saw) used in the dicing process, and as a result, deterioration of the cutting performance of the cutting jig can be suppressed. Because there is.
This screen printing process may be performed under known printing conditions.

Rewiring film 4 made of Ag-Pd paste
Are formed and arranged so as to be "rewiring conductors" for interconnecting each chip electrode 2 and the corresponding chip electrode 2, and one end of the opening 3a of the passivation film 3 is formed.
It contacts the corresponding chip electrode 2 via. The other end of the rewiring conductor formed of the rewiring film 4 is set at a position in contact with the external electrode 6 formed in a later step.

The reason why the Ag--Pd paste is used as the material for the redistribution film 4 is that the electrical connection with the aluminum electrode 2 is good. It is not preferable to use a copper (Cu) paste instead of the Ag-Pd paste. This is because the connection reliability with the aluminum electrode 2 is poor.

The thickness of the rewiring film 4, that is, the Ag-Pd paste film is determined according to the width of the rewiring conductor made of the rewiring film 4, which is required in design.

Subsequently, an insulating epoxy resin is selectively applied by a screen printing method to form a sealing film 5. At this time, in order to suppress deterioration of the cutting performance of the cutting jig for dicing, the insulating epoxy resin is also not applied to the dicing area 12. This screen printing process may also be performed under known printing conditions.

After that, the applied insulating epoxy resin is heated at an appropriate temperature to be hardened, whereby the insulating epoxy resin shown in FIG.
The sealing film 5 is formed as shown in (c). This sealing film 5
Has a plurality of openings 5a for exposing the other end of the rewiring conductor formed of the rewiring film 4 therebelow. These openings 5 a are arranged in the same grid pattern as the grid pattern of the external electrodes 6.

The insulating epoxy resin contains an appropriate amount of fine particles of silica (SiO ₂ ) as a filler. this is,
This is to reduce the coefficient of linear expansion after curing to suppress warpage as a package. The insulating epoxy resin is not applied to the dicing region 12 in order to suppress deterioration of the cutting performance of the cutting jig for dicing.

The thickness of the printed and applied insulating epoxy resin can be set to a desired value by suitably selecting the screen printing mask and the insulating epoxy resin.

The shape of the opening 5a of the insulating epoxy resin film 5 is usually circular, but the shape is not limited to this. Further, the diameter (size) of the opening 5 a is set according to the size of the external electrode 6.

Further, a copper (Cu) paste is selectively applied by a screen printing method, and then heated and cured at an appropriate temperature to form a columnar external electrode 6 as shown in FIG. 1 (d). To form. The supply amount of the Cu paste is set to an appropriate amount according to the size and the total number of the external electrodes 6. At this time, the lower end of each external electrode 6 is in contact with the other end of the conductor made of the rewiring film 4 immediately thereunder through the opening 5a of the insulating epoxy resin film 5. The upper end of each external electrode 6 is curved in a convex shape, and slightly protrudes above the surface of the insulating epoxy resin film 5. This is so that the external electrode 6 can be directly connected to the mounting target.

In this way, as shown in FIG.
The chip electrodes 2 made of aluminum, which are arranged in a frame shape inside, are converted into the external electrodes 6 rearranged in a grid shape inside the chip portion 11 as shown in FIG. as a result,
A wafer level chip size package WP in which the arrangement pitch of the chip electrodes 2 is expanded to the arrangement pitch of the external electrodes 6 can be obtained.

As the Cu paste, one that can be soldered is used. The height of the external electrode 6 (particularly, the height protruding from the surface of the insulating epoxy resin film 5) is within a range in which it can be directly soldered to a printed wiring board,
It is set to the desired value. The external electrode 6 is a silicon LSI
It has the function of absorbing the difference in the coefficient of thermal expansion between the chip and the printed wiring board, that is, the "stress relaxation function". In this package WP, since the external electrodes 6 can be directly soldered to the printed wiring board, there is an advantage that a step of forming and fixing solder balls is unnecessary.

Subsequently, the wafer level chip size package WP is cut along the dicing region 12 by a known dicing processing method, and is divided into each chip portion 11. Thus, a silicon LSI chip having a chip size package is obtained.

As described above, in the method of manufacturing the wafer level chip scale package according to the first embodiment of the present invention, the step of forming the redistribution film 4 of FIG. 1B and the step of FIG. The step of forming the insulative epoxy resin film 5 and the step of forming the external electrode 6 of FIG. 1D are all performed by the screen printing method using a predetermined paste. It can be carried out by a process and does not require expensive equipment such as a thin film forming apparatus or special technology. Therefore, the manufacturing cost of the package can be reduced.

Further, since the screen printing method is used in all of these steps, the materials used in the method,
That is, Ag-Pd paste, insulating epoxy resin, Cu
The paste is hardly wasted. Therefore, the use efficiency of the material is high.

Further, since each of the external electrodes 6 is formed in a substantially columnar shape and has a stress relaxation function, the wafer level chip size package WP manufactured by the method of the present invention.
When mounted on a printed wiring board or the like, the external electrodes 6 can be fixed directly to the electrodes of the printed wiring board or the like by soldering using a solder paste. Therefore, the mounting work is facilitated and high connection reliability is obtained.

The pitch of the aluminum electrodes (chip electrodes) 2 of each chip portion 11 of the silicon wafer W is 60 μm or less in a fine structure. Therefore, these chip electrodes 2 are mounted on the surface-mounting technology (Surface-Mounting Technolog
It is difficult to directly connect to the electrodes of the printed wiring board (not shown) using y, SMT). However, in the wafer level chip size package WP, since the pitch of the external electrodes 6 is expanded, it is possible to connect to the electrodes of the printed wiring board using SMT.

Further, since the aluminum electrode 2 on the silicon chip is made of aluminum or its alloy, normal soldering cannot be performed due to the oxide film formed on its surface, but In the level chip size package WP, the aluminum electrode 2 is used because the external electrode 6 is made of Cu or its alloy.
There is no such problem. That is, it becomes possible to connect to the electrodes of the printed wiring board using the SMT via the external electrodes 6.

Further, a rewiring film 4 which is brought into contact with the aluminum electrode 2 is formed of Ag-Pd paste,
Since the external electrode 6 that is brought into contact with the rewiring film 4 made of Ag-Pd paste is made of Cu paste, not only between the aluminum electrode 2 and the rewiring film 4, but also between the rewiring film 4 and the external electrode 6. However, there is an advantage that electrical connection becomes good.

(Second Embodiment) FIGS. 2A and 2B are
FIG. 9 is a main-portion cross-sectional view showing each step of the method of manufacturing the wafer-level chip scale package of the second embodiment of the present invention with respect to one chip section.

First, a silicon wafer W having a structure as shown in FIGS. 1A and 3 is prepared. And FIG.
As shown in (b), the passivation film 3 and the aluminum electrode 2 exposed from the passivation film 3 are selectively coated with an Ag-Pd paste by a screen printing method to form a rewiring film 4. Next, as shown in FIG. 1C, an insulating epoxy resin is selectively applied by a screen printing method to form a sealing film 5. The process up to this point is the same as in the case of the first embodiment described above.

After that, Cu paste is selectively applied by a screen printing method, and then heated and cured at an appropriate temperature to form an external electrode 6a as shown in FIG. 2 (a). At this time, the lower end of each external electrode 6a is in contact with the other end of the conductor composed of the rewiring film 4 immediately thereunder through the opening 5a of the insulating epoxy resin film 5.

Unlike the external electrode 6 of the first embodiment, the external electrode 6a of the second embodiment does not have its upper end surface protruding upward from the opening 5a of the insulating epoxy resin film 5. It is slightly lower than the surface of the opening 5a of the insulating epoxy resin film 5, and is in a concave shape. The external electrode 6a having such a shape is Cu supplied to each opening 5a.
It can be easily formed by reducing the amount of paste as compared with the case of the first embodiment.

Subsequently, the solder balls 20 formed separately are placed on the upper end surfaces of the external electrodes 6a by a known method and pressure is applied thereto, as shown in FIG. 2 (b).
The solder ball 20 is fixed to the upper end surface of each external electrode 6a.

Thus, as in the case shown in FIG. 3, the chip electrodes 2 made of aluminum, which were arranged in a frame shape inside the chip section 11, were rearranged inside the chip section 11 in a grid pattern to form the Cu paste. To the external electrode 6a (see FIG. 4). As a result, a wafer level chip scale package WPa in which the pitch of the chip electrodes 2 is expanded to the pitch of the external electrodes 6 is obtained.

Subsequently, a wafer level chip scale package WP is formed by a known dicing processing method.
a is cut along the dicing region 12 and the chip portion 11
Divide into each. Thus, an LSI chip having a chip size package is obtained.

As described above, in the method of manufacturing the wafer level chip scale package according to the second embodiment of the present invention, the same effect as that of the first embodiment can be obtained.

The solder ball 2 is attached to the external electrode 6a.
It goes without saying that the step of fixing 0 may be performed after dividing each chip portion 11 in the dicing step.

(Modification) The first and second embodiments described above are
The present invention is not limited to these embodiments because it shows examples embodying the present invention. It goes without saying that various modifications can be made without departing from the spirit of the present invention.

For example, in the first to second embodiments, the step of forming the rewiring film 4 of FIG. 1B, the step of forming the insulating epoxy resin film 5 of FIG. 1 (d)
Although all the steps of forming the external electrode 6 are performed by the screen printing method, the step of forming the redistribution film 4 may be performed by a known thin film forming method such as the sputtering method. This modification can be suitably applied when the arrangement density of the external electrodes 6 is further increased. This is because the thin film forming method such as the sputtering method can form the rewiring conductor pattern made of the rewiring film 4 with higher accuracy than the screen printing method.

In the first and second embodiments, the insulating epoxy resin is used as the sealing film (protective film) 5, but a photosensitive epoxy resin may be used instead.
In this case, instead of the screen printing method, it may be formed by exposing the photosensitive epoxy resin to light and developing it with a predetermined developing solution. That is, the sealing film 5 may be formed by patterning a photosensitive epoxy resin using a photolithography method.

[0074]

As described above, according to the first method for manufacturing a wafer level chip scale package of the present invention, it can be carried out by a simple process and expensive equipment is not required. Cost can be reduced. In addition, the use efficiency of the material is high. Further, high connection reliability can be obtained when the package is mounted.

According to the second wafer level chip scale package manufacturing method of the present invention, the manufacturing cost can be reduced and the material can be used efficiently. Further, high connection reliability can be obtained when the package is mounted.

[Brief description of drawings]

FIG. 1 is an essential part cross-sectional view showing each step of a method of manufacturing a wafer level chip scale package according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a key portion showing each step of the method of manufacturing the wafer-level chip scale package according to the second embodiment of the present invention.

FIG. 3 is a plan view of a principal part showing a mounting surface of a silicon wafer used in the method for manufacturing a wafer level chip scale package according to the first and second embodiments of the present invention.

FIG. 4 is a plan view of relevant parts showing a mounting surface of a wafer level chip scale package manufactured by the method for manufacturing a wafer level chip scale package according to the first and second embodiments of the present invention.

[Explanation of symbols]

W Silicon wafer WP, WPa Wafer level chip size package 1 Silicon substrate 2 Aluminum electrode (chip electrode) 3 Insulating film (passivation film) 4 Ag-Pd paste film 5 Epoxy resin insulating film (sealing material) 5a Epoxy resin Insulation film openings 6 and 6a External electrodes 11 Chip part 12 on silicon wafer 12 Scribe line 20 on silicon wafer Solder balls

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tsunemitsu Kouda             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company F term (reference) 5F033 HH08 HH11 HH14 PP26 VV07

Claims (11)

[Claims] 1. A method of manufacturing a chip scale package of a semiconductor device at a wafer level, comprising: (a) a semiconductor wafer having a plurality of chip parts in which a predetermined circuit is formed, A surface of each of which is covered with a first insulating film, and a plurality of chip electrodes are exposed from a plurality of openings of the first insulating film; In each case, a conductive rewiring film is selectively formed on the first insulating film by a printing method using a conductive paste, and thus the chip is provided through the plurality of openings of the first insulating film. A step of forming a plurality of rewiring conductors respectively brought into contact with the electrodes, and (c) a plurality of rewiring conductors by a printing method using an insulating paste in each of the chip parts. A second insulating film is selectively formed so as to cover the plurality of openings, and a plurality of the plurality of openings are formed through a plurality of openings of the second insulation film at positions different from the plurality of openings of the first insulation film. A step of exposing the rewiring conductor, and (d) a plurality of openings in the second insulating film by selectively forming a conductive film by a printing method using a conductive paste in each of the chip parts. And a step of forming a plurality of external electrodes in contact with the rewiring conductors via, wherein each of the external electrodes is substantially columnar and has a stress relaxation function.・ Chip scale package manufacturing method. 2. The method for manufacturing a wafer level chip scale package according to claim 1, wherein an Ag—Pd paste is used as the conductive paste for the redistribution film. 3. The method of manufacturing a wafer level chip scale package according to claim 1, wherein the external electrodes are formed of a solderable material. 4. The method of manufacturing a wafer level chip scale package according to claim 1, wherein the external electrodes are formed of Cu paste. 5. The wafer level according to claim 1, wherein the external electrode is formed so as to project from the opening of the second insulating film so as to be capable of directly contacting a mounting object.・ Chip scale package manufacturing method. 6. The wafer level chip scale according to claim 1, further comprising a step (e) of fixing a solder ball to the external electrode through the opening of the second insulating film. -Package manufacturing method. 7. A method of manufacturing a chip scale package of a semiconductor device at a wafer level, comprising: (a) a semiconductor wafer having a plurality of chip parts in which a predetermined circuit is formed, A surface of each of which is covered with a first insulating film, and a plurality of chip electrodes are exposed from a plurality of openings of the first insulating film; In each case, a conductive redistribution film is selectively formed on the first insulating film by a sputtering method so that the conductive redistribution film is brought into contact with the chip electrodes through the plurality of openings of the first insulating film. A plurality of rewiring conductors are formed, and (c) a second insulating layer is formed on each of the chip parts by a printing method using an insulating paste so as to cover the plurality of rewiring conductors. The edge film is selectively formed, and the plurality of rewiring conductors are formed through the plurality of openings of the second insulating film at positions different from the plurality of openings of the first insulating film. And (d) in each of the chip portions, by selectively forming a conductive film by a printing method using a conductive paste, the rewiring through the plurality of openings of the second insulating film. A step of forming a plurality of external electrodes in contact with the conductor for use, each of the external electrodes having a substantially columnar shape and having a stress relaxation function. Production method. 8. The method of manufacturing a wafer level chip scale package according to claim 7, wherein the external electrodes are formed of a solderable material. 9. The method of manufacturing a wafer level chip scale package according to claim 7, wherein the external electrodes are formed of Cu paste. 10. The wafer level according to claim 7, wherein the external electrode is formed so as to project from the opening of the second insulating film so as to be capable of directly contacting a mounting object.・ Chip scale package manufacturing method. 11. The wafer level according to claim 7, further comprising a step (e) of fixing a solder ball to the external electrode via the opening of the second insulating film.
Manufacturing method of chip scale package.