JP2003204248A - Moving average circuit - Google Patents

Abstract

(57) Abstract: The present invention relates to a moving average circuit that calculates a moving average of data in digital signal processing, and an object of the present invention is to provide a moving average circuit that can reduce the circuit scale. A first accumulator for accumulating input data, a delay for delaying input data, a second accumulator for accumulating output data delayed by the delay, and a first accumulator And a subtractor for subtracting the output data of the second accumulator from the output data of the second accumulator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving average circuit for calculating a moving average of data in digital signal processing.

[0002]

2. Description of the Related Art Conventionally, a moving average circuit has been frequently used in measuring instruments for the purpose of removing high frequency components of noise. As a configuration of this moving average circuit, for example, one shown in FIG. 5 is known. This moving average circuit has 8
It calculates a moving average of the data, and has a shift register 3 including eight registers 1 for delaying the input data by eight clocks. The moving average circuit also includes a first arithmetic unit 7 including four adders 5A for adding the output data of the two registers 1 in the shift register 3 and four registers 1A for storing the addition results. have. Furthermore, this moving average circuit is provided with an adder 5B that adds the output data of the two registers 1A in the first operation unit 7 and two registers 1B that store the result of the addition. It has a part 9.
Then, the moving average circuit is provided with the adder 5C for adding the output data of the two registers 1B in the second operation unit 9 and the register 1C for storing the addition result, respectively. It has a section 11. Further, this moving average circuit has a divider 13 that divides the output data from the third arithmetic unit 11 by 8 which is the number of registers 1 in the shift register 3.

In this moving average circuit, every time a clock is input to the shift register 3, the shift register 3
The data inside is updated, and the first to third arithmetic units 7, 9, 11 are updated.
The calculation result in (1) is also updated and finally divided by the divider 13 to calculate the moving average of the input data.

[0004]

However, in the moving average circuit as described above, when the number of data for moving average increases, the number of registers 1 in the shift register 3 increases, and accordingly, the adders 5A and 5B are added. , 5C and the number of registers 1A, 1B, 1C for storing the addition results of the adders 5A, 5B, 5C are increased, which causes a problem that the circuit scale is increased.

The present invention has been made in order to solve such a conventional problem, and an object thereof is to provide a moving average circuit capable of reducing the circuit scale.

[0006]

According to another aspect of the present invention, a moving average circuit includes a first cumulative addition section for cumulatively adding input data, a delay section for delaying the input data, and output data delayed by the delay section. And a subtractor for subtracting the output data of the second cumulative addition unit from the output data of the first cumulative addition unit.

A moving average circuit according to a second aspect is the moving average circuit according to the first aspect, further comprising a delay control section for selecting a number of clocks to be delayed by the delay section.

[0008]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a first embodiment (corresponding to claim 1) of a moving average circuit of the present invention.

The moving average circuit 14 of the first embodiment
Includes a cumulative addition unit 17 that is a first cumulative addition unit that cumulatively adds the input data 15S that is input for each clock, and a delay unit 19 that delays the input data 15S by n clocks. The moving average circuit 14 also includes a delay data cumulative addition unit 23, which is a second cumulative addition unit that cumulatively adds the output data 21S delayed by the delay unit 19, and a cumulative addition unit 17.
And the subtracter 29 for subtracting the output data 27S of the delay data cumulative addition unit 23 from the output data 25S of.
Furthermore, the moving average circuit 14 has a divider 35 that divides the output data 31S of the subtractor 29 by the number of clocks n delayed by the delay unit 19 and outputs moving average data 33S.

With this configuration, the output data 27S of the delayed data accumulative addition unit 23 delayed by n clocks and cumulatively added is subtracted from the output data 25S of the accumulative addition unit 17 to which all the input data 15S have been accumulatively added, and finally divided. Input data 15S divided by natural number n in the instrument 35
The moving average of is calculated. FIG. 2 is an explanatory diagram showing details of the moving average circuit 14.

As shown in the figure, the cumulative addition unit 17 has an adder 39A and a register 41A for storing the calculation result of this adder 39A. Delay data cumulative addition unit 23
Like the cumulative addition unit 17, has an adder 39B and a register 41B for storing the calculation result of this adder 39B. The delay unit 19 has eight registers 41C1 to 41Cn arranged in series.

Next, the operation of the moving average circuit 14 will be described. First, the input data 15S is input to the cumulative addition unit 17 and the delay unit 19 for each clock. In the adder 39A, the input data 15S to the cumulative addition unit 17 is added to the data stored in the register 41A when the input data 15S is input to the adder 39A. Next, this addition result is input to the register 41A and is replaced with the data stored until then. Then,
The data stored in the register 41A is output data 25 when the clock is next input to the adder 39A.
It is input to the subtractor 29 as S.

On the other hand, input data 15S to the delay unit 19
Is input to the register 41C1 and the register 41C1
The data that was in C1 is input to 41C2. Similarly, it is sequentially input to the registers 41C3 to 41Cn on the right side of the drawing,
The data in 1Cn is input to the delay data cumulative addition unit 23 as the output data 21S. Next, in the delay data cumulative addition unit 23, the same processing as the cumulative addition unit 17 is performed, and the output data 27S is input to the subtractor 29.

Then, the subtracter 29 obtains the difference between the output data 25S and the output data 27S. Finally,
The output data 31S of the subtractor 29 is divided by the natural number n in the divider 35 to calculate moving average data 33S. In the moving average circuit 14 of the first embodiment, when the number of shift registers 41C1 to 41Cn is increased / decreased, the moving average number is increased / decreased, so that the moving average can be calculated with a simple configuration. The circuit scale can be reduced.

In addition, in the moving average circuit 14 of the first embodiment, when the moving average number is increased, the delay unit 1
9 serially arranged shift registers 41C1 to 41Cn
The number of shift registers 41Ck-
If 41 Cn (2 ≦ k ≦ n) is added, it is possible to easily cope with the increase in the number of moving averages. On the other hand, when the number of moving averages is reduced, the number of shift registers 41C1 to 41Cn arranged in series in the delay unit 19 may be reduced. Therefore, some of the shift registers 41C1 to 41Cn are detachably configured. By doing so, it is possible to easily cope with the decrease in the number of moving averages.

(Second Embodiment) FIG. 3 is a block diagram showing a second embodiment (corresponding to claim 2) of the moving average circuit of the present invention. In addition, in this 2nd Embodiment, the same code | symbol is attached | subjected to the member same as 1st Embodiment, and detailed description is abbreviate | omitted.

The moving average circuit 43 of the second embodiment is provided with a delay control section 45 for selecting the number of clocks delayed by the delay section 19 from a natural number of n or less. Then, the moving average number signal 47S is input to the delay control unit 45 and the divider 35. Next, the operation of the delay control unit 45 will be described with reference to FIG. In the moving average circuit 43 of the second embodiment, first, the moving average number signal 47S for instructing how many clocks ago the input data 15S is averaged is transmitted to the delay controller 45 and the divider 35. Entered in.

Next, the divider 35 outputs the output data 3 from the subtractor 29 based on the moving average number signal 47S.
1S is divided by a natural number m (m ≦ n). On the other hand, the delay control unit 45 connects with the delay unit 19 so that the registers 41C1 to 41Cm are activated from the registers 41C1 to 41Cn based on the moving average number signal 47S. Also in the moving average circuit 43 of the second embodiment, the same effect as that of the first embodiment can be obtained.

Since the moving average circuit 43 of the second embodiment is provided with the delay control unit 45 for selecting the number of clocks to be delayed by the delay unit 19 from a natural number of n or less, the delay control unit is provided. Since a predetermined number of moving averages can be calculated only by inputting the moving average number signal 47S to 45 and the divider 35, the moving average number can be easily changed.

[0020]

As described above, in the moving average circuit of the present invention, the moving average number is increased or decreased by increasing or decreasing only the number of shift registers in the delay section. Therefore, the moving average can be calculated with a simple configuration. In addition, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a moving average circuit of the present invention.

FIG. 2 is an explanatory diagram showing details of the first embodiment of the moving average circuit of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the moving average circuit of the present invention.

FIG. 4 is an explanatory diagram showing details of a second embodiment of the moving average circuit of the present invention.

FIG. 5 is a block diagram showing an embodiment of a conventional moving average circuit.

[Explanation of symbols]

15S input data 17 Cumulative adder 19 Delay section 21S, 25S, 27S, 31S output data 23 Delayed data cumulative adder 29 Subtractor 35 divider 45 Delay control unit

Claims (2)

[Claims] 1. A first cumulative addition unit for cumulatively adding input data, a delay unit for delaying the input data, and a second cumulative addition for output data delayed by the delay unit.
A moving average circuit comprising: a cumulative addition unit; and a subtractor that subtracts the output data of the second cumulative addition unit from the output data of the first cumulative addition unit. 2. The moving average circuit according to claim 1, further comprising a delay control unit for selecting the number of clocks to be delayed by the delay unit.