JP2003299387A - Variable speed controller - Google Patents

Abstract

An object of the present invention is to correct an output voltage in accordance with a timing of increasing or decreasing a DC bus voltage in a variable speed control device. SOLUTION: A voltage ripple estimating means 2 estimates a DC bus voltage at the time when a voltage is actually output by using a periodicity of a DC bus voltage ripple fluctuation in a variable speed control device. The DC bus voltage estimation value estimated based on the DC bus voltage detection value detected by the detection means 46 is output to the output voltage calculation means 47 as the value of the DC bus voltage. The output voltage calculation means 47 calculates the output voltage based on the output frequency output from the output frequency calculation means 45, and corrects the output voltage based on the estimated DC bus voltage output from the voltage ripple estimation means 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable speed control device for driving an electric motor at a variable speed.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a configuration of a conventional variable speed control device. In the figure, 30 is an inverter main circuit, 3
1 is a converter unit for converting the AC power supply 34 into DC power,
32 is a capacitor for smoothing a DC voltage, 33 is a transistor and a diode, and an inverter unit for converting DC power into AC power of variable frequency and voltage.
Reference numeral 5 denotes an electric motor such as an induction motor that is driven at a variable speed as a load.

Reference numeral 40 is an inverter control circuit for controlling the on / off of the transistors of the inverter unit 33.
Further, reference numeral 41 is a memory as a storage means for storing various data such as a frequency command value, acceleration / deceleration time or an output frequency / output voltage relational expression. 42 is a memory communication unit for reading and writing data in the memory 41,
43 is a frequency command value input means for detecting a frequency command value input from the outside, and 44 is an output frequency from the frequency command value detected by the frequency command value input means 43 and the acceleration / deceleration time stored in the memory 41 in advance. Output frequency calculating means for calculating, 45 is an output phase calculating means for calculating a phase angle from the output frequency calculated by the output frequency calculating means 44 according to the processing time of software.

Reference numeral 46 is a DC bus voltage detecting means for detecting the voltage across the capacitor 32. Further, 47 is an output voltage calculation means for inputting the output frequency calculated by the output frequency calculation means 44 and calculating the output voltage based on the relational expression of output frequency / output voltage stored in the memory 41 in advance. The output voltage calculation means 47 corrects the output voltage according to the value of the DC bus voltage detected by the DC bus voltage detection means 46 at the time of calculating the output voltage.

Further, 48 is output to each of the U phase, V phase and W phase which are the outputs of the variable speed control device from the phase obtained by the output phase calculating means 45 and the output voltage calculated by the output voltage calculating means 47. Three-phase voltage generating means for generating three-phase voltage,
Reference numeral 49 is a PWM waveform output means for creating a switching signal for controlling ON / OFF of the transistor of the inverter section 33 from the three-phase voltage generated by the three-phase voltage generation means 48 and outputting the switching signal to the inverter section 33.

Further, 50 is a frequency command value input means 43,
It is a microcomputer (hereinafter referred to as a CPU) having an output frequency calculation means 44, an output phase calculation means 45, an output voltage calculation means 47 and a three-phase voltage generation means 48.

Next, the operation of the conventional variable speed control device will be described. When the voltage is supplied to the variable speed control device, the frequency command value input means 43 sends information such as the frequency command value obtained from the memory 41 via the memory communication means 42 to the CPU 50.
The data is converted into the data format of the frequency set value handled internally and output to the output frequency calculation means 44. The output frequency calculation means 44 determines whether during acceleration, at constant speed, from the frequency command value output from the frequency command value input means 43 and the information such as the acceleration / deceleration time obtained from the memory 41 via the memory communication means 42. The current output frequency is calculated according to the internal state such as during deceleration, and the output phase calculation means 45 and the output voltage calculation means 47 are calculated.
Output to. The output phase calculation means 45 advances the output phase according to the calculation cycle of the CPU 50 based on the output frequency output from the output frequency calculation means 44.

Further, the DC bus voltage detecting means 46 always keeps the DC bus voltage (capacitor 32) of the inverter main circuit 30.
Of the DC bus voltage is detected.
It is converted into a voltage data format handled inside the PU 50 and output to the output voltage calculation means 47. Output voltage calculation means 47
Calculates the output voltage corresponding to the output frequency from the output frequency output from the output frequency calculation means 45 using the output frequency / output voltage relational expression obtained from the memory 41 via the memory communication means 42. However, at this time, the value of the DC bus voltage detected by the DC bus voltage detecting means 47 is compared with the reference voltage, and if the value of the DC bus voltage is large, the output voltage is reduced in accordance with the ratio. If the value of the bus voltage is small, the output voltage is increased according to the ratio. The correction of the output voltage based on the value of the DC bus voltage described above is performed in order to avoid the phenomenon that the output current is disturbed in synchronization with the voltage ripple of the periodic DC bus voltage that occurs when used in a single-phase voltage power supply. By correcting the output voltage according to the increase / decrease in the DC bus voltage, the actually output three-phase voltage is always kept constant.

From the output voltage calculated by the output voltage calculation means 47 by the three-phase voltage generation means 48 and the current output phase calculated by the output phase calculation means 45, three-phase voltages of U phase, V phase and W phase are obtained. To generate. The PWM waveform output means 49 compares the three-phase voltage generated by the three-phase voltage generation means 48 with a triangular wave that is a carrier wave respectively, and outputs a three-phase switching signal for controlling ON / OFF of the transistor of the inverter section 33 to the inverter section. To 33.

In the above process, the AC motor having the variable frequency and the variable voltage converted by the inverter unit 33 drives the load electric motor at a variable speed.

[0011]

In the conventional variable speed control device as described above, the output frequency corresponding to the output frequency is calculated from the output frequency calculated by the output frequency calculating means 44 by the relational expression of output frequency / output voltage. After calculating the voltage, the output voltage was corrected by the value of the DC bus voltage detected by the DC bus voltage detecting means 46, but the DC bus voltage was detected due to the restrictions on S / W and H / W. There is a problem in that it takes time to be actually reflected in the output of the inverter unit 33, and the actual change in the DC bus voltage cannot be efficiently reflected in the correction.

The present invention has been made to solve the above problems, and an object thereof is to correct the output voltage in accordance with the timing of the increase / decrease of the DC bus voltage in the variable speed control device.

[0013]

In a variable speed control device according to the present invention, a converter section for converting an AC power supply into a DC power, a capacitor for smoothing a DC voltage, a transistor and a diode are provided. An inverter unit for converting AC power of variable frequency and variable voltage, a DC bus voltage detecting means for detecting the voltage across the capacitor, an output voltage based on the output frequency, and the DC bus voltage detecting means for detecting the output voltage. The output voltage calculating means for correcting the output voltage based on the detected DC bus voltage and the PWM waveform output means for on / off controlling the transistor of the inverter portion based on the output voltage are provided, and the motor is controlled at a variable speed. In the variable speed control device to drive,
The output voltage calculating means includes a voltage ripple estimating means for estimating a DC bus voltage at the time of ON / OFF controlling the transistor of the inverter unit based on the detected value of the DC bus voltage detected by the DC bus voltage detecting means. The output voltage is calculated based on the output frequency, and the output voltage is corrected by the DC bus voltage estimated value output by the voltage ripple estimating means.

Further, the voltage ripple estimating means 2 detects when the DC bus voltage detected value becomes maximum in the ripple fluctuation of the DC bus voltage detected value detected by the DC bus voltage detecting means, or when the DC bus voltage detected value is The DC bus voltage at the time when the transistor of the inverter section is controlled to be turned on / off is estimated by using the time point when it becomes the minimum as the reference point of the waveform having periodicity.

Further, the voltage ripple estimating means 2 is
When data is not stored in the entire area of the DC bus voltage detection value storage memory for storing the DC bus voltage detection value detected by the DC bus voltage detection means, the entire area of the DC bus voltage detection value storage memory is stored. If the data is saved, but two cycles of DC bus voltage ripple fluctuation have not elapsed, two cycles of DC bus voltage ripple fluctuation have passed, but the previous value DC bus voltage maximum value and previous value DC bus If the difference from the minimum voltage value is less than or equal to the first predetermined value, and if the difference between the previous value DC bus voltage maximum value and the previous value DC bus voltage minimum value is greater than or equal to the first predetermined value, this time DC bus voltage When the difference between the maximum value and the previous maximum value of the DC bus voltage is equal to or more than the second predetermined value, the average value of the DC bus voltage is determined as the DC bus voltage at the time when the transistor of the inverter unit is turned on / off. It is those that were in use.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing the configuration of a variable speed control device according to a first embodiment of the present invention. In the figure, 30-35, 41, 42-4
9 is the same as that in FIG. 7, and the description thereof is omitted. Also,
1 is an inverter control circuit, 2 is a DC bus voltage detecting means 4
It is a voltage ripple estimating means for predicting the fluctuation of the DC bus voltage by inputting the DC bus voltage data detected in 6. Further, 3 is voltage ripple estimating means 2, frequency command value input means 43, output frequency calculating means 44, output phase calculating means 4
5, output voltage calculation means 47 and three-phase voltage generation means 48
Microcomputer having (hereinafter referred to as CPU)
Is.

Next, the operation of the variable speed control device according to the first embodiment will be described. When a voltage is supplied to the variable speed control device, the frequency command value input means 43 converts the information such as the frequency command value obtained from the memory 41 via the memory communication means 42 into the data format of the frequency set value handled in the CPU 3. And outputs it to the output frequency calculation means 44. The output frequency calculation means 44 is accelerating based on the frequency command value output from the frequency command value input means 43 and the information such as the acceleration / deceleration time obtained from the memory 41 via the memory communication means 42.
The present output frequency is calculated according to the internal state such as constant speed, deceleration, etc., and output to the output phase calculation means 45 and the output voltage calculation means 47. The output phase calculation means 45 calculates the CP based on the output frequency output from the output frequency calculation means 44.
The output phase is advanced according to the calculation cycle of U3.

Further, the DC bus voltage detecting means 46 is always provided with a DC bus voltage (capacitor 32) of the inverter main circuit 30.
Of the DC bus voltage is detected.
The data is converted into a format of voltage data handled inside the PU 3, and is output to the voltage ripple estimating means 2. The voltage ripple estimating means 2 estimates the DC bus voltage at the time when the voltage is actually output by utilizing the periodicity of the DC bus voltage ripple fluctuation in the variable speed control device. The estimated value of the DC bus voltage estimated based on the detected detected value of the DC bus voltage is output to the output voltage calculation means 47 as the value of the DC bus voltage.

The output voltage calculating means 47 uses the output frequency / output voltage relational expression obtained from the memory 41 via the memory communicating means 42 from the output frequency output from the output frequency calculating means 45. Calculate the output voltage corresponding to. When calculating the output voltage, the value of the DC bus voltage output from the voltage ripple estimating means 2 is compared with the reference voltage, and if the value of the DC bus voltage is large, the output voltage to the motor is reduced according to the ratio. If the value of the DC bus voltage is small, the output voltage is increased according to the ratio.

From the output voltage calculated by the output voltage calculation means 47 and the current output phase calculated by the output phase calculation means 45, the three-phase voltage generation means 48 calculates three-phase voltages of U phase, V phase and W phase. To generate. The PWM waveform output means 49 compares the three-phase voltage generated by the three-phase voltage generation means 48 with a triangular wave that is a carrier wave respectively, and outputs a three-phase switching signal for controlling ON / OFF of the transistor of the inverter section 33 to the inverter section. To 33.

In the above process, the electric motor, which is a load, is driven at a variable speed by the variable frequency and variable voltage AC power converted by the inverter unit 33.

FIGS. 2 and 3 utilize the periodicity of the DC ripple voltage ripple fluctuation in the voltage ripple estimating means 2 of the variable speed control apparatus according to the first embodiment, and the DC bus at the time when the voltage is actually output. It is a flowchart which estimates a voltage. FIG. 2 is a process for obtaining a memory address (reference point for DC bus voltage estimation) that maximizes the DC bus voltage within one ripple cycle, and FIG. 3 is an estimation of the DC bus voltage using the memory address obtained in FIG. This is the process to be performed. The voltage ripple estimating means 2 uses a time point when the DC bus voltage becomes maximum in the DC bus voltage ripple fluctuation as a reference point of a waveform having periodicity. For this reason, a memory (not shown) inside the CPU that stores the detected value of the DC bus voltage (hereinafter, referred to as a memory for storing the detected value of the DC bus voltage) is a DC of each DC bus voltage ripple fluctuation cycle in the variable speed control device. The memory size is such that three or more maximum bus voltage values can be stored.

Further, FIG. 4 shows the detected value V of the DC bus voltage at this time.
It is a figure which shows the relationship between now and DC bus voltage minimum detection value Vmin, (a) is a case of Vnow <Vmin, (b) is a case of Vnow> Vmin. Further, FIG. 5 is a diagram showing the relationship between the DC bus voltage detection value Vnow and the DC bus voltage detection maximum value Vmax of this time, and (a) is Vnow> Vm.
In the case of ax, (b) is the case of Vnow <Vmax.

FIG. 6 illustrates the relationship between the detected value of the DC bus voltage, the memory for storing the detected value of the DC bus voltage, and the estimated value of the DC bus voltage in the estimation of the DC bus voltage in the variable speed control apparatus according to the first embodiment of the present invention. FIG. DC bus voltage estimated value Vne estimated at the time of calculating the output voltage
xt is a DC bus voltage value at the memory address N + T (a memory address advanced from the memory address N at the time of detecting the DC bus voltage by the memory address T), and in FIG. 6, the number of prereads T (output voltage from the time when the DC bus voltage is detected) An example is shown in which the period (until the time of calculation) is T = 3.

The voltage ripple estimating means 2 of the variable speed control apparatus according to the first embodiment uses the current DC bus voltage detected value Vn.
The relative address position M between the memory address N storing ow and the current maximum value address Nmax in which the maximum DC bus voltage Vmax_tmp in this cycle is stored.
(M = N_Nmax) is calculated, and the DC bus voltage detection stored in the memory address Nmax_pre + M + T is performed using the previous temporary maximum value address Nmax_pre in which the DC bus voltage maximum value Vmax_pre in the previous cycle is stored. Value is the memory address N +
The estimated value of DC bus voltage at T is Vnext.

The voltage ripple estimating means 2 of the variable speed control device according to the first embodiment utilizes the periodicity of the DC bus voltage ripple fluctuation in the variable speed control device, and the DC bus bar at the time when the voltage is actually output. The voltage is estimated, and the time when the DC bus voltage becomes maximum in the DC bus voltage ripple fluctuation is used as the reference point of the periodic waveform. For this reason, the current maximum value address Nmax and the previous temporary maximum value address Nmax_pre are required for the DC bus voltage estimation. Therefore, as the DC bus voltage detected value storage memory for storing the DC bus voltage detected value, the variable speed control device is used. It is necessary to have a size capable of storing three or more maximum values in the fluctuation of the DC bus voltage ripple in. Since the determination of the maximum value is the memory address A2 next to the memory address A1 storing the maximum value, in order to secure the current maximum value address Nmax and the previous temporary maximum value address Nmax_pre, as shown in FIG. , A size that can store three maximum values is required. Therefore, in order to store the detected value of the DC busbar voltage for two cycles of the voltage ripple including the maximum value of the past two times the maximum value of the DC busbar voltage Vmax_tmp in the current cycle and the maximum value of the DC busbar voltage Vmax_pre in the previous cycle. The required number of memories + the number required to store two memories are required. Further, as the memory for storing the detected value of the DC bus voltage, a ring buffer type memory in which one old data is erased when one new data is stored is used.

The process of estimating the DC bus voltage of the voltage ripple estimating means 2 will be described with reference to FIGS. First, a procedure for obtaining a memory address that maximizes the DC bus voltage within one ripple period will be described with reference to FIGS. 2, 4, and 5. However, the DC bus voltage state flag is set to rising during the initial processing when the power is turned on, and the DC bus voltage detection maximum value Vmax = 0 and the DC bus voltage detection minimum value Vmin = 0.

In step S1, the DC bus voltage detecting means 4
The DC bus voltage detection value detected for each sampling in 6,
The current detection value Vnow is stored in the memory address of the DC bus voltage detection value storage memory indicated by the counter N.
In step S2, it is determined by the DC bus voltage status flag whether the fluctuation of the DC bus voltage is rising or falling. If the fluctuation of the DC bus voltage is falling, the process proceeds to step S3, and the fluctuation of the DC bus voltage is detected. If it is rising, the process proceeds to step S6. If the DC bus voltage status flag is falling, it is determined whether the DC bus voltage has reached the minimum.If the DC bus voltage status flag is rising, it is determined whether the DC bus voltage has reached the maximum. Make a decision.

If the DC bus voltage state flag is falling, the present detected value Vnow and the minimum value Vmin are compared in step S3, and the present detected value Vnow is the minimum value Vm.
If it is less than in (FIG. 4A), step S4
Then, the present detected value Vnow is saved as the minimum value Vmin (the minimum value Vmin as the comparison data is updated). As a result of comparison in step S3, the present detected value Vnow is the minimum value Vm.
If it is greater than or equal to in (FIG. 4B), the current minimum value Vm
Judge in as the minimum DC bus voltage ripple,
In step S5, the DC bus voltage state flag is switched to rising, the maximum value Vmax is cleared to 0 in preparation for the maximum value detection from the next detection, and the current minimum value Vmi is set.
Save n as the previous minimum value Vmin_pre.

If the DC bus voltage status flag is rising in step S2, then the present detected value Vnow is compared with the maximum value Vmax in step S6. In step S6, the current detection value Vnow and the maximum value Vmax are compared, and if the current detection value Vnow exceeds the maximum value Vmax (FIG. 5A), the current detection value V is detected in step S7.
The value now is saved as the maximum value Vmax (the maximum value Vmax as the comparison data is updated), and the memory address N is saved as the temporary maximum value address Nmax_tmp. In the comparison in step S6, the current detected value Vno
If w is less than or equal to the maximum value Vmax (FIG. 5 (b)), it is determined that the current maximum value Vmax is the maximum of the DC bus voltage ripple, and in step S8, the maximum value of the DC bus voltage so far is The stored memory address Nmax is saved as the previous temporary maximum value address Nmax_pre, and the memory address where the maximum value is saved (temporary maximum value address created one time before) Nmax_tmp is saved as the current maximum value address Nmax. . Further, the DC bus voltage state flag is set to the descending state, and the maximum value Vmax is set to the minimum value Vmin in preparation for the minimum value detection from the next detection.

Next, referring to FIGS. 3 and 6, the maximum value address Nmax and the previous temporary maximum value address Nmax_pre
The procedure for performing DC bus voltage ripple estimation will be described using. Suppose that the DC bus voltage is detected T times during the period from the detection of the DC bus voltage to the actual output of the voltage. When estimating the DC bus voltage, T times are calculated from the current detection time of the DC bus voltage T times. It is necessary to estimate the DC bus voltage that will be detected later. Further, the estimation of the DC bus voltage in the voltage ripple estimating means 2 utilizes the periodicity of the DC bus voltage ripple fluctuation in the variable speed control device, and in FIG. 6, the point where the DC bus voltage becomes maximum (maximum value Address Nmax, previous maximum value address Nma
x_pre) is used as a reference point of the DC bus voltage ripple period, and an example of estimating the DC bus voltage at the time when the voltage is actually output has been shown.

In step S11, whether the data is stored in the entire area of the DC bus voltage detected value storage memory, or after the data is stored in the entire area of the DC bus voltage detected value storage memory, the DC bus voltage ripple fluctuation is detected. Check whether 2 cycles have passed. If it is determined that the data is not stored in the entire area of the DC bus voltage detection value storage memory, or if it is determined that two cycles of the DC bus voltage ripple fluctuation have not elapsed, the process proceeds to step S12 and detection is performed. The average value Vdc_ave of the DC bus voltage is calculated and is output as the DC bus voltage Vdc to the output voltage calculation means 47.
The average value Vdc_ave of the DC bus voltage is set, and the process jumps to step S18.

If it is determined in step S11 that the data has been stored in the entire area of the memory for storing the detected value of the DC bus voltage, and two cycles of the fluctuation of the DC bus voltage ripple have elapsed, then in step S13. , It is determined whether the difference between the previous value DC bus voltage maximum value Vmax_pre stored in the previous maximum value address Nmax_pre and the previous value DC bus voltage minimum value Vmin_pre exceeds the first predetermined value α. | Vmax_pre-Vmin
If _pre | ≦ α, it is determined that there is not enough voltage ripple to perform the estimated correction, and the process jumps to step S12.

Also, | Vmax_pre-Vmi
If n_pre |> α, it is determined that there is a change in the DC bus and that the estimated correction is necessary, and then step S14.
Then, the detected value of the DC bus voltage stored in the maximum value address Nmax this time (hereinafter, the maximum value of the DC bus voltage maximum value Vma this time).
x_tmp) and the previous maximum value address Nmax-p
It is determined whether the difference between the detected value of the DC bus voltage stored in re (hereinafter, referred to as the previous maximum DC bus voltage Vmax_pre) is the second predetermined value β or less. | Vmax
If _tmp−Vmax_pre |> β, it is determined that there is no voltage ripple enough for the estimation correction and there is no periodicity, and the process jumps to step S12.

Also, | Vmax_tmp-Vma
When x_pre | ≦ β, the DC bus voltage estimation process of steps S15 to S17 is executed.

In step S15, the relative address position M from the current maximum value address Nmax of the DC bus voltage of the memory address N for storing the current detected value of the DC bus voltage.
Is calculated by the following formula. M = N-Nmax

In step S16, the estimated value Vnext of the DC bus voltage after the number of prereads T from the current detection time of the DC bus voltage is calculated by using the periodicity of the DC bus voltage ripple to the previous maximum value address Nmax-pre + relative position M.
The DC bus voltage value is estimated to be approximately the same as the detected DC bus voltage value stored in the memory address of + prefetch count T. In step S17, the estimated value of DC bus voltage Vnext is set as the DC bus voltage Vdc output to the output voltage calculation means 47, and the process proceeds to step S18.

In step S18, the memory address N is counted up. N ← N + 1

The voltage ripple estimating means 2 of the variable speed control apparatus according to the first embodiment estimates the DC bus voltage at the time when the voltage is actually output by utilizing the periodicity of the DC bus voltage ripple fluctuation. Under the following conditions, it is assumed that the periodicity of the DC bus voltage ripple fluctuation, which is a premise for estimating the DC bus voltage, is not satisfied, and step S1
The output voltage is corrected using the average value of the DC bus voltage without executing the DC bus voltage estimation processing of steps 5 to S17. a. Confirm the storage of periodicity data of DC bus voltage ripple fluctuation used for DC bus voltage estimation after the DC bus voltage rise period during capacitor charging at power-on and all areas of the memory for storing the detected DC bus voltage. If it is determined that the data has not been stored in 1., or if it has been determined that two cycles of the DC bus voltage ripple fluctuation have not elapsed, it is determined that the data for estimating the DC bus voltage is insufficient. b. When the difference between the maximum value and the minimum value of the DC bus voltage is small, it is determined that the voltage ripple does not require the estimated correction. c. If the difference between the maximum value of the DC bus voltage this time and the maximum value of the previous DC bus voltage is large, it is determined that there is no periodicity.

In the above description, the voltage ripple estimating means 2 shows an example in which the time point when the DC bus voltage becomes maximum in the DC bus voltage ripple fluctuation is used as the reference point of the periodic waveform. The time point when the DC bus voltage becomes minimum may be used as the reference point of the periodic waveform.

Also, an example is shown in which the number of prereads T (the period from the time when the DC bus voltage is detected to the time when the output voltage is calculated) is T = 3, but it is set as appropriate in correspondence with S / W and H / W. And

[0042]

Since the present invention is constructed as described above, it has the following effects.

In the variable speed control device according to the present invention, a converter section for converting an AC power supply into a DC power, a capacitor for smoothing the DC voltage, a transistor and a diode are provided, and the DC power is converted into a variable frequency and a variable voltage. An inverter unit for converting into AC power, a DC bus voltage detecting means for detecting the voltage across the capacitor, and an output voltage calculated based on the output frequency, and a DC bus voltage detection value detected by the DC bus voltage detecting means. And a PWM waveform output means for ON / OFF controlling the transistor of the inverter unit based on the output voltage, and a variable speed control device for driving the electric motor at a variable speed. In the above, based on the detected value of the DC bus voltage detected by the DC bus voltage detection means, the transformer of the inverter unit is The output voltage calculation means calculates the output voltage based on the output frequency, and the DC ripple output means outputs the DC voltage output from the voltage ripple estimation means. Since the output voltage is corrected based on the estimated value of the bus voltage, it is possible to obtain the variable speed control device that corrects the output voltage in accordance with the increase / decrease timing of the DC bus voltage.

Further, the voltage ripple estimating means 2 detects when the DC bus voltage detected value becomes maximum in the ripple fluctuation of the DC bus voltage detected value detected by the DC bus voltage detecting means, or when the DC bus voltage detected value is Since the DC bus voltage at the time when the transistor of the inverter section is turned on / off is estimated by using the point of time when it becomes the minimum as the reference point of the periodic waveform, the transistor of the inverter section is turned on / off. The DC bus voltage estimation process at the time of control can be easily performed.

Further, the voltage ripple estimating means 2 is
When data is not stored in the entire area of the DC bus voltage detection value storage memory for storing the DC bus voltage detection value detected by the DC bus voltage detection means, the entire area of the DC bus voltage detection value storage memory is stored. If the data is saved, but two cycles of DC bus voltage ripple fluctuation have not elapsed, two cycles of DC bus voltage ripple fluctuation have passed, but the previous value DC bus voltage maximum value and previous value DC bus If the difference from the minimum voltage value is less than or equal to the first predetermined value, and if the difference between the previous value DC bus voltage maximum value and the previous value DC bus voltage minimum value is greater than or equal to the first predetermined value, this time DC bus voltage When the difference between the maximum value and the previous maximum value of the DC bus voltage is equal to or more than the second predetermined value, the average value of the DC bus voltage is determined as the DC bus voltage at the time when the transistor of the inverter unit is turned on / off. Since to use, estimation processing of the DC bus voltage at the time of ON / OFF control of the transistors of the inverter can be stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a variable speed control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure for estimating a DC bus voltage in the variable speed control device according to the first embodiment of the present invention, in which a memory address (DC bus voltage estimation of a DC bus voltage estimation in which a DC bus voltage within one ripple period is maximized) is maximized. This shows the procedure for obtaining the reference point).

FIG. 3 is a flowchart showing a procedure for estimating a DC bus voltage in the variable speed control device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an updated state of the present minimum value Vmin when the DC bus voltage is decreased in the DC bus voltage estimation in the variable speed control device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating an updated state of the current maximum value Vmax when the DC bus voltage rises in the DC bus voltage estimation in the variable speed control device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship between a DC bus voltage detected value, a DC bus voltage detected value storage memory, and a DC bus voltage estimated value in DC bus voltage estimation in the variable speed control device according to the first embodiment of the present invention. is there.

FIG. 7 is a diagram showing a configuration of a conventional variable speed control device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 inverter control circuit, 2 voltage ripple estimation means, 3 CPU, 30 inverter main circuit, 31
Converter part, 32 capacitor, 33 inverter part, 35 electric motor, 40 inverter control circuit,
41 memory, 42 memory communication means, 43 frequency command value input means, 44 output frequency calculation means,
45 output phase calculation means, 46 DC bus voltage detection means, 47 output voltage calculation means, 48 three-phase voltage generation means, 49 PWM waveform output means, 50 CPU,
α first predetermined value, β second predetermined value, Vnow
Current DC bus voltage detection value, Vmin DC bus voltage minimum detection value, Vmax DC bus voltage maximum detection value, V
Next Estimated DC bus voltage at the time of calculating the output voltage, Vmax_tmp Maximum DC bus voltage in this cycle, Vmax_pre Maximum DC bus voltage in the previous cycle, Vnext Estimated DC bus voltage at memory address N + T, Vmin
_Pre Previous minimum value, Vdc_ave Average value of DC bus voltage detected, N Current DC bus voltage detection value V
memory address for storing now, T memory address, Nmax current maximum value in which the maximum value Vmax_tmp of the DC bus voltage in the current cycle is stored, M
(M = N_Nmax) Current DC bus voltage detection value Vn
a relative address position between the memory address N storing ow and the current maximum value address Nmax in which the maximum value Vmax_tmp of the DC bus voltage in this cycle is stored,
Nmax_pre The previous temporary maximum value address in which the maximum value Vmax_pre of the DC bus voltage in the previous cycle is stored, Nmax_tmp The temporary maximum value address.

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Claims (3)

[Claims] 1. A converter unit for converting an AC power supply into DC power, a capacitor for smoothing DC voltage, an inverter unit configured by transistors and diodes for converting DC power into AC power of variable frequency and voltage. DC bus voltage detection means for detecting the voltage across the capacitor, and calculating the output voltage based on the output frequency,
An output voltage calculation means for correcting the output voltage by the DC bus voltage detection value detected by the DC bus voltage detection means,
PWM waveform output means for ON / OFF controlling the transistor of the inverter section based on this output voltage, in a variable speed control device for driving the electric motor at a variable speed, in the DC bus voltage detecting means, the DC bus The output voltage calculating means calculates the output voltage based on the output frequency, the voltage ripple estimating means for estimating the DC bus voltage at the time of ON / OFF control of the transistor of the inverter section based on the detected voltage value. In addition, the variable speed control device is characterized in that the output voltage is corrected by the DC bus voltage estimated value output by the voltage ripple estimating means. 2. The voltage ripple estimating means is the time when the detected value of the DC bus voltage becomes maximum in the ripple fluctuation of the detected value of the DC bus voltage detected by the DC bus voltage detection means, or the detected value of the DC bus voltage is minimum. When
The DC bus voltage at the time when the transistor of the inverter section is turned on / off is estimated as a reference point of a waveform having periodicity.
Variable speed control device described. 3. The voltage ripple estimating means, when data is not stored in the entire area of the DC bus voltage detection value storage memory for storing the DC bus voltage detection value detected by the DC bus voltage detecting means, Although the data is stored in all areas of the memory for storing the detected value of the DC bus voltage, if two cycles of the ripple fluctuation of the DC bus voltage have not passed, two cycles of the ripple fluctuation of the DC bus voltage have passed, The difference between the previous value DC bus voltage maximum value and the previous value DC bus voltage minimum value is less than or equal to the first predetermined value, and the difference between the previous value DC bus voltage maximum value and the previous value DC bus voltage minimum value is first. However, if the difference between the current DC bus voltage maximum value and the previous DC bus voltage maximum value is a second predetermined value or more, it is only possible to turn on / off the transistor of the inverter unit at the time. 3. The variable speed control device according to claim 1, wherein an average value of the DC bus voltage is used as the DC bus voltage.