JP2003298072A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a PiN diode having improved reverse recovery characteristics and improved withstand capability during reverse recovery. In a PiN diode, an N- base layer is provided.
1, a P-emitter layer 3 formed on the first main surface of the N- base layer, a P-emitter layer 2 formed on the second main surface of the N- base layer, and an N-base It comprises an N-type pillar layer 6 selectively formed in the layer, and a P-type pillar layer 7 formed in the N- base layer in contact with the N- base layer and the N-type pillar layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a rectifying function, and more particularly, to a structure of a high breakdown voltage diode used for controlling a large amount of electric power, which is used for an inverter circuit for controlling a large motor, a switching power source, etc. It is applied to a PiN diode, a Schottky barrier diode (SBD) and the like.

[0002]

2. Description of the Related Art An inverter circuit for controlling a large motor uses a combination of a switching element such as a GTO and a flywheel diode composed of a high breakdown voltage diode.

FIG. 31 schematically shows a conventional motor control inverter circuit.

In this circuit, S is a switching element, L is a load, D is a flywheel diode,
A high voltage diode is used.

In the above inverter circuit, when the switching element S is turned on and a current is passed through the load L and then the switching element S is turned off, the current flowing through the load L begins to flow back in the loop 104 shown in the figure, and is fed to the diode D. Forward current flows.

After that, when the switching element S is turned on again, the diode D tries to turn off because a reverse voltage is applied. During the reverse recovery operation of the diode D, many carriers such as electrons and holes are accumulated inside the diode D, so that the diode D cannot be turned off immediately, and a large reverse current instantaneously flows through the diode D.
After that, when the accumulated carriers are completely discharged, the diode D
Is turned off.

FIG. 32 shows an example of a current waveform during the reverse recovery operation of the diode D.

FIG. 33A shows a diode D in FIG.
FIG. 9 is a cross-sectional view schematically showing a conventional structure of a high breakdown voltage and high speed PiN diode used as a device.

In FIG. 33 (a), 101 is a low impurity concentration n.
Type semiconductor substrate (N-base layer), a P anode diffusion layer (p emitter layer) 102 is formed on the front surface thereof, and an N cathode diffusion layer (N emitter layer) 103 is formed on the back surface thereof.

An anode electrode 104 is formed as a first main electrode on the surface of the P anode layer 2, and a cathode electrode 105 is formed as a second main electrode on the surface of the N cathode layer 3. In addition, A is an anode terminal and K is a cathode terminal.

Next, the operation of the PiN diode will be described separately for energization and reverse recovery.

First, the operation during energization will be described. When a positive voltage larger than the built-in voltage generated at the junction between the N- base layer 101 and the P-emitter layer 102 is applied between the anode electrode 104 and the cathode electrode 105, the P-emitter layer 102 will be exposed to Holes are injected into. According to the injection amount of the holes, N electrons are emitted from the N emitter layer 103.
The carriers (electrons and holes) injected into the base layer 101 and injected into the N − base layer 101 are accumulated, and the resistance of the N − base layer 101 is reduced.

Next, the operation at the time of reverse recovery will be described.
The reverse recovery operation of the diode is an operation that occurs when the voltage applied between the anode and cathode electrodes of the diode in the energized state is inverted (the reverse voltage is applied between the anode electrode 104 and the cathode electrode 105). Is. When the applied voltage is reversed in the energized state, the N- base layer 10
The electrons and holes accumulated in 1 are correspondingly discharged to the N emitter layer 103 and the P emitter layer 102, and the depletion layer is removed from the junction (main junction) between the N − base layer 101 and the P emitter layer 102. Begins to spread. As a result, a reverse voltage is applied between the anode and the cathode, and the diode enters the reverse blocking state.

FIG. 33B schematically shows the electric field strength distribution in the depth direction from the anode to the cathode during the reverse recovery operation of the PiN diode shown in FIG. It should be noted that when this distribution is represented according to the actual size in the depth direction, it becomes a substantially triangular shape.

By the way, in recent years, in order to improve the efficiency of the above-mentioned inverter circuit and the like, the switching frequency of the switching element S has been increased, and it is required to reduce the reverse recovery loss of the diode D.

To satisfy this, the N-base layer 101
It is only necessary to reduce the amount of carriers accumulated therein, and as an effective means therefor, the impurity concentration of the P emitter layer 102 may be lowered.

However, it is not preferable to reduce the surface concentration of the P emitter layer 102 in order to keep the contact resistance between the P emitter layer 102 and the anode electrode 104 low, and to reduce the thickness of the P emitter layer 102. I had to go. Therefore, if the thickness of the P emitter layer 102 is reduced, the possibility that the PiN diode will be destroyed by the power applied during reverse recovery increases.

Further, in recent years, the switching element S has been operating at high speed in order to reduce the noise and the loss of the equipment using the above-mentioned inverter circuit, and it depends on the switching time of the switching element S. The reverse recovery operation of the diode D is also accelerated.

However, in the PiN diode of the conventional example, when the reverse recovery operation becomes faster, the peak reverse recovery current Irrp shown in FIG. 30 becomes larger, the energy applied instantaneously becomes larger, and it is destroyed when it exceeds a certain limit value. There was a problem of doing.

On the other hand, switching power supplies, especially DC-DC
An SBD having a low on-voltage and high speed is used in a portion of the converter to which a voltage of 100 V or less is applied. This S
BD loss is a conduction loss determined by ON resistance and a recovery loss at the time of recovery. The on-resistance is determined by the impurity concentration of the n- layer that forms the Schottky junction. Since the impurity concentration of the n- layer also affects the breakdown voltage, there is a trade-off between the on-resistance and the breakdown voltage of the SBD determined by the material. Exists.

In order to improve the trade-off of this SBD, a buried p layer is formed in the n- layer to relax the electric field in the n- layer, thereby increasing the impurity concentration of the n- layer while maintaining the breakdown voltage. A structure that realizes low on-resistance is known.

FIG. 34 is a sectional view schematically showing the structure of a conventional SBD.

This SBD has an n- drift layer (n- layer).
An n + cathode layer 202 is formed on one surface of 201, and a cathode electrode 203 is formed on the n + cathode layer 202. A p guard ring layer 204 is selectively formed on the other surface of the n- layer 201, and a p buried layer 205 is formed in the n- layer 201. This p buried layer 205
Are electrically suspended.

In such an SBD, the electric field in the n-layer 201 is divided by the p-embedded layer 205 in the off state in which a voltage is applied in the opposite direction. For example, p buried layer 205
In the case of a single layer, the electric field of the n − layer 201 is divided into two, and assuming a device having a breakdown voltage of 100V, the breakdown voltage required between the n − layer 201 and the p-buried layer 205 is 50V.

Since the breakdown voltage is lowered in this way,
The impurity concentration of the n- layer 201 can be doubled as compared with the case where the p-buried layer 205 is not provided, and the electric resistance in the n- layer 201 can be reduced, so that the ON resistance of the element is reduced to 1/2. It is possible to reduce to a certain degree.

In the SBD having the conventional structure as described above, it is indispensable to form the high-density and fine p-buried layer 205 in order to maintain the withstand voltage and the low on-resistance. In order to maintain the breakdown voltage, it is necessary to divide the electric field by the p-embedded layer 205, and the electric field lines are terminated between the p-embedded layer 205 and the p-guard ring layer 204 to divide the electric field. A high density p buried layer 205 is required.
In this case, the resistance between the p-embedded layers 205 becomes a parasitic resistance, and therefore the fine p-embedded layer 205 is required to achieve a low on-resistance.

However, when forming the p buried layer 205,
When the buried crystal growth is performed, re-diffusion occurs during the crystal growth, so that it is difficult to form a fine p buried layer.

[0028]

As described above, in the conventional PiN diode, when the thickness of the P emitter layer is reduced in order to meet the demand for reducing the reverse recovery loss, the power applied during the reverse recovery is reduced. There was a problem that the possibility of destruction increases.

Further, in the conventional high breakdown voltage high speed diode, when the reverse recovery operation becomes faster, the peak reverse recovery current Irrp becomes larger, the energy applied instantaneously becomes larger, and the diode is destroyed when it exceeds a certain limit value. was there.

Further, in the conventional SBD, it is necessary to form a high-density and fine p-type buried layer in order to maintain a breakdown voltage and a low on-resistance, but it is possible to form a fine p-type buried layer. There was a problem that it was difficult.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of realizing a PiN diode having improved reverse recovery characteristics and improved withstand capacity during reverse recovery. To do.

Another object of the present invention is to provide a semiconductor device capable of realizing a high breakdown voltage high speed diode capable of suppressing the breakdown of the diode during the reverse recovery operation.

Still another object of the present invention is to provide a semiconductor device capable of forming a fine p-type buried layer and realizing an SBD having a high breakdown voltage and a low on-resistance.

[0034]

A first semiconductor device of the present invention comprises a first conductivity type base layer and a first conductivity type emitter layer formed on a first main surface of the first conductivity type base layer. A second conductive type emitter layer formed on the second main surface of the first conductive type base layer, and selectively formed in the first conductive type base layer in contact with the second conductive type emitter layer. A first conductive type pillar layer; a first conductive type base layer; and a second conductive type pillar layer formed in the first conductive type base layer in contact with the first conductive type pillar layer. Characterize.

A second semiconductor device of the present invention is a first conductivity type base layer, a first conductivity type emitter layer formed on a first main surface of the first conductivity type base layer, and the first conductivity type. A second conductive type emitter layer formed on the second main surface of the base layer; and a second conductive type potential fixing layer selectively embedded in the first conductive type base layer. To do.

A second semiconductor device of the present invention comprises a first semiconductor layer of the first conductivity type and a second semiconductor layer of the second conductivity type formed on one surface of the first semiconductor layer and having a high impurity concentration. And a third semiconductor layer having a high impurity concentration of the first conductivity type formed on the other surface of the first semiconductor layer,
A second conductive type fourth semiconductor layer for relaxing an electric field is formed on the surface of the first semiconductor layer at a position deeper than the second semiconductor layer.

A fourth semiconductor device of the present invention is a first semiconductor layer of the first conductivity type, a first main electrode electrically connected to the first semiconductor layer, and the first semiconductor. A second semiconductor layer of the second conductivity type selectively formed on the surface of the layer, an insulator embedded in a groove selectively formed on the surface of the first semiconductor layer, and a bottom of the groove Formed on the surfaces of the third semiconductor layer of the second conductivity type selectively formed on the first semiconductor layer and the second semiconductor layer, and forming a Schottky junction with the first semiconductor layer. And a second main electrode.

According to a fifth semiconductor device of the present invention, a first conductive type first semiconductor layer, a first main electrode electrically connected to the first semiconductor layer, and the first semiconductor layer are provided. A polycrystalline semiconductor embedded in a groove selectively formed on the surface of the layer,
A second conductive type second semiconductor layer electrically connected to the polycrystalline semiconductor; an insulator embedded in a groove selectively formed on the surface of the first semiconductor layer; A third semiconductor layer of the second conductivity type selectively formed on the bottom, and formed on the surfaces of the first semiconductor layer and the second semiconductor layer,
Second forming a Schottky junction with the first semiconductor layer
And a main electrode of.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the following embodiments, the first conductivity type is n type and the second conductivity type is p type. Further, in the drawings, constituent elements having substantially the same functions and configurations are designated by the same reference numerals, and repeated description will be given only when necessary.

<First Embodiment> According to the research conducted by the inventors, in order to obtain good reverse recovery characteristics in a silicon PiN diode having a withstand voltage of about 4.5 kV, the thickness of the P-type emitter layer is 5 μm or less. Turned out to need to.

However, it has been found that if the thickness of the P-type emitter layer is 5 μm or less, the PiN diode is more likely to be destroyed by the power applied during reverse recovery. This is because, as in the characteristic of the conventional example shown in FIG. 31B, the portion where the highest electric field is generated is the main junction, and the reverse recovery current and the high electric field cause the avalanche phenomenon in the main junction portion near the surface. It is thought to be easily destroyed.

Therefore, in the first embodiment, several examples of PiN diodes having improved reverse recovery characteristics and improved withstand capacity during reverse recovery will be described.

(First Embodiment) FIGS. 1A and 1B.
FIG. 4 is a cross-sectional view schematically showing the structure of the high breakdown voltage PiN diode according to the first embodiment of the present invention and a characteristic diagram schematically showing the electric field strength distribution in the depth direction from the anode to the cathode during the reverse recovery operation. Is.

In this diode, a P emitter layer 2 is formed on an N- base layer 1 and an N emitter layer 3 is formed on the opposite side, similarly to the conventional diode described with reference to FIG. 33 (a). Has been formed. An anode electrode 4 is formed on the P emitter layer 2, and a cathode electrode 5 is formed on the N emitter layer 3. Furthermore, an N pillar layer 6 and a P pillar layer 7 are inserted between the N − base layer 1 and the P emitter layer 2.

Here, the impurity concentration of the N pillar layer 6 is N-.
Although the concentration is set to be higher than that of the base layer 1, the concentration may be set to the same level. The impurity concentration of the P pillar layer 7 is set to be approximately the same as that of the N pillar layer 6. The pillar layers 6 and 7 have a depth-width ratio (aspect ratio) set to 5 to 7.

The diode having the above-mentioned structure is the N-base layer 1
When the depletion layer spreads in the reverse blocking state by forming the N pillar layer 6 and the P pillar layer 7 between the N pillar layer 6 and the P emitter layer 2, the charge generated by the impurity ions causes the N pillar layer 6 and the P pillar layer 7 to be charged. And the effective impurity concentration decreases. Therefore, by setting the impurity concentration of the P pillar layer 7 higher than that of the N pillar layer 6 by a specified amount, a low concentration P-type impurity layer can be created.

According to such a diode, as shown in FIG.
As shown in (b), the highest electric field is generated between the N − base layer 1 and the pillar layers 6 and 7, so that the region where the avalanche phenomenon is most severe is the boundary portion between the N − base layer 1 and the pillar layers 6 and 7. Becomes As described above, the avalanche phenomenon is weakened just below the P emitter layer 2, so that the breakdown of the diode can be suppressed, and the conduction loss can be reduced without increasing the reverse recovery loss.

The thicknesses of the N-pillar layer 6 and the P-pillar layer 7 are set in consideration of the region where the avalanche phenomenon occurs.
It is preferably 5 μm or more.

Further, it is not necessary to form the P emitter layer 2 on the entire surface of the N- base layer 1, and as shown in FIG.
-It may be formed on a part of the surface of the base layer 1. in this case,
The contact between the anode electrode 4 and the N pillar layer 6 and the P pillar layer 7 must be a Schottky contact in order to obtain a withstand voltage. When formed as shown in FIG. 29,
The area of the P emitter layer 2 for injecting holes becomes small, and N
-Injection of holes into the base layer 1 is suppressed, and the reverse recovery characteristic can be further improved.

(Second Embodiment) FIG. 2 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a second embodiment of the present invention.

This diode is obtained by modifying the structure outside the region of the junction termination portion where the junction between the P emitter layer 2 and the N-base layer terminates in the diode described with reference to FIG.

This diode has an insulating film on the N- base layer 1 in order to relax the electric field at the peripheral portion of the P emitter layer 2.
The field plate 8 is formed via 11. At the edge of the chip, an N-type EQR (Equi-Potential Rin) for suppressing the spread of the depletion layer and stabilizing the potential is provided.
g) Layer 9 and EQR electrode 10 are formed.

In the reverse blocking state of the diode having the above structure,
Since the field plate 8 has the same potential as the anode electrode 4 and the interval between equipotential surfaces under the field plate 8 is widened, the electric field is alleviated and the breakdown voltage of the element can be improved.

The impurity concentration ratio between the N pillar layer 6 and the P pillar layer 7 at the junction termination portion is set to be substantially the same in order to promote depletion, unlike the central portion of the element. Good.

Further, it is not necessary to form the P emitter layer 2 on the entire surface of the N- base layer 1, and as shown in FIG.
-It may be formed on a part of the surface of the base layer 1. in this case,
The contact between the anode electrode 4 and the N- base layer 1 must be a Schottky contact in order to obtain a withstand voltage. When formed as shown in FIG. 30, P for injecting holes is formed.
The area of the emitter layer 2 is reduced, the injection of holes into the N- base layer 1 is suppressed, and the reverse recovery characteristic can be further improved.

(Third Embodiment) FIG. 3 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a third embodiment of the present invention.

This diode is obtained by changing the outside of the junction termination portion in the diode described with reference to FIG. 2 into a two-stage field plate structure.

By thus forming the two-stage field plate structure, the effect of alleviating the electric field is enhanced as compared with the one-stage field plate structure of FIG. 2, so that the breakdown voltage of the device is improved.

The field plate 8 is not limited to the two-stage structure, and may be a multi-stage field plate having two or more stages.

(Fourth Embodiment) FIG. 4 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a fourth embodiment of the present invention.

This diode is obtained by replacing the outside of the junction termination portion of the diode shown in FIG. 2 or 3 with a RESURF structure.

In this diode, a P-- RESURF layer 12 having a low impurity concentration is formed outside the peripheral portion of the P emitter layer 2, and the P-- RESURF layer 12 is depleted in the reverse blocking state. It is set to concentration.

By adopting such a RESURF structure, the P-- RESURF layer 12 is depleted in the reverse blocking state, so that a negative charge exists on the surface of the P-- RESURF layer 12 in the same state. Therefore, similarly to the field plate structure shown in FIG. 2 or 3, the electric field at the junction termination portion is relaxed and the breakdown voltage is improved.

(Fifth Embodiment) FIG. 5 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a fifth embodiment of the present invention.

This diode is modified such that the P--resurf layer 12 in the diode described above with reference to FIG. 4 is formed deeper than the P emitter layer 2.

With this structure, the action of relaxing the electric field at the junction termination portion becomes stronger, and the breakdown voltage is further improved.

(Sixth Embodiment) In the diode shown in FIG. 4 or FIG. 5, since the P--resurf layer 12 is inserted, the reverse recovery current is concentrated at the junction termination portion of the diode and the diode is destroyed. There is a possibility that this will occur, and the improvement measures will be described below.

FIG. 6 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to the sixth embodiment of the present invention.

This diode has a structure in which the outside of the junction termination portion in the diode described with reference to FIG. 4 or FIG.
It has been changed to a corrugated resurf structure.

This diode has a P emitter layer 2 and a P--
P with the RESURF layer 12 set to a concentration that does not deplete
-Modified to insert the ring layer 13.

With such a structure, it is possible to reduce the current concentration at the junction termination portion and improve the withstand voltage during reverse recovery.

Although the P-- RESURF layer 12 is formed at the same depth as the P emitter layer 2 in FIG. 6, it may be formed deeper than the P emitter layer 2. In addition, the P-ring layer 13 is
By forming it shallower than the emitter layer 2, the current at the junction termination portion can be further suppressed.

Although FIGS. 2 to 6 exemplify the case where the field plate structure and the RESURF structure are individually applied, other RFP (Registive Field Plate)
The structures may be applied individually or these structures may be used in combination.

(Seventh Embodiment) FIG. 7 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a seventh embodiment of the present invention.

This diode is different in that the width of the P pillar layer 7 is set wider than the width of the N pillar layer 6 in the diode described above with reference to FIG.

With such a structure, the impurity concentration ratio of the P pillar layer 7 and the N pillar layer 6 can be set stably.

(Eighth Embodiment) FIGS. 8A and 8B.
FIG. 4A is a cross-sectional view schematically showing the structure of a high breakdown voltage PiN diode according to an eighth embodiment of the present invention and a characteristic view schematically showing the electric field strength distribution in the depth direction from the anode to the cathode during reverse recovery operation. Is.

This diode is different from the diode described above with reference to FIG. 1A in that the N-pillar layer 6 and the P-pillar layer 7 are omitted, and a P + type potential fixing layer is formed in the N- base layer 1. The difference is that 20 is inserted. Here, the impurity concentration of the P + potential fixed layer 20 is set to a concentration that does not deplete in the reverse blocking state.

In the reverse blocking state of this diode, when the depletion layer spreads between the P emitter layer 2 and the P + potential fixing layer 20, it is fixed to the potential defined by the impurity concentration of the N- base layer 1, When a large voltage is applied, the depletion layer begins to spread from the P + potential fixed layer 20 and the potential distribution becomes as shown in FIG. 8 (b).

In this case, by forming the P + potential fixing layer 20 on the side closer to the P emitter layer 2 than half the thickness of the N- base layer 1, the portion where the maximum electric field region occurs is the P + potential fixing layer. It can be set directly under 20.

With such a structure, the maximum electric field region is generated away from the main junction.
As with the diode shown in (a), the reverse recovery withstand capability is improved.

(Ninth Embodiment) FIG. 9 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a ninth embodiment of the present invention.

This diode is obtained by forming a junction termination structure on the diode described above with reference to FIG.

In this diode, a P + guard ring layer 21 is formed in the junction termination region in order to relax the electric field. Then, the insulating film 11 is formed on the junction terminal portion. Further, an N-type EQR layer 9 and an EQR electrode 10 are formed on the peripheral edge of the element.

With such a structure, in the reverse blocking state of the diode, the potential of the P + guard ring layer 21 is fixed according to the spread to the depletion layer, so that the electric field is relaxed and the breakdown voltage of the diode is reduced. Can be improved.

The P + potential fixing layer at the junction termination portion
The 20 intervals are formed as necessary to reduce the concentration of the electric field. Usually, the concentration of the electric field is relaxed by densely forming the portion close to the P emitter layer 2 (the portion where the electric field is large) and sparsely forming the portion far from the P emitter layer 2 (the portion where the electric field is relatively small). can do.

(Tenth Embodiment) FIG. 10 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a tenth embodiment of the present invention.

This diode corresponds to the P of the diode of FIG.
The + guard ring layer 21 and the P + potential fixed layer 20 are changed to be in contact with each other. With such a structure, since the P + guard ring layer 21 and the P + potential fixed layer 20 have the same potential, the potential of the P + potential fixed layer 20 is stabilized and the breakdown voltage can be stabilized.

Although the guard ring structure is illustrated as the junction termination structure in FIGS. 9 and 10, the junction termination structure is not limited to the guard ring structure, and the field plate structure illustrated in FIGS. 2 and 3 and FIG. It is possible to apply the RESURF structure illustrated in FIGS. 6A to 6C, other RFP structures, a combination of these structures, and the like.

<Second Embodiment> In the second embodiment,
A diode having a main pn junction on the n- type substrate 1, for example, "Comparison of High Voltage Power Rectifier Stru"
Several examples in which the present invention is applied to various high breakdown voltage power diodes as disclosed in ctures "1993 IEEE pp.199-204 will be described.

(Eleventh Embodiment) FIG. 11A is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to an eleventh embodiment of the present invention.

This PiN diode has a high-concentration impurity layer of the second conductivity type on one surface of the semiconductor substrate 21 of the first conductivity type.
22 is formed, a high-concentration impurity layer 23 of the first conductivity type is formed on the other surface, and an impurity layer 26 of the second conductivity type is further formed on one surface of the semiconductor substrate.
The total amount of impurities per unit area of the conductivity type impurity layer 26 is 2 ×
It is characterized in that it is 10 ¹² cm ⁻² or less.

That is, in FIG. 11A, 21 is a high-resistance (low impurity concentration) n-type semiconductor layer (n-base layer, n-type).
-Layer), and on one surface thereof is a shallow high impurity concentration p-type anode layer (p + anode layer) 22 of about 10 μm or less and a deep low impurity concentration p-type well layer (p− of about 60 μm). well) 26 is formed.

An n + cathode layer 23 is formed on the other surface of the n − layer 21. An anode electrode 24 is formed as a first main electrode on the surface of the p + anode layer 22, and n +
On the surface of the cathode layer 23, a cathode electrode 25 is formed as a second main electrode.

When a forward voltage is applied to this diode, holes are n-typed from the p + anode layer 22 through the p-well 26.
-Injected into the layer 21, electrons from the n + cathode layer 23 are n- layers
The electron-hole pairs of high concentration are accumulated in the n − layer 21 by being injected into the n − layer 21.

Next, when a reverse voltage is applied to the diode to perform a reverse recovery operation, the electrons accumulated in the n- layer 21 move to the n + cathode layer 23 and the holes move to the p + anode layer 22. Therefore, the depletion layer expands from the junction between the p-well 26 and the n-layer 21.

The diffusion depth of the p-well 26 is the rated withstand voltage of the PiN diode between the anode electrode 24 and the cathode electrode 25, that is, between the p + anode layer 22 and the n + cathode layer 23. When applied, it is preferably 5% or more of the width of the depletion layer formed in the vicinity of the junction between the n- layer 21 and the p + anode layer 22.

FIG. 11 (b) schematically shows the electric field strength distribution in the depth direction from the anode to the cathode during the reverse recovery operation of the diode of FIG. 11 (a). Here, the areas of the hatched display portions S1 and S2 correspond to p-well 26,
The voltage applied to the n-layer 21 is shown.

When the voltage applied during the reverse recovery operation of the diode of this example is equal to the voltage applied during the reverse recovery operation of the diode of the conventional example, the area of S1 + S2 in the characteristic of FIG. 11 (b) and the conventional example shown in FIG. The area of S3 in the characteristic is equal, and the following equation is established.

S1 + S2 = S3 here, S2 = W · Emax / 2 S3 = W '· Emax' / 2 Therefore,   S1 + W · Emax / 2 = W ′ · Emax ′ / 2 (1) Becomes

When the currents flowing through the diode of the present example and the diode of the conventional example are also equal, the electric field strengths in the n- layer 21 and the electric field strength in the n- substrate 101 are equal, and therefore the following equation (2) Holds.

[0103]   Emax / W = Emax '/ W' (2) By solving the above equations (1) and (2), the following equation (3) is obtained.

{1- (W / W ')} = 2S1 {1+ (W / W')} / Emax '... (3) Here, since all variables are positive values, {1- (W / W ′)} ≧ 0 (4), and by solving the equations (4) and (2), the following equation (5) is obtained.

Emax ′> Emax (5) In the above expression (5), the maximum electric field of the diode of this example is always smaller than the maximum electric field of the diode of the conventional example, that is, the maximum electric field in the diode is p− It shows that it is alleviated by well26.

When the maximum electric field in the diode is relaxed in this way, the power loss density P = ExJ locally generated in the diode is relaxed, so that the breakdown resistance of the diode is improved.

That is, the high breakdown voltage PiN of the eleventh embodiment described above.
Since the diode forms a deep diffusion p-well 26 that is fully depleted during reverse recovery operation, the maximum electric field generated inside the diode during reverse recovery operation can be relaxed, and the diode is destroyed during reverse recovery operation. Can be suppressed.

Here, the reason why the total amount of impurities in the p-well 26 is set to 2 × 10 ¹² cm ^-2 or less will be described. This value is a condition for the p-well 26 to be completely depleted before the pn junction (here, the junction between the p-well 26 and the n-layer 21) undergoes avalanche breakdown.

When the depletion layer extends in p-well 26,
By solving Poisson's equation, which is the basic equation for semiconductors, it is found that there is the following relationship between the maximum electric field Emax (V / cm) and the total amount of impurities Q (cm ^-2 ) in the depleted region. .

Emax = (q / ε _Si ) Q (6) Here, q is the amount of elementary charge of electrons and is 1.6 × 10 5.
^-19 (C), ε _Si is the dielectric constant of silicon 1.05 × 10
^-12 (F / cm).

In order for the p-well 26 to be completely depleted before the avalanche breakdown occurs in the pn junction, it is sufficient that Emax is smaller than the critical electric field strength Ec at which avalanche breakdown occurs. That is, Emax <Ec (7).

Generally, Ec is 2 to 3 × 10 ⁵ (V / cm)
Therefore, by solving the above equations (6) and (7), the condition of Q = ε _{Si ·} Ec / q ≦ 2 × 10 ¹² (cm ⁻² ) (8) is obtained. However, this value is not a strict critical condition because it depends on the device structure.

(Twelfth Embodiment) FIG. 12 is a sectional view schematically showing the structure of a high breakdown voltage P-iN diode according to a twelfth embodiment of the present invention.

This P-iN diode is shown in FIG.
Compared with the PiN diode described above with reference to FIG. 3, a p- anode layer 22a is formed on the surface of the n- layer 21 instead of the p + anode layer 22, and the other points are the same.

The p- anode layer 22a is formed as shown in FIG.
Compared with the inside p + anode layer 22, the total amount of impurities per unit area is small, and the diffusion depth thereof is shallow, which is 2 to 4 μm.

(Thirteenth Embodiment) FIG. 13 shows a high breakdown voltage MPS (Merged PiN / Schott) according to a thirteenth embodiment of the present invention.
ky) is a sectional view schematically showing the structure of a diode.

This MPS diode is different from the PiN diode described with reference to FIG.
P + anode layer 22 is selectively formed on the surface of
They are the same except that they have an ohmic contact surface and a Schottky contact surface on the contact surface between the anode electrode 24 and the silicon region.

(Fourteenth Embodiment) FIG. 14 shows a high breakdown voltage SSD (Static Shielding Dielectric) according to a fourteenth embodiment of the present invention.
(ode) is a cross-sectional view schematically showing the structure of a diode.

Compared with the MPS diode described above with reference to FIG. 13, this SSD diode has an anode electrode 24
The other points are the same, except that the Schottky contact surface has a small total amount of impurities per unit area and has a very shallow p-anode layer 22a having a diffusion depth of about 0.2 to 1 μm.

(Fifteenth Embodiment) FIG. 15 shows a high withstand voltage SPEED (Self adapting P) according to a fifteenth embodiment of the present invention.
-Emitter Efficiency Diode) FIG. 3 is a cross-sectional view schematically showing the structure of a diode.

Compared to the SSD diode described above with reference to FIG. 14, this SPEED diode has a p-anode layer 22b different in injection efficiency so as to surround the p + anode layer 22 instead of the p- anode layer 22a. The points are different, and the others are the same.

(Sixteenth Embodiment) FIG. 16 shows a high breakdown voltage SFD (Soft and Fast recov) according to a sixteenth embodiment of the present invention.
(erry Diode) is a cross-sectional view schematically showing the structure of a diode.

Compared with the SSD diode described above with reference to FIG. 14, this SFD diode has an anode electrode 24
The difference is that the Schottky contact surface of is formed of Al-Si-Alloy 27, and the other is the same.

(Seventeenth Embodiment) FIG. 17 is a sectional view schematically showing the structure of a high breakdown voltage TMBS diode according to a seventeenth embodiment of the present invention.

This TMBS diode is different from the MPS diode described with reference to FIG. 13 in that an anode electrode 24 is formed in the trench groove via an oxide film 28 instead of the p + anode layer 22. , But the others are the same.

<Third Embodiment> In the third embodiment,
Several examples in which the present invention is applied to a power SBD will be described.

(Eighteenth Embodiment) FIG. 18 is a sectional view schematically showing the structure of a power SBD according to an eighteenth embodiment of the present invention.

This SBD is n − which is the first semiconductor layer.
A semiconductor layer having a high impurity concentration (for example, n
+ Cathode layer) 32 is formed, and a first main electrode (cathode electrode) 33 is formed on the n + cathode layer 32.

On the other surface of the n-layer 31, a plurality of p-guard ring layers 34 are formed as second semiconductor layers with a space between each other selectively and in a diffused plane stripe pattern. (Trench) is formed and filled with an insulator 37. A p-embedded layer 35 is formed as a third semiconductor layer on the bottom of the groove. And the n- layer
A second main electrode (anode electrode) 36 forming a Schottky junction with 31 is formed.

FIGS. 19A to 19F show SBs in FIG.
It is sectional drawing which shows each structure typically according to the manufacturing process (process flow) of D.

First, as shown in FIG. 19A, an n + layer
A semiconductor wafer (original substrate) having an n − layer 31 formed by epitaxial growth on 32 is prepared. Next, FIG.
As shown in (b), an oxide film (SiO 2) is formed on the surface of the n − layer 31.
₂ film) 51, a pattern of resist 52 is formed, and n
Forming a groove 53 in the layer 31.

Next, as shown in FIG. 19C, boron is ion-implanted into the bottom of the groove 53 to activate it.
As shown in FIG. 19D, the p-buried layer 35 is selectively formed. After that, the inside of the groove 53 is filled with an insulator (SiO ₂ ) 37. Then, as shown in FIG.
After the p guard ring layer 34 is selectively formed on the surface of, the anode electrode 36 and the cathode electrode 33 are formed as shown in FIG.

In this process, the main heat step is only the activation annealing of the p buried layer 35 and the p guard ring layer 34, and the diffusion of the p buried layer 35 can be suppressed. It is possible to form the layer 35.

Further, as a process of suppressing the diffusion of the p-buried layer 35, contrary to the above-mentioned process, after forming the p-guard ring layer 34 on the surface of the n − layer 31, a groove is formed to form the p-buried layer 35. Then, the p-buried layer 35 can be formed under annealing conditions different from those for the p-guard ring layer 34, so that miniaturization is possible.

Here, as an example of a diode having a withstand voltage of 100 V, the n − layer 31 has an impurity concentration of 4 × 10 ¹⁵ cm −3.
The n + cathode layer 32 has an impurity concentration of about 1 × 10 ¹⁹ cm ^-3 and a thickness of about 200 μm.

The n + cathode layer 32 may be formed if necessary. The groove filled with the insulator 37 is formed with a width of 0.6 μm and a depth of 4 μm, and the p-embedded layer 35 at the bottom thereof is formed with a depth of 1 μm, a width of 1.4 μm and a lateral pitch of 3 μm. There is.

When the p buried layer 205 is formed by using buried crystal growth as in the conventional example shown in FIG. 34, the p buried layer 205 is re-diffused during the buried growth.
Is formed with a depth of 2.5 μm and a width of 3 μm, so p
The parasitic resistance between the buried layers 205 increases.

That is, as described above, when the groove 53 is formed without using the buried crystal growth and the p buried layer 35 is formed at the bottom of the groove 53, the process temperature is lowered and a high density and fine p
It becomes possible to form the buried layer 35.

FIG. 20 shows S in the case where the p-buried layer 35 is formed at the bottom of the groove as in the present embodiment and in the case where the p-buried layer 205 is formed by using buried crystal growth as in the conventional example.
It is shown in order to explain the trade-off relationship of BD on-resistance / breakdown voltage. For comparison, SB without p-embedded layer
The characteristic of D is also illustrated.

Compared to the case where there is no p-type buried layer, the ON resistance becomes lower when the p-type buried layer exists. in this case,
When the buried crystal growth is used as in the conventional example, the p-buried layer is wide, but when the p-buried layer 35 is formed at the bottom of the groove as in the present embodiment, it can be formed finely. Has a lower on-resistance than the conventional example. In particular, in a diode having a withstand voltage of 100 V or less, when the buried growth is used as in the conventional example, the parasitic resistance between the p-buried layers cannot be ignored, and the on-resistance becomes the same as that without the buried layer. In this embodiment, the withstand voltage is 100.
Even if it is V or less, a lower on-resistance can be expected as compared with the case where there is no p buried layer.

Further, in this embodiment, after forming the p-buried layer 35 at the bottom of the groove, before filling the inside of the groove with the insulator 37, the p-side surface of the groove is formed by ion implantation or vapor phase diffusion from an oblique direction. -P-guard ring layer 34 by forming a layer
By connecting the p-embedded layer 35 with the p-embedded layer 35, it is possible to quickly charge the p-embedded layer 35 that has been depleted when a reverse voltage is applied, which is advantageous for high-speed operation.

(Nineteenth Embodiment) FIG. 21 is a sectional view schematically showing the structure of a power SBD according to a nineteenth embodiment of the present invention.

Compared with the diode described above with reference to FIG. 18, this SBD has a two-layered p guard ring layer 34a composed of a polycrystalline semiconductor (polysilicon) 38 filling the groove and a p guard ring layer 34 around the groove. Are the same, and the others are the same.

According to such a structure, since the p guard ring layer 34 is formed only in the groove portion, the width is narrow, which cannot be obtained by thermal diffusion like the diode shown in FIG. 18, and
A deep p guard ring layer 34 can be formed.

As a result, it is possible to reduce the leakage current of the Schottky junction and the parasitic resistance between the p guard ring layers 34. Further, the process of forming the p-guard ring layer 34 using the groove can shorten the thermal diffusion time for forming the p-guard ring layer 34, and thus the p-guard ring layer 34 and the p-buried layer 35 can be formed. If you do the diffusion at the same time,
The diffusion time is shortened, which is suitable for forming a fine p buried layer 35.

(Twentieth Embodiment) FIG. 22 is a sectional view schematically showing the structure of a power SBD according to a twentieth embodiment of the present invention.

This SBD is different from the diode described above with reference to FIG. 18 in that the p guard ring layer 34 and the p buried layer 35 are formed in the same groove portion, and the other points are the same.

In the nineteenth embodiment shown in FIG. 21, the p-guard ring layer 34 and the p-embedded layer 35 are formed in separate grooves, but first, the p-embedded layer 35 is formed at the bottom of the groove to form the groove. If the insulator 37 is buried in the inside and then the insulator 37 is dug down by wet etching and the p-type polysilicon 38 is buried, the dry etching process can be omitted once compared with the nineteenth embodiment. It will be possible.

(Twenty-first Embodiment) FIG. 23 is a sectional view schematically showing the structure of a power SBD according to a twenty-first embodiment of the present invention.

This SBD is different from the diode described with reference to FIG. 18 in that the p guard ring layer 34 and the p buried layer 35 are formed in a plane stripe shape and are orthogonal to each other.

With such a structure, each cycle can be controlled independently. The period of the p-guard ring layer 34 affects the Schottky junction leak, and the period of the p-buried layer 35 affects the electric field division in the n-layer 31, so that it is possible to optimize each design.

Further, the p guard ring layer 34 may have a structure in which polysilicon is embedded in the groove as described above.

(Twenty-second Embodiment) FIG. 24 is a sectional view schematically showing the structure of a power SBD according to a twenty-second embodiment of the present invention.

Compared with the diode described above with reference to FIG. 18, this SBD has the p-buried layer 35 formed in a grid pattern by arranging the grooves for forming the p-buried layer in a planar grid pattern. The difference is that they are formed.

Further, in the device termination portion, the p guard ring layer 34 is formed on the surface on the anode side, and the n − layer 31 is formed.
By forming the p-embedded layer 35 therein and relaxing the electric field, a decrease in breakdown voltage is suppressed. In this case, it is possible to implement even if the period of the p guard ring layer 34 at the device termination portion is different from the period of the p buried layer 35.

With such a structure, the parasitic resistance between the p-buried layers 35 can be reduced and the on-resistance can be lowered, as compared with the case where the p-buried layers 35 are formed in a stripe shape as described above. It will be possible.

It is also possible to arrange the grooves for forming the p-buried layer so as to form a plane zigzag lattice pattern in which the lattice pattern is shifted in a zigzag pattern.

(Twenty-third Embodiment) FIG. 25 is a sectional view schematically showing the structure of a power SBD according to a twenty-third embodiment of the present invention.

In this SBD, as compared with the diode described with reference to FIG. 24, the groove for forming the p-buried layer is formed in a stripe shape in the central portion of the element and in a lattice shape in the terminal portion of the element. The points are different.

The p-buried layer 35 needs to be formed periodically even at the device terminal portion. If the groove for forming the p-buried layer is formed in a stripe shape also in the terminal portion, carriers are confined by the insulator 37 when the depletion layer extends in the lateral direction when a reverse voltage is applied, and thus depletion occurs. This is hindered, the electric field is concentrated, and the breakdown voltage is reduced. Therefore, in the terminal portion, the grooves for forming the p-buried layer are formed in a lattice shape or a zigzag lattice shape so as to prevent carriers from being confined during depletion when a reverse voltage is applied, thereby lowering the breakdown voltage. Can be suppressed.

(Twenty-fourth Embodiment) FIG. 26 is a sectional view schematically showing the structure of a power SBD according to a twenty-fourth embodiment of the present invention.

In this SBD, the p-embedded layer 35 is formed using the groove for forming the p-embedded layer in the lateral SBD. Here, 31 is an n- layer, 32 is an n + cathode layer, 33 is a cathode electrode, 34 is a p guard ring layer, 35 is a p buried layer having a structure in which polysilicon 39 is buried in a groove, and 36 is an anode electrode. is there. The n- substrate 30, which is the SBD substrate, is
It is desirable that the impurity concentration is lower than that of the n- layer 31 in which the carriers run.

Further, by increasing the number of p-embedded layers 35 in the n − layer 31 between the anode electrode 36 and the cathode electrode 33 to increase the number of electric field divisions, the concentration of the n − layer 31 becomes the number of divisions. Since it can be increased proportionally, the on-resistance can be further reduced.

The p-buried layer 35 can be formed by using ion implantation and thermal diffusion without using the groove as described above, but in order to obtain a deep and narrow p-buried layer 35, It is desirable to use grooves.

As shown by the dotted line in the figure, the p-layer 40 is formed on the surface of the n-layer 31, and the p-layer 40 is used to form the p-embedded layer 3.
When 5 and the p guard ring layer 34 are connected, the p buried layer 35 is quickly charged through the p- layer 40 during forward recovery of the diode, which is suitable for high speed operation.

In addition, the cathode electrode 33 and the anode electrode 36
Can form a deep electrode when each is formed using a groove, and can increase the effective electrode area through which carriers flow, so that it is possible to reduce the on-resistance without expanding the chip area. .

(Twenty-fifth Embodiment) FIG. 27 is a sectional view schematically showing the structure of a power SBD according to a twenty-fifth embodiment of the present invention.

This SBD is different from the lateral diode described above with reference to FIG.
The difference is that the Schottky metal 41 is embedded.

With such a structure, the embedded Schottky metal 41 exhibits the same effect as the p-embedded layer 35, so that electric field division can be performed and low on-resistance can be realized.

The anode electrode 36 and the embedded Schottky metal 41 can be formed by forming grooves simultaneously and filling the Schottky metal at the same time.

Further, a p layer is formed at the bottom and corners of the groove in which the anode electrode 36 and the Schottky metal 41 are embedded, and the corners of the groove are rounded by hydrogen annealing, wet etching, chemical dry etching or the like. It is possible to alleviate the electric field and suppress the leak current by carrying out such a treatment.

Further, if the n + cathode layer 32 is formed deep by using the groove, it is possible to widen the area over which carriers travel, and it is possible to reduce the on-resistance.

(Twenty-sixth Embodiment) FIG. 28 is a sectional view schematically showing the structure of a power SBD according to a twenty-sixth embodiment of the present invention.

This SBD is different from the lateral diode described with reference to FIG.
The insulator 42 is embedded in the groove, but operates on the same principle.

With such a structure, the embedded insulator 42 exhibits the same effect as the p-embedded layer 35, so that the electric field can be divided and a low on-resistance can be realized.

By making the shape of the insulator 42 into a plane U shape, electrons are accumulated in the U shape groove. Both the acceptor ions of the p-embedded layer 35 and the electrons accumulated at the interface of the insulator 42 are negative charges and similarly have a role of dividing the electric field, which is effective for lowering the on-resistance. Further, when the SBD surface is covered with the insulator 42, electrons are easily trapped and the electric field division is facilitated.

In FIG. 28, two layers of the insulator 42 are formed in the n − layer 31 between the anode electrode 36 and the cathode electrode 33, but even if one layer of the insulator 42 is formed, the on-resistance is reduced. Is effective, and if the number of layers of the insulator 42 is increased,
A lower on-resistance can be achieved. Further, if the Schottky electrode and the n + cathode layer 32 are deeply formed by using the groove, the on-resistance can be further reduced.

The SBD according to the third embodiment is not limited to the eighteenth to twenty-sixth examples. For example, in the eighteenth to twenty-third embodiments, the structure in which the p buried layer 35 is one layer has been described, but the p buried layer 35 is described.
Even with a structure having two or more layers, the same effect as described above can be obtained. Further, the plurality of p-embedded layers in each layer are not limited to the stripe shape described above, and may be formed in a mesh shape.

Although the SBD using silicon (Si) as the semiconductor has been described, examples of the semiconductor include silicon carbide (SiC) and gallium nitride (GaN).
A compound semiconductor such as aluminum nitride (AlN) or diamond can be used.

Further, although the third embodiment has been described with respect to the SBD having the buried layer in which the potential is floating, the switching element such as MOSFET, SIT, JFET or the like having the layer in which the potential is floating, or the combination of the SBD and the switching element or The integrated device can also be implemented according to the SBD described above.

[0181]

As described above, according to the semiconductor device of the present invention, it is possible to realize a PiN diode having improved reverse recovery characteristics and improved withstand capacity during reverse recovery.

Further, according to the semiconductor device of the present invention, it is possible to realize a high breakdown voltage high speed diode capable of suppressing the breakdown of the diode during the reverse recovery operation.

Further, according to the semiconductor device of the present invention, a fine p-type buried layer can be formed, and an SBD having a high breakdown voltage and a low on-resistance can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a first embodiment of the present invention and schematically showing an electric field strength distribution in the depth direction from an anode to a cathode during a reverse recovery operation. Characteristic diagram.

FIG. 2 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a second embodiment of the present invention.

FIG. 3 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a third embodiment of the present invention.

FIG. 4 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a seventh embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing the structure of a high breakdown voltage PiN diode according to an eighth embodiment of the present invention, and schematically shows an electric field strength distribution in the depth direction from the anode to the cathode during reverse recovery operation. Characteristic diagram.

FIG. 9 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a ninth embodiment of the present invention.

FIG. 10 is a high breakdown voltage PiN according to a tenth embodiment of the present invention.
Sectional drawing which shows the structure of a diode typically.

FIG. 11 is a high breakdown voltage PiN according to an eleventh embodiment of the present invention.
Sectional drawing which shows the structure of a diode typically, and the characteristic view which shows roughly the electric field strength distribution from the anode to the depth direction at the time of reverse recovery operation.

FIG. 12 is a high breakdown voltage P-i according to a twelfth embodiment of the present invention.
Sectional drawing which shows the structure of N diode typically.

FIG. 13 is a high breakdown voltage MPS according to a thirteenth embodiment of the present invention.
(Merged PiN / Schottky) Sectional drawing which shows the structure of a diode typically.

FIG. 14 is a high breakdown voltage SSD according to a fourteenth embodiment of the present invention.
(Static Shielding Diode) Sectional drawing which shows the structure of a diode typically.

FIG. 15 is a high breakdown voltage SPE according to a fifteenth embodiment of the present invention.
Sectional drawing which shows typically the structure of ED (Self adapting P-Emitter Efficiency Diode) diode.

FIG. 16 is a high breakdown voltage SFD according to a sixteenth embodiment of the present invention.
(Soft and Fast recoverry Diode) A sectional view schematically showing the structure of a diode.

FIG. 17 is a high breakdown voltage TMB according to a seventeenth embodiment of the present invention.
Sectional drawing which shows the structure of S diode typically.

FIG. 18 is a power SBD according to an eighteenth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 19 is a cross-sectional view schematically showing the structure according to the manufacturing process (process flow) of the SBD of FIG.

20 is an SBD in which a p-buried layer is formed by using the SBD and the buried crystal growth shown in FIG. 19 and an S without the p-buried layer.
The figure shown in order to demonstrate the trade-off relationship of ON resistance / withstand voltage of BD.

FIG. 21 is a power SBD according to a nineteenth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 22 is a power SBD according to a twentieth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 23 is a power SBD according to a twenty-first embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 24 is a power SBD according to a twenty-second embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 25 is a power SBD according to a twenty-third embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 26 is a power SBD according to a twenty-fourth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 27 is a power SBD according to a twenty-fifth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 28 is a power SBD according to a twenty sixth embodiment of the present invention.
Sectional view schematically showing the structure of FIG.

FIG. 29 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a modification of the first embodiment of the present invention.

FIG. 30 is a sectional view schematically showing the structure of a high breakdown voltage PiN diode according to a modification of the second embodiment of the present invention.

FIG. 31 is a circuit diagram showing a simplified conventional motor control inverter circuit.

FIG. 32 is a sectional view schematically showing the structure of a conventional example of a high breakdown voltage PiN diode, and a characteristic diagram schematically showing the electric field strength distribution in the depth direction from the anode to the cathode during reverse recovery operation.

FIG. 33 is a characteristic diagram schematically showing the electric field strength distribution in the depth direction from the anode to the cathode during the reverse recovery operation of the conventional high breakdown voltage diode.

FIG. 34 is a sectional view schematically showing the structure of a conventional SBD.

[Explanation of symbols]

1 ... N- base layer, 2 ... P emitter layer, 3 ... N emitter layer, 4 ... Anode electrode, 5 ... Cathode electrode, 6 ... N pillar layer, 7 ... P pillar layer.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tomoki Inoue             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Wataru Saito             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Ichiro Omura             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 4M104 AA01 AA03 AA04 CC01 CC03                       FF10 FF32 GG02 GG03 GG18                       HH20

Claims (16)

[Claims] 1. A first conductivity type base layer, and a first main surface formed on the first main surface of the first conductivity type base layer.
A conductive type emitter layer, and a second conductive layer formed on the second main surface of the first conductive type base layer.
A conductive type emitter layer; a first conductive type pillar layer formed in contact with the second conductive type emitter layer and selectively formed in the first conductive type base layer; the first conductive type base layer; and the first conductive type pillar layer. A semiconductor device comprising: a second conductive type pillar layer formed in the first conductive type base layer in contact with the conductive type pillar layer. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type pillar layer is higher than the impurity concentration of the first conductivity type pillar layer. 3. The width of the second conductive type pillar layer is the first conductive layer.
3. The semiconductor device according to claim 1, which is wider than the width of the conductive pillar layer. 4. A first conductivity type base layer, and a first main surface formed on the first main surface of the first conductivity type base layer.
A conductive type emitter layer, and a second conductive layer formed on the second main surface of the first conductive type base layer.
A semiconductor device comprising: a conductive type emitter layer; and a second conductive type potential fixing layer selectively embedded in the first conductive type base layer. 5. The distance between the second conductivity type potential fixing layer and the second conductivity type emitter layer is less than half the thickness of the first conductivity type base layer. Semiconductor device. 6. The second main surface of the first conductivity type base layer is selectively formed outside a junction termination region where the junction between the second conductivity type emitter layer and the first conductivity type base layer terminates. 5. A guard ring layer of the second conductivity type is further provided, and a part of the potential fixing layer of the second conductivity type is in contact with a bottom portion of the guard ring layer of the second conductivity type.
Alternatively, the semiconductor device according to item 5. 7. A first semiconductor layer of a first conductivity type, a second semiconductor layer having a high impurity concentration of a second conductivity type formed on one surface of the first semiconductor layer, and the first semiconductor layer. A third semiconductor layer having a high impurity concentration of the first conductivity type formed on the other surface of the semiconductor layer, and an electric field relaxation formed on the surface of the first semiconductor layer at a position deeper than the second semiconductor layer. And a fourth semiconductor layer of the second conductivity type for use in a semiconductor device. 8. The fourth semiconductor layer is formed in a unit area per unit area.
The total amount of pure material is 2 x 10 ¹²cm^-2Characterized by
The semiconductor device according to claim 7, wherein 9. The diffusion depth of the fourth semiconductor layer is the same as that of the first semiconductor layer and the second semiconductor layer when a rated voltage is applied between the second semiconductor layer and the third semiconductor layer. 9. The semiconductor device according to claim 7, wherein the width of the depletion layer formed in the vicinity of the junction with the semiconductor layer is 5% or more. 10. A first semiconductor layer of a first conductivity type, a first main electrode electrically connected to the first semiconductor layer, and selectively formed on a surface of the first semiconductor layer. A second semiconductor layer of the second conductivity type, an insulator embedded in a groove selectively formed on the surface of the first semiconductor layer, and a second semiconductor layer selectively formed at the bottom of the groove. A second conductive type third semiconductor layer; and a second main electrode formed on the surfaces of the first semiconductor layer and the second semiconductor layer and forming a Schottky junction with the first semiconductor layer. A semiconductor device characterized by the above. 11. A first semiconductor layer of a first conductivity type, a first main electrode electrically connected to the first semiconductor layer, and selectively formed on a surface of the first semiconductor layer. A polycrystalline semiconductor embedded in the formed groove, a second conductive type second semiconductor layer electrically connected to the polycrystalline semiconductor, and selectively formed on the surface of the first semiconductor layer. An insulator embedded in the groove, a third semiconductor layer of the second conductivity type selectively formed at the bottom of the groove, and formed on the surfaces of the first semiconductor layer and the second semiconductor layer, A semiconductor device comprising: the first semiconductor layer and a second main electrode forming a Schottky junction. 12. The trenches filled with the polycrystalline semiconductor layer and the trenches filled with an insulating material are overlapped with each other in the horizontal direction, and the polycrystalline semiconductor is wider and deeper than the insulating material. The semiconductor device according to claim 11, wherein the depth is shallow. 13. The semiconductor device according to claim 10, wherein the second semiconductor layer and the third semiconductor layer are formed in a stripe shape and are orthogonal to each other. . 14. The second semiconductor layer and the third semiconductor layer are cyclically formed in a horizontal direction, respectively, and have different cycles, respectively. Semiconductor device. 15. The semiconductor according to claim 10, wherein the trenches embedded with the insulating material and the third semiconductor layer are arranged in a zigzag pattern or a lattice pattern. apparatus. 16. The trenches and the third semiconductor layer embedded with the insulating material are arranged in a stripe shape in the central portion of the element and in a zigzag or lattice shape in the terminal portion of the element. The semiconductor device according to any one of 10 to 14.