JP2003298069A - Semiconductor display device, its manufacturing method, and active-matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor display device that can suitably maintain its display quality even when the device is manufactured through a step of producing a polycrystalline semiconductor by irradiating an amorphous semiconductor positioned above a light shielding layer with laser light, and to provide a method of manufacturing the device. <P>SOLUTION: A light shielding layer 2 is formed on a glass substrate 1 and a silicon nitride layer 3 and a silicon oxide layer 4 are laminated upon the substrate 1 and layer 2. On the silicon oxide layer 4, an amorphous silicon layer which becomes a polycrystalline silicon layer 10 constituting a transistor DTFT is formed. Then the polycrystalline silicon layer 10 is produced by irradiating the amorphous silicon layer 4 with laser light. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor display device and a method of manufacturing the same, and more particularly, to a semiconductor display device having a light-shielding layer that blocks irradiation of light to a driving element and a method of manufacturing the same.

[0002]

2. Description of the Related Art As an example of such a semiconductor display device,
FIG. 8 shows a sectional structure of a conventional liquid crystal display device. This liquid crystal display device is manufactured by the following steps. First, a metal film is formed on the glass substrate 100 and patterned to form the light shielding layer 101. Next, silicon oxide (S) is formed on the light shielding layer 101 and the glass substrate 100.
An insulating layer 102 of iO ₂ ) is formed. Then, an amorphous silicon layer to be the polycrystalline silicon layer 110 is formed on the insulating layer 102, and the polycrystalline silicon layer 110 is formed by irradiating the amorphous silicon layer with a laser. The insulating layer 102 insulates the conductive light shielding layer 101 and the polycrystalline silicon layer 110 from each other, and at the same time, the polycrystalline silicon layer 11 is formed.
It is provided to prevent impurities from entering 0. That is, when an amorphous silicon layer is formed on the glass substrate 100 and laser irradiation is performed, not only the amorphous silicon layer but also the glass substrate 100 has a high temperature for a short time, and impurities inside the substrate 100 are removed. Polycrystalline silicon layer 11
This is because 0 may be adversely affected.

When the polycrystalline silicon layer 110 is formed in this way, an insulating layer 111 forming a gate insulating film is formed thereon.
And the gate 112 are sequentially formed. The drain 110d and the channel 110 of the polycrystalline silicon layer 110 are
The c and the source 110s are generated by implanting impurities into the polycrystalline silicon layer 110. In this way, the thin film transistor TFT as a drive element for driving the liquid crystal is produced. Further, the insulating layer 111 and the gate 112 are covered with an interlayer insulating film 113. Then, contact holes 120 are opened in the interlayer insulating film 113 and the insulating layer 111, and the drain 1 is formed through the contact holes 120.
An electrode 121 is formed on the interlayer insulating film 113 so as to be electrically connected to the source 110s for 10d.

After that, the interlayer insulating film 113 and the electrode 121 are formed.
A flattening layer 130 is formed on the upper surface, and a contact hole 131 is formed in the flattening layer 130 to form a transparent pixel electrode 140 while making contact with the electrode 121.

[0005]

As described above, the insulating layer 102 is preliminarily formed between the glass substrate 100 and the light shielding layer 101 and the amorphous silicon layer, so that the amorphous layer is formed. Glass substrate 1 during laser irradiation of silicon layer
Impurities from 00 enter the silicon layer. However, when the amorphous silicon layer is irradiated with the laser, impurities on the light shielding layer 101 and the upper surface of the light shielding layer 101 are not isolated from the insulating layer 1.
May spread to 02. It is considered that this is because not only the amorphous silicon layer but also the light shielding layer and the insulating layer are heated to a high temperature by irradiating the amorphous silicon layer with a laser. As described above, if impurities are diffused into the insulating layer 102, the display quality of the display device is unavoidably deteriorated.

Not only the liquid crystal display device described above, but also a semiconductor in which a driving element is formed by using a polycrystalline semiconductor formed by forming an amorphous semiconductor above a light-shielding layer and irradiating the amorphous semiconductor with a laser. In the display device, the actual situation caused by the diffusion of impurities into the insulating layer is also common.

The present invention has been made in view of the above circumstances, and an object thereof is to display an amorphous semiconductor above a light shielding layer by irradiating a laser to produce a polycrystalline semiconductor. An object of the present invention is to provide a semiconductor display device, a manufacturing method thereof, and an active matrix type display device, which can maintain good quality.

[0008]

The invention according to claim 1 is
In a semiconductor display device in which a polycrystalline semiconductor layer forming a drive element is provided above a light-shielding layer, a blocking layer that suppresses diffusion of impurities is provided between the polycrystalline semiconductor layer and the light-shielding layer, and the polycrystalline semiconductor layer is The gist is that it is formed on an insulating layer having a lower interface state with the polycrystalline semiconductor than the blocking layer.

A second aspect of the invention is based on the first aspect of the invention, and the gist is that the light shielding layer is formed in a tapered shape in which an end portion thereof spreads toward the transparent substrate side.

According to a third aspect of the present invention, the light shielding layer comprises:
3. The semiconductor display device according to claim 1, wherein the same signal or a constant voltage is applied to a scanning line which scans a driving element formed above the light shielding layer.

A fourth aspect of the present invention is characterized in that, in the first or second aspect of the invention, the insulating layer is made of silicon oxide and the blocking layer is made of silicon nitride.

According to a fifth aspect of the present invention, a step of forming a light shielding layer on the transparent substrate, a step of forming a blocking layer for suppressing diffusion of impurities on the light shielding layer and the transparent substrate, and an upper portion of the blocking layer. A step of forming an insulating layer having an interface level lower than that of the blocking layer, a step of forming an amorphous semiconductor layer on the insulating layer, and irradiating the amorphous semiconductor layer with light energy to increase the amount of this. The gist of the invention is to include a step of crystallizing.

A sixth aspect of the present invention is based on the fifth aspect, and is characterized in that an end portion of the light shielding layer is formed in a tapered shape that spreads toward the transparent substrate side.

According to a seventh aspect of the present invention, the light shielding layer comprises:
7. The method of manufacturing a semiconductor display device according to claim 5, wherein the same signal or a constant voltage is applied to a scanning line which scans a driving element formed above the light shielding layer.

According to an eighth aspect of the invention, in the invention of the fifth or sixth aspect, the steps from the step of forming the blocking layer to the step of forming the amorphous semiconductor layer are continuously performed in the same apparatus. This is the gist.

A ninth aspect of the present invention is, in the invention according to any one of the fifth to eighth aspects, characterized in that silicon oxide is used as the insulating layer and silicon nitride is used as the blocking layer. To do.

According to a tenth aspect of the present invention, the same substrate is provided,
A pixel region and a driver region are provided, a plurality of pixels are arranged in the pixel region, each pixel is provided with a pixel region transistor and a display element, and the driver region outputs a signal for driving each pixel of the pixel region. An active matrix type display device having a plurality of driver region transistors for outputting, wherein the pixel region transistor and the driver region transistor both use a polycrystalline semiconductor of the same material as an active layer, and are formed on the substrate. A blocking layer that is configured as a top-gate transistor and is formed below the polycrystalline semiconductor layer of the pixel region transistor and the driver region transistor to suppress diffusion of impurities and a blocking layer that is in contact with the polycrystalline semiconductor active layer. An insulating layer having a lower interface state between the polycrystalline semiconductor active layer and From the substrate side are formed in this order, further, the lower layer of polycrystalline semiconductor active layer of the pixel area transistors, and summarized in that the light-shielding layer across the insulating layer and the blocking layer is disposed.

An eleventh aspect of the present invention is the active matrix display device according to the tenth aspect, wherein the light shielding layer has a tapered side surface that widens toward the substrate side. Active matrix display device.

According to a twelfth aspect of the present invention, in the active matrix type display device according to the tenth or eleventh aspect,
The gist of the present invention is that the same signal or a constant voltage as that of a scanning line for scanning the pixel region thin film transistor formed above the light shielding layer is applied to the light shielding layer.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which a semiconductor display device and its manufacturing method according to the present invention are applied to a liquid crystal display device and its manufacturing method will be described below with reference to the drawings.

FIG. 1 is a schematic circuit configuration diagram of a liquid crystal display device according to the present embodiment, showing a pixel region formed on the same substrate and a driver region formed around the pixel region. FIG. 2A shows a planar configuration near one pixel (one dot) as a minimum display unit in the pixel region of the liquid crystal display device as shown in FIG.

The drain 10d, the channel 10c and the source 10s of the top gate type double gate transistor DTFT shown in FIG. 2A are formed in the polycrystalline silicon layer 10. And this transistor DTFT
A data (drain) signal line 23 is connected to the drain 10d of the through a contact hole 22.
The gate 12 is formed integrally with the gate signal line 15. On the other hand, the source 10 s of the transistor DTFT has a transparent pixel electrode 40 through the contact hole 20.
Are connected.

The display signal (video signal) applied from the H driver to the corresponding data signal line 23 is supplied from the V driver to the gate 12 via the corresponding gate signal line 15.
A scanning signal (selection signal) is applied to the transistor DTF
When T is turned on, it is applied to the pixel electrode 40 via the drain 10d and the source 10s. In this embodiment, the polycrystalline silicon layer 10 is extended further outward (on the side of the adjacent pixel) from the region where the source 10s is formed, and is formed of the same material as the gate 12 above this extended portion. A storage capacitor is formed by the electrode 13. The electrodes 13 of this storage capacitor are connected to each other by a storage capacitor line 16. By providing the storage capacitor in each pixel in this manner, the video signal output to the source 10s can be held for a sufficient time for driving the pixel electrode 40.

Here, the transistor DT in the pixel region
The light shielding layer 2 is formed below the FT. The light shielding layer 2 is formed along the gate signal line 15 and has a width larger than the width of the gate signal line 15.
This prevents light incident from below the transistor DTFT, that is, from the substrate 1 side, from being blocked by the light shielding layer 2 and radiated to the channel 10c.
It should be noted that the gate signal line 15 and the light shielding layer 2 are electrically connected to each other here (not shown in FIG. 2 (a circuit is shown in FIG. 1)).

FIG. 2B shows a sectional structure taken along line AA of FIG.

As shown in FIG. 2B, on the glass substrate 1, for example, chromium (Cr), molybdenum (M
o), titanium (Ti), tungsten (W) and the like, the light-shielding layer 2 made of a refractory metal film is formed. A silicon nitride (SiN) layer 3 is formed on the light shielding layer 2.
And a silicon oxide (SiO ₂ ) layer 4 are sequentially laminated. A polycrystalline silicon layer 10 is formed on the silicon oxide layer 4. This polycrystalline silicon layer 1
Impurity is injected into 0 to impart a predetermined conductivity, thereby forming the drain 10d, the channel 10c, and the source 10s. The transistor DT is formed on the polycrystalline silicon layer 10.
Silicon oxide (SiO ₂ ) and silicon nitride (Si) that function as a gate insulating film of FT and a dielectric film of a storage capacitor.
The insulating layer 11 formed of the laminated film of N) is formed. Then, on the insulating layer 11, for example, chromium (Cr),
The gate 12 and the electrode 13 made of a refractory metal film such as molybdenum (Mo), titanium (Ti), and tungsten (W) are formed.

These insulating layer 11, gate 12, electrode 13
A silicon nitride (SiN) film and a silicon oxide (S
An interlayer insulating film 14 is formed by laminating an iO ₂ ) film. Contact holes 20 and 22 are formed in the interlayer insulating film 14 in the regions corresponding to the source 10s and the drain 10d of the transistor DTFT. Through the contact holes 20 and 22, contacts are established between the source 10s and the electrode 21 and between the drain 10d and the data signal line 23. The data signal lines 23 and the electrodes 21 are formed of a laminated film of molybdenum (Mo), aluminum (Al) and molybdenum (Mo).

The interlayer insulating film 14 and the drain signal line 2 are also provided.
3. A flattening layer 30 made of an organic resin is formed on the electrodes 21 to cover them. A contact hole 31 is formed in the flattening layer 30, and the electrode 21 and ITO (Indium Tin O 2) are formed through the contact hole 31.
The pixel electrodes 40 made of xide) are electrically connected.

In the above display device, the silicon nitride layer 3 is provided as a blocking layer for preventing diffusion of impurities to the upper layer on the light shielding layer 2, and the interface level at the interface with the polycrystalline silicon layer is provided on the upper layer of this blocking layer. A silicon oxide layer 4 is sequentially laminated as an insulating layer lower than the blocking layer, and a polycrystalline silicon layer 10 is formed on the silicon oxide layer 4. Therefore, the display quality can be appropriately maintained even when the step of forming the polycrystalline silicon layer 10 by irradiating the amorphous silicon layer above the light shielding layer 2 with the laser is provided.

That is, the silicon nitride layer 3 is formed on the light shielding layer 2.
Since the amorphous silicon layer to be the polycrystalline silicon layer 10 is irradiated with the laser beam, the light shielding layer 2 is formed.
It is possible to prevent the material and impurities on the light shielding layer 2 from diffusing into the silicon oxide layer 4. Further, since the polycrystalline silicon layer 10 is formed on the silicon oxide layer 4 having a lower interface state than the silicon nitride layer 3, the characteristics of the transistor DTFT configured using the polycrystalline silicon layer 10 are also kept good. be able to. On the other hand, when the polycrystalline silicon layer 10 is directly formed on the silicon nitride layer 3,
Due to the high interface state, carrier traps increase, or the threshold value of the transistor DTFT changes, which causes characteristic variations.

Further, in the present embodiment, the end portion (side wall) of the light shielding layer 2 is formed in a tapered shape that spreads toward the glass substrate 1 side. As a result, a step generated on the glass substrate 1 between the portion where the light-shielding layer 2 is formed and the other portion can be relaxed. Therefore, when the silicon nitride layer 3 and the silicon oxide layer 4 are formed on the glass substrate 1, It becomes possible to avoid problems such as cracks in the.

It should be noted that H for driving the pixel region shown in FIG.
Each pixel T in the above pixel area is included in the driver and V driver.
A driving element (thin film transistor) using the same polycrystalline silicon layer as that of FT (DTFT) as an active layer can be adopted. In this case, it is possible to adopt a structure in which a light-shielding layer is not provided in the lower layer of the driver transistor, as shown in FIG. In the driver region, the transistor is required to operate at high speed, and it is preferable that the grain size (grain size) of polycrystalline silicon is large.
On the other hand, the transistors in the pixel region are required to have a small leak current and a small characteristic variation in each pixel,
For that purpose, since the grain size is large, it is required that the factors that affect the characteristics such as the number of crystal grain boundaries are equal in each TFT as much as possible. When amorphous silicon is irradiated with laser under the same conditions to perform polycrystallization annealing, the light diffusion layer 2 which is a metal layer having a high thermal conductivity as the lower layer has a higher thermal diffusion rate, and thus the final layer is formed. The grain size obtained in 1 tends to be small. Therefore, in the driver region, the light shielding layer 2 is not provided in the lower layer of the TFT (removed at the time of patterning the light shielding layer), the light shielding layer 2 is provided only in the lower layer of the TFT in the pixel region, and the amorphous silicon is annealed under the same conditions. Thus, polycrystalline silicon having an appropriate grain size can be obtained in each region. As will be described later, in order to obtain an appropriate grain size for any region by performing the annealing under the same energy condition, the insulating layer 4 located below the polycrystalline silicon layer 10 is required.
It is preferable to adjust the thickness of the blocking layer 3 to optimize the heat capacity of the insulating layer and the blocking layer.

Next, the manufacturing procedure of the liquid crystal display device of this embodiment will be described.

In this series of steps, first, as shown in FIG. 4A, the refractory metal film is formed on the glass substrate 1 by sputtering, for example, to have a film thickness of " The film is formed at 200 nm "and patterned. At the time of this patterning, as described above, the end portion (side wall) of the light shielding layer 2 is formed in a tapered shape that spreads toward the glass substrate 1 side.

Next, the silicon nitride layer 3 and the like are deposited by a device different from the sputtering device used for forming the light shielding layer 2. That is, in this example, plasma CVD (Ch
A substrate having the patterned light-shielding layer 2 is carried into an emical vapor deposition (chemical vapor deposition) apparatus, and silicon nitride is formed into a film having a thickness of, for example, “50 nm” as shown in FIG. Then, the silicon nitride layer 3 as the blocking layer is formed.
Following this, similarly using the plasma CVD method, as shown in FIG.
As shown in (c), a silicon oxide film having a film thickness of "13" is used.
The silicon oxide layer 4 as the insulating layer is formed by forming the film with a thickness of 0 nm. Further, as shown in FIG. 4D, an amorphous silicon layer 10 'is formed to a film thickness of "50 nm" by the plasma CVD method.

The steps from the silicon nitride layer 3 to the amorphous silicon layer 10 'shown in FIGS. 4 (b) to 4 (d) are continuously performed in the same apparatus (CVD apparatus) in this embodiment. Do it. That is, by using a multi-chamber including a plurality of chambers (chambers A, B, and C) schematically shown in FIG. 5, the film formation from the silicon nitride layer 3 to the amorphous silicon layer 10 ′ is performed. Perform continuously in vacuum. This suppresses impurities from being mixed into the layers from the silicon nitride layer 3 to the amorphous silicon layer 10 '.

After the silicon nitride layer 3 to the amorphous silicon layer 10 'are continuously formed in this way, the glass substrate 1 on which the amorphous silicon layer 10' is formed is taken out from the apparatus used for the film formation. Then, as shown in FIG.
The amorphous silicon layer 10 ′ is polycrystallized by irradiating it with laser as polycrystallization annealing.

Then, as shown in FIG.
Polycrystalline silicon layer 10 is formed by patterning
In addition, using ion doping, for example, boron or phosphorus
"1 x 10¹³After about a degree of doping the resist mask
Rin through the 60 "1 x 10 ¹⁵"About doping
It Next, after removing the resist mask 60, FIG.
As shown in (b), using the plasma CVD method,
For example, silicon oxide (SiO 2) with a film thickness of “130 nm”₂)
And, for example, silicon nitride (SiN) having a film thickness of “50 nm”
The insulating layer 11 is formed by laminating. And FIG.
As shown in (c), the gate 12, the electrode 13, etc. are formed.
To achieve this, a refractory metal film, for example, with a film thickness of "200 nm"
Film formation and patterning, using the gate 12 as a mask
For example, "1 x 10"¹³Dope to a degree. This
As a result, the channel 10c and the drain 10d
And LDD (Ligh) between channel 10c and source 10s.
tly Doped Drain).

Next, as shown in FIG. 6D, for example, silicon nitride having a film thickness of "100 nm" and a film thickness of "500" are used.
Then, the interlayer insulating film 14 is formed by laminating silicon oxide of “nm” by plasma CVD method, and the contact holes 20 and 22 are opened in the insulating layer 11 and the interlayer insulating film 14. Then, as shown in FIG. 6E, for example, molybdenum (Mo) having a film thickness of "100 nm" and a film thickness of "400" are used.
The gate signal line 15 is formed by stacking aluminum (Al) having a thickness of “nm” and molybdenum (Mo) having a thickness of “100 nm”.
The electrodes 21 are formed. Further, the flattening layer 30 as shown in FIG. 2B is formed thereon, and the display device shown in FIG. 1 is formed.

According to this embodiment described above, the following effects can be obtained.

(1) A silicon nitride layer 3, a silicon oxide layer 4, and a polycrystalline silicon layer 10 were laminated on the light shielding layer 2. Therefore, it is preferable that the light-shielding layer 2 and impurities on the upper surface thereof diffuse into the silicon oxide layer 4 when the amorphous silicon 10 ′ serving as the polycrystalline silicon layer 10 is irradiated with a laser in the silicon nitride layer 3. Suppressed to. Further, the silicon oxide layer 4 having a lower interface state than the silicon nitride layer 3
By forming the polycrystalline silicon layer 10 on the transistor DT, the transistor DT configured by using the polycrystalline silicon layer 10 is formed.
The characteristic of FT can be maintained suitably.

(2) By forming the end portion of the light-shielding layer 2 in a tapered shape that spreads toward the glass substrate 1 side, the step difference between the portion where the light-shielding layer 2 is formed on the glass substrate 1 and the other portion is alleviated. be able to. Therefore, when forming the silicon nitride layer 3 and the silicon oxide layer 4, it is possible to avoid problems such as cracks in these layers.

(3) The film formation from the silicon nitride layer 3 to the amorphous silicon layer 10 'is continuously performed in the same apparatus.
For this reason, it is possible to prevent each of these layers from being immersed in the outside air during the film formation of these layers, and thus it is possible to suitably suppress the mixing of impurities into the layers from the silicon nitride layer 3 to the amorphous silicon layer 10. be able to.

The above embodiment may be modified and implemented as follows.

The materials exemplified in the above embodiment may be appropriately changed. For example, the data signal line 23, the electrode 21 and the like are made of aluminum (Al) and silicon aluminum (Al-S).
It may be formed by either i) or copper (Cu), or a laminated film of them and a refractory metal such as molybdenum (Mo) or titanium (Ti). Further, instead of the glass substrate 1, any transparent substrate such as a transparent plastic substrate may be used.

Each film thickness exemplified in the above embodiment may be appropriately changed in consideration of the film forming speed, the contact hole forming time and the like. For example, if the thickness of the silicon oxide layer 4 is
The thickness of the silicon nitride layer 3 may be set to "50 nm to 4000 nm" and "50 nm to 2000 nm".

Here, in the driver region, the metal light-shielding layer is not formed, and the amorphous silicon is polycrystallized by the laser annealing under the same conditions, so that the polycrystalline silicon having an appropriate grain size is formed in both the driver region and the pixel region. When a layer is obtained, it is preferable that the thicknesses of the blocking layer and the insulating layer be determined in consideration of heat leak due to the light shielding layer in the pixel region where the metal light shielding layer is below the polycrystalline silicon layer. is there. That is, when polycrystallizing amorphous silicon by laser annealing, the range of the optimum value of energy for realizing an appropriate grain size is not so wide, so that there is no light-shielding layer below the polycrystal silicon layer and there is no light shielding layer on the glass substrate. In the driver region in which the polycrystalline silicon layer is formed via the blocking layer and the insulating layer, and in the pixel region in which the light-shielding layer with a large heat leak exists in the lower layer, the blocking layer and the blocking layer are formed so as to have a relatively similar heat leak. It is preferable to set the thickness of the insulating layer. To realize this, each layer can be set as follows, for example. First, when the film thickness h2 of the silicon nitride layer 3 as the blocking layer is 50 nm, the thickness h1 of the silicon oxide layer 4 is preferably 200 nm or more. Alternatively, when the thickness h1 of the silicon oxide layer 4 is 130 nm, the thickness h2 of the silicon nitride layer 3 is 1
It is preferably at least 00 nm. Of course, this 2
The respective thicknesses of the layers are not limited to these, and the materials and the thicknesses of the blocking layer and the insulating layer are not particularly limited to the above examples. However, these two layers are an amorphous silicon layer and a metal light-shielding layer. It is preferable that the gap between the layers is increased and the amorphous silicon layer is formed to have a thickness that makes it difficult for heat to escape when the laser is irradiated.

In place of the laminated structure of the light shielding layer 2, the silicon nitride layer 3, the silicon oxide layer 4 and the polycrystalline silicon layer 10, the space between the light shielding layer 2 and the silicon nitride layer 3 or the silicon nitride layer 3 and the silicon oxide layer. Another film may be interposed between the four. It is desirable that this film has a low dielectric constant. Thereby, the electrostatic capacitance between the light shielding layer 2 and the polycrystalline silicon layer 10 can be suppressed to be small.

In place of the silicon nitride layer 3, an arbitrary blocking layer capable of suppressing the diffusion of the material of the light shielding layer 2 and the impurities on the light shielding layer 2 at the time of irradiating the amorphous silicon layer 10 ′ with a laser may be used. Good. Further, instead of the silicon oxide layer 4, any insulating film having an interface state lower than that of the blocking layer may be used.

The example in which the light shielding layer is connected to the gate signal line is shown, but in addition to this, it may be connected to the storage capacitor line.

The drive element is not limited to the double gate transistor DTFT.

The present invention is applied not only to liquid crystal display devices but also to any semiconductor display device having a polycrystalline semiconductor layer formed by irradiating a laser on an amorphous semiconductor layer provided on a light shielding layer. be able to.

Specifically, for example, as shown in FIG. 7, an active matrix type electroluminescence (E
L) It can be applied to a display device and the like, and similar effects can be obtained. Here, in the EL display device of FIG. 7, a light shielding layer is not formed below the TFTs in the H driver region and the V driver region as in the above, and the active TFTs are formed on the stacked structure of the blocking layer and the insulating layer. Layer (polycrystalline silicon layer) is formed, and TFTs (Tr1, Tr1) in the pixel region are formed.
A configuration may be adopted in which a light shielding layer is formed below 2) and the blocking layer and the insulating layer are formed between the light shielding layer and the active layer (polycrystalline silicon layer) of the pixel region TFT. EL element (OL connected to the pixel TFT (Tr2)
ED) uses, for example, the ITO pixel electrode 40 of FIG. 2B as a first electrode, and a second electrode made of a metal or the like facing the first light emitting element layer having a multilayer or single layer structure and the first electrode. A structure in which and are sequentially formed may be used. In addition, in FIG. 7, VL is EL through Tr2 in the pixel TFT.
It is a power supply line for supplying a current according to the display content to the element. In FIG. 7, the metal layer below Tr1 has a gate potential, and the metal layer below Tr2 is connected to a power supply potential for electroluminescence. Connection in Tr2 is T
This has the effect of causing the current capacity of r2 to decrease. The connection of the metal layers of Tr1 and Tr2 is not limited to this, and when high-speed driving or the like is not necessary as described above, it is possible to connect to a constant voltage potential such as a storage capacitor line,
It is also possible to supply the gate voltage when current capability is required. As a combination thereof, when Tr1 is connected to the gate signal line, Tr2 is any one of the gate signal line, the EL drive power source line, and the storage capacitor line.
If Tr1 is connected to the storage capacitor line, Tr2 is a gate signal line, EL
May be connected to any one of the drive power supply line for EL and the storage capacitor line. Further, when Tr1 is connected to the drive power supply line for EL, Tr2 is a gate signal line, a drive power supply line for EL, and It may be connected to any one of the storage capacitor lines, but the effect can be obtained in any case.

[0054]

According to the first aspect of the invention, the blocking layer prevents diffusion of impurities in the light shielding layer material and the upper surface of the light shielding layer, which occurs when a polycrystalline semiconductor layer is formed by irradiating a laser on the amorphous semiconductor layer. It can be suppressed appropriately. Furthermore, by forming the polycrystalline semiconductor layer on the insulating film having a lower interface state than the blocking layer, it is possible to maintain good characteristics of the driving element including the semiconductor layer.

According to the second aspect of the present invention, the end portion of the light shielding layer is tapered so as to spread to the transparent substrate side, whereby the step difference between the light shielding layer forming region and the other regions can be reduced. As a result, it is possible to avoid problems such as cracking during the formation of the blocking layer or the insulating layer. According to the invention described in claims 3, 7 and 12, the potential of the light-shielding layer is not stable in the state where the light-shielding layer is not connected anywhere, and the display signal charging / holding operation by the TFT becomes unstable for each pixel. It is possible to prevent the display quality from deteriorating.
That is, if the potential of the light-shielding layer is kept constant, the signal charge holding operation becomes stable and it is possible to prevent the display quality from deteriorating.
Furthermore, since the capacity during charging can be improved by connecting the gate potential, it becomes possible to cope with high-speed driving that requires charging capacity.

According to the fourth aspect of the invention, the blocking layer and the insulating layer having a lower interface state than that of the blocking layer can be accurately constituted.

According to a fifth aspect of the present invention, the method comprises the step of forming a blocking layer above the light shielding layer and the step of forming an amorphous semiconductor layer on the insulating layer having an interface level lower than that of the blocking layer. Therefore, the blocking layer can suitably suppress the diffusion of the light-shielding layer material and the impurities on the upper surface of the light-shielding layer, which are generated when the polycrystalline semiconductor is generated by irradiating the amorphous semiconductor with a laser. Further, by providing a step of forming an amorphous semiconductor layer on an insulating film having an interface state lower than that of the blocking layer, it is possible to maintain excellent characteristics of a drive element including the semiconductor layer. .

According to the sixth and eleventh aspects of the present invention, the end portion of the light-shielding layer is tapered so as to spread toward the transparent substrate, so that the step difference between the light-shielding layer forming region and the other regions is reduced. As a result, it is possible to avoid problems such as cracking during the film formation of the blocking layer and the insulating layer.

According to the invention described in claim 8, since the steps from the step of forming the blocking layer to the step of forming the amorphous semiconductor layer are continuously performed in the same apparatus, each layer is formed at the time of forming these layers. It is possible to avoid being immersed in the outside air, and consequently it is possible to prevent impurities from mixing into these layers.

According to the ninth aspect of the present invention, the blocking layer and the insulating layer having a lower interface state than that of the blocking layer can be accurately formed.

According to the tenth aspect of the present invention, the light-shielding layer is removed in the driver region, the light-shielding layer is formed in the pixel region, and the same layer is formed under each polycrystalline semiconductor active layer formed in those regions. By forming the insulating layer and the blocking layer, it becomes easy to obtain a polycrystalline semiconductor having an appropriate grain size in each region by performing annealing for polycrystallization under the same conditions, for example. In addition, in the pixel region, it is possible to reliably prevent impurities from entering the drive element from the light-shielding layer side, and it is possible to prevent irradiation of external light from the substrate side that causes characteristic fluctuations and leak currents.

[Brief description of drawings]

FIG. 1 is a schematic circuit configuration diagram of a liquid crystal display device according to an embodiment.

2A and 2B are a plan view and a cross-sectional view showing a configuration of an embodiment in which the semiconductor display device according to the present embodiment is applied to a liquid crystal display device.

FIG. 3 is a schematic cross-sectional view illustrating a difference in structure between a driver region and a pixel region of the liquid crystal display device according to the above embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing procedure of the display device according to the embodiment.

FIG. 5 is a diagram schematically showing a multi-chamber.

FIG. 6 is a cross-sectional view showing the manufacturing procedure of the display device in the embodiment.

FIG. 7 is a schematic circuit configuration diagram of an EL display device according to the present embodiment.

FIG. 8 is a sectional view of a conventional liquid crystal display device.

[Explanation of symbols]

1, 101 ... Glass substrate, 3 ... Silicon nitride layer, 4 ... Silicon oxide layer, 10, 110 ... Polycrystalline silicon layer, 10
c, 110c ... Channel, 10d, 110d ... Drain, 10s, 110s ... Source, 11, 111 ... Insulating layer, 12, 112 ... Gate, 13, 21, 121 ... Electrode, 14, 113 ... Interlayer insulating film, 15 ... Gate Signal line,
16 ... Storage capacitance line, 20, 22, 31, 120, 131
... Contact hole, 23 ... Drain signal line, 30 ... Flattening layer, 40, 140 ... Pixel electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05B 33/02 H05B 33/14 A 33/10 33/22 Z 33/14 H01L 29/78 626C 33/22 619B 627G F term (reference) 2H091 FA34Y GA02 GA13 GA16 LA16 2H092 JA24 JB52 JB54 JB56 JB57 KA05 MA08 MA27 MA30 NA01 PA01 3K007 AB11 AB17 BB00 CA00 DB03 EA00 FA01 DB01 CA10 DB01 DB13 CA01 DB01 DB13 CA01 DA01 DB13 DA01 CA13 BA01 BA13 BA43 BA43 BA43 BA43 BA43 BA43 BA43 BA43 BA43 BA43 BA43 AA17 AA30 BB02 CC02 DD01 DD02 DD13 DD14 DD17 EE04 EE28 FF02 FF03 FF09 FF30 GG02 GG13 GG25 GG32.

Claims (12)

[Claims] 1. A semiconductor display device in which a polycrystalline semiconductor layer forming a driving element is provided above a light-shielding layer, wherein a blocking layer for suppressing diffusion of impurities is provided between the polycrystalline semiconductor layer and the light-shielding layer, and the polycrystalline semiconductor layer is provided. A semiconductor display device, wherein a crystalline semiconductor layer is formed on an insulating layer having a lower interface state with the polycrystalline semiconductor layer than the blocking layer. 2. The semiconductor display device according to claim 1, wherein the light-shielding layer is formed in a tapered shape in which an end portion thereof spreads toward the transparent substrate side. 3. The light shielding layer is applied with the same signal or a constant voltage as a scanning line for scanning a driving element formed above the light shielding layer. Semiconductor display device. 4. The insulating layer is made of silicon oxide, and the blocking layer is made of silicon nitride.
The semiconductor display device described. 5. A step of forming a light shielding layer on a transparent substrate, a step of forming a blocking layer that suppresses diffusion of impurities above the light shielding layer and the transparent substrate, and a step of forming a blocking layer above the blocking layer rather than the blocking layer. Forming an insulating layer having a low interface state with the polycrystalline semiconductor layer, forming an amorphous semiconductor layer on the insulating layer, and irradiating the amorphous semiconductor layer with light energy. And a step of polycrystallizing the semiconductor display device. 6. The method of manufacturing a semiconductor display device according to claim 5, wherein an end portion of the light shielding layer is formed in a tapered shape that spreads toward the transparent substrate side. 7. The light shielding layer is applied with the same signal or a constant voltage as a scanning line for scanning a driving element formed above the light shielding layer. Manufacturing method of semiconductor display device. 8. The method of manufacturing a semiconductor display device according to claim 5, wherein the step of forming the blocking layer to the step of forming the amorphous semiconductor layer are continuously performed in the same device. 9. The method of manufacturing a semiconductor display device according to claim 5, wherein silicon oxide is used as the insulating layer, and silicon nitride is used as the blocking layer. 10. A pixel region and a driver region are provided on the same substrate, a plurality of pixels are arranged in the pixel region, each pixel is provided with a pixel region transistor and a display element, and the driver region is the pixel region. An active matrix type display device comprising a plurality of driver region transistors for outputting a signal for driving each pixel, wherein both the pixel region transistor and the driver region transistor are made of the same material as an active layer. A blocking layer that suppresses diffusion of impurities is formed under the polycrystalline semiconductor layer of the pixel region transistor and the driver region transistor, the blocking layer being configured as a top gate type transistor on the substrate using a polycrystalline semiconductor. The polycrystalline semiconductor active layer, which is formed in contact with the semiconductor active layer, rather than the blocking layer. And an insulating layer having a low interface state between them are sequentially formed from the substrate side. Further, a light shielding layer is sandwiched between the insulating layer and the blocking layer below the polycrystalline semiconductor active layer of the pixel region transistor. An active matrix type display device characterized by being arranged. 11. The active matrix display device according to claim 10, wherein the light shielding layer has a tapered side surface that widens toward the substrate. 12. The light shielding layer is applied with the same signal or a constant voltage as a scanning line for scanning the pixel region thin film transistor formed above the light shielding layer. The active matrix display device described.