JP2003289674A - Inverter circuit and photovoltaic generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter circuit by which a variation in input current is effectively reduced without using a large-capacity capacitor, and a photovoltaic generator. <P>SOLUTION: Either of a transistor Q<SB>31</SB>and a transistor Q<SB>32</SB>is switched on and another is switched off according to the polarity of an AC current i<SB>ac</SB>. In a first mode, either of a transistor Q<SB>1</SB>and a transistor Q<SB>2</SB>is switched on according to the polarity of the AC current i<SB>ac</SB>, to make an exciting current flow to a transformer TR. In a second mode, when the on-state transistor is switched off, the current generated by exciting energy accumulated in the transformer TR is outputted from a secondary winding via a diode D<SB>31</SB>or a diode D<SB>32</SB>. When the exciting energy is exhausted and the current is cut off, the on- state diode is switched off. The first and second modes are repeated by a high frequency, and the low-frequency AC current i<SB>ac</SB>is outputted. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit that converts an input DC voltage into an AC current, and a system linkage type that converts a DC voltage generated in a photovoltaic cell into an AC current and outputs the AC current to a system line. The present invention relates to a photovoltaic power generation device.

[0002]

2. Description of the Related Art In recent years, interest in natural energy has been increasing as clean energy that does not deteriorate the environment. In particular, various studies have been conducted on solar power generation systems that can be easily used in urban areas.

In a general solar power generation system, the DC voltage of the photovoltaic cells connected in series is boosted DC / D.
A relatively high DC voltage (eg 20
Converted to 0VDC) and further converted by an inverter circuit to an AC voltage at the same level as the system line (for example, 100V).
It is converted into AC) and supplied to the electronic device that is a load.

However, since the power generated by the photovoltaic cell fluctuates greatly depending on the amount of received light, if the light receiving surface of the photovoltaic cell is covered by the shadow of a nearby building, utility pole, tree, etc., the generated power is significantly reduced. There is a problem.

In order to compensate for such fluctuations in generated power,
There is a known grid-connected photovoltaic power generation system that can supply power to a load in cooperation with a grid line that can stably supply power. A general grid-connected photovoltaic power generation system includes a photovoltaic cell and an inverter circuit that converts a DC voltage of the photovoltaic cell into an AC current and outputs the AC current to a grid line. The power generated by the photovoltaic cells is supplied to the load connected to the grid line via the inverter circuit, and even if the generated power fluctuates according to the amount of light received by the photovoltaic cells, the load does not Stable power is supplied from the line.

[0006] Here, in the solar power generation system described above
The available inverter circuit will be described. FIG. 23 shows
FIG. 3 is a circuit diagram showing a configuration of a general voltage type inverter circuit.
It In the inverter circuit shown in FIG. 23, the n-type MOS
Transistor Q_aSource and n-type MOS transistor Q
_bN-type MOS transistor connected in series with the drain of the
Langista Q_cSource and n-type MOS transistor Q_d
The drain is connected in series with the connected series circuit
ing. Furthermore, for the parallel circuit, the capacitor C
_inAre connected in parallel. Also, n-type MOS transistor
Dista Q_aAnd n-type MOS transistor Q_bConnection with
Inductor L₁One end is connected, the other
One end is the capacitor C_outThrough inductor L2
Connected to one end. The other end of inductor L2
Is an n-type MOS transistor Q _cAnd n-type MOS transistor
Star Q_dIt is connected to the connection node with.

In the above-described inverter circuit of FIG. 23, the DC input voltage v _in is applied to the capacitor C _in , and the AC output voltage v _out is output from both ends of the capacitor C _out . The control method of each transistor (Q _{a to} Q _d ) for generating the AC output voltage v _out includes:
There are several ways. For example, while the on state of each half cycle of the AC n-type MOS transistors Qn _a or n-type MOS transistors _{Q b,} and sets the other to the OFF state, n-type MOS transistor _{Q c} or n-type with a constant switching period There is a method of setting one of the MOS transistors Q _{d in} the on state and the other in the off state. By changing the ratio (duty ratio) of the period in which the n-type MOS transistor Q _c (or the n-type MOS transistor Q _d ) is in the ON state with respect to the switching cycle,
An AC output voltage v _out is obtained.

When the inverter circuit of FIG. 23 is applied to a grid-connected photovoltaic power generation system, a DC voltage generated in the photovoltaic cell is applied to the input (both ends of the capacitor C _in ) of the inverter circuit, and the inverter circuit is applied. Output (both ends of the capacitor C _out ) is connected to the system line. Then, the on / off state of each transistor is feedback-controlled so that the output current i _out is in phase with the voltage of the system line. As a result, the impedance of the system line viewed from the output of the inverter circuit becomes equivalent to the resistance load, and the power generated in the photovoltaic cell is injected into the system line via the inverter circuit.

FIG. 24 is a diagram showing waveforms of the output current i _out and the input current i _{in in} the inverter circuit of FIG. As shown in FIG. 24A, when a low frequency current, for example, an alternating current of about 50 Hz flows as the output current i _out, as shown in FIG. 24B, the input current i _in
A low frequency component having a frequency twice that of the output current is generated.

[0010]

On the other hand, the relationship between the current and the power with respect to the voltage of the photovoltaic cell has the relationship shown in FIG. 12 when the amount of received light is constant. FIG. 25 is a diagram showing a relationship between voltage and current and a relationship between voltage and power in a general photovoltaic cell. In FIG. 25, a curve CVa shows the relationship between voltage and current, and a curve CVb shows the relationship between voltage and power. The horizontal axis represents the voltage of the photovoltaic cell, and the vertical axis represents the current or power.

As shown in FIG. 25, since the electric power generated by the photovoltaic cell becomes maximum at the voltage V _max and the current I _max , the output of the photovoltaic cell is output in the inverter circuit at the next stage of the photovoltaic cell. The current is this current I _max
To match input current i _in and output current i
It is desirable to set _out .

However, as shown in FIG. 24B, in the inverter circuit of FIG. 23, since the input current i _in contains a low frequency component, the optimum current I _max that maximizes the power from the photovoltaic cell is obtained. Therefore, there is a problem that an error occurs periodically and the efficiency of power generation is reduced.

Therefore, in order to attenuate such a low frequency component of the input current i _in , normally, a capacitor C _in
A method of increasing the capacitance of is used. in this case,
Since a considerably large capacitance is required to attenuate a low frequency component of about 100 Hz, a large-capacity electrolytic capacitor or the like is used. However, the electrolytic capacitor is large in size and expensive, and has a problem of life in which the characteristics deteriorate with time.

Although a method of inserting a DC / DC converter between the photovoltaic cell and the inverter circuit is also common, this DC / DC converter also has a certain degree to attenuate the low frequency component of the input current. A large capacitance capacitor is required. Further, there is a problem that the power generation efficiency is lowered due to the power loss generated in the DC / DC converter, and a problem that the number of parts is increased and the cost is increased.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide an inverter circuit having a simpler structure and a photovoltaic device having such an inverter circuit. . A second object is to provide an inverter circuit that can effectively reduce the fluctuation of the input current without using a large-capacity capacitor, and a photovoltaic device having such an inverter circuit.

[0016]

In order to achieve the above object, an inverter circuit according to a first aspect of the present invention is an inverter circuit that converts an input DC voltage into an AC current, and includes a tap. A transformer including a first winding and a second winding, and connected in parallel to the first winding,
Input for inputting the DC voltage between the series circuit of the first switch and the second switch, the connection node of the first switch and the second switch, and the tap of the first winding. A terminal, an output terminal for the alternating current, a third switch inserted in series on a connection line between the second winding and the output terminal, and the first switch depending on the polarity of the alternating current. Or the second switch is selected, and in the first mode, the selected switch is turned on, the third switch is opened, and the second mode following the first mode is selected. In the mode, the control circuit opens the selected switch, turns on the third switch, and periodically repeats the control of the first mode and the second mode. Preferably, the third switch is the second switch.
In this mode, when the conduction current flowing from the second winding is cut off, the conduction state changes from the conduction state to the open state, and the control circuit changes from the second mode with the third switch opened. The mode shifts to the first mode.

According to the inverter circuit of the first aspect of the present invention, in the first mode, one of the first switch and the second switch is selected according to the alternating current. , The selected switch is set to the conductive state. As a result, the direct current is applied to the first winding or the second winding. At this time, since the third switch is in the open state, a current flows from the input terminal to the transformer, which causes excitation energy to be stored in the transformer. In the second mode following the first mode, when the switch selected in the first mode is set to the open state and the third switch is set to the conductive state, the transformer is turned on. The accumulated excitation energy is output as a current from the second winding through the third switch to the output terminal. Further, in the second mode, when the conduction current flowing from the second winding through the third switch is cut off and the third switch changes from the conduction state to the open state, the output Since the current flowing from the terminal to the second winding is blocked, both the first winding and the second winding are in a state where the current is cut off. In this state, from the second mode to the first mode
When the mode is changed to, the selected switch above
When the current is cut off, the open state is set to the conductive state. The alternating current is output from the output terminal by periodically repeating the control in the first mode and the control in the second mode.

A series circuit of a fourth switch and a fifth switch connected in parallel to the first winding,
A capacitor connected between a connection node of the fourth switch and the fifth switch and a tap of the first winding, and a current flowing from the first tap to the first winding. A current detection circuit for detecting, the control circuit has a third mode between the first mode and the second mode, and the fourth switch in the first mode. And the fifth switch are both opened, and when the detected value of the current detection circuit reaches the command value of the input current flowing through the input terminal, the first mode is switched to the third mode, In the third mode, all the first switch, the second switch, and the third switch are opened, and the comparison result between the command value of the input current and the command value of the alternating current, and AC power mentioned above Depending on the polarity, is made conductive one of the fourth switch or the fifth switch,
When the detected value of the current detection circuit reaches the command value of the alternating current, the third mode is transitioned to the second mode, and the fourth switch is made conductive in the second mode. Alternatively, the fifth switch may be opened. According to the inverter circuit having the above configuration, when the detected value of the current detection circuit reaches the command value of the input current flowing through the input terminal, the operation mode shifts from the first mode to the third mode. Therefore, the peak of the current flowing from the input terminal to the first winding is controlled according to the command value of the input current. In the third mode, when either one of the fourth switch and the fifth switch is set to the conductive state, the excitation energy accumulated in the first winding in the first mode is A part is transferred to the capacitor via the switch set to the conducting state, or the electrostatic energy stored in the capacitor is transferred to the first winding via the switch set to the conducting state. Transferred to the line. When the detected value of the current detection circuit reaches the command value of the alternating current, the operation mode is shifted from the third mode to the second mode, and the excitation energy accumulated in the transformer is converted into a current. Since it is output from the output terminal, the current output from the output terminal is controlled according to the command value of the alternating current.

The photovoltaic device according to the second aspect of the present invention is
A photovoltaic device comprising at least one photovoltaic cell and an inverter circuit for converting a voltage generated in the photovoltaic cell into an alternating current and outputting the alternating current to the grid line, wherein the inverter circuit includes a tap. A transformer including a first winding and a second winding; a series circuit of a first switch and a second switch connected in parallel to the first winding; An input terminal for inputting the DC voltage between the connection node of the switch and the second switch, and the tap of the first winding, an output terminal for the AC current, and the second winding. The third switch inserted in series on the connection line to the output terminal and either the first switch or the second switch is selected according to the polarity of the alternating current, and the first switch is selected. In the mode of
The selected switch is turned on and the third switch is connected.
And opening the selected switch in the second mode subsequent to the first mode and turning on the third switch to control the first mode and the second mode. And a control circuit that periodically repeats. Preferably, the third switch is
In the second mode, when the conduction current flowing from the second winding is cut off, the conduction state changes to the open state, and the control circuit causes the second switch to be opened when the third switch is opened. The mode is changed to the first mode.

Further, a series circuit of a fourth switch and a fifth switch connected in parallel to the first winding,
A capacitor connected between a connection node of the fourth switch and the fifth switch and a tap of the first winding, and a current flowing from the first tap to the first winding. A current detection circuit for detecting, the control circuit has a third mode between the first mode and the second mode, and the fourth switch in the first mode. And the fifth switch are both opened, and when the detected value of the current detection circuit reaches the command value of the input current flowing through the input terminal, the first mode is switched to the third mode, In the third mode, all the first switch, the second switch, and the third switch are opened, and the comparison result between the command value of the input current and the command value of the alternating current, and AC power mentioned above Depending on the polarity, is made conductive one of the fourth switch or the fifth switch,
When the detected value of the current detection circuit reaches the command value of the alternating current, the third mode is transitioned to the second mode, and the fourth switch is made conductive in the second mode. Alternatively, the fifth switch may be opened.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Two embodiments of the present invention will be described with reference to the drawings. <First Embodiment> FIG. 1 is a view showing an example of the outer appearance of a photovoltaic module according to the embodiment of the present invention. Panel P
N is a photovoltaic cell (not shown) or a connection device C for wiring the same.
N is a base for fixing the inverter circuit INV and the like, and has a flat box shape in the example of FIG.

Inside the box-shaped panel PN, a connecting device CN for connecting the wirings from the photovoltaic cells in series is provided.
The inverter circuit INV for converting the DC voltage of the photovoltaic cells connected in series by the connecting device CN into an AC current and outputting the AC current to the system line UL is fixed. Also panel P
One or a plurality of photovoltaic cells (not shown) are arranged on the surface of N opposite to the surface on which the connection device CN and the inverter circuit INV are fixed, with the light receiving surface facing outward.

FIG. 2 is a schematic block diagram showing a structural example of a photovoltaic system in which a plurality of photovoltaic modules shown in FIG. 1 are connected in parallel. In the example of FIG. 2, the current output terminals of the _n photovoltaic modules (MD _{1 to} MD _n ) are connected in parallel to the system line UL.
Further, the photovoltaic modules (MD _{1 to} MD _n ) each include one or a plurality of photovoltaic cells PV and an inverter circuit INV that converts a DC voltage thereof into an AC current. The connection device CN is not shown in FIG.

According to the photovoltaic system shown in FIG. 2, in each of the solar cell modules (MD _{1 to} MD _n ), the DC voltage of the photovoltaic cell PV is the inverter circuit INV.
Is converted into an alternating current by and output to the system line UL. As a result, the power generated by the photovoltaic modules (MD _{1 to} MD _n ) is supplied to the load connected to the grid line UL, and the generated power is generated by the photovoltaic cell PV.
Even if the load varies depending on the amount of received light, stable power is supplied to the load from the system line.

FIG. 3 shows an image according to the first embodiment of the present invention.
It is a schematic circuit diagram which shows the structural example of an inverter circuit. Figure
In 3, the code Q₁, Code Q_Two, Code Q₃₁And marks
Issue Q₃₂Indicates an n-type MOS transistor. Code D₃₁
And sign D₃₂Indicates a diode. Code SW₁Is
n-type MOS transistor Q₁And diode D₁Directly
3 shows a switch having a column circuit. Code SW_TwoIs an n-type M
OS transistor Q_TwoAnd diode D_TwoSeries circuit of
Shows a switch with. Code SW_ThreeIs an n-type MOS transistor
Langista Q₃₁, N-type MOS transistor Q_{Three Two}, Da
Iodo D₃₁, And diode D₃₂Sui with
Show the switch. Reference symbol TR indicates a transformer, and reference symbol W₁₁And
And code W₁₂Is its primary winding, and is denoted by the symbol W_TwoIs the second volume
Each line is shown. Reference numeral TP is the primary winding W₁₁
And primary winding W₁₂From the connection midpoint of the
Shows the Code C_iAnd symbol C_oIndicates a capacitor
You Reference numerals 1 to 3 denote n-type MOS transistor gates.
3 shows a drive circuit for inputting a drive voltage between a source and a source. Drive
The driving circuit 1 is an n-type MOS transistor Q₁Drive circuit 2
Is an n-type MOS transistor Q_TwoIn addition, the drive circuit 3 is an n-type M
OS transistor Q ₃₁And n-type MOS transistor
Q₃₂Input drive voltage to each. Reference numeral 4 is a system
Voltage v_ac2 shows a voltage detection circuit for detecting Reference numeral 5 is
A control circuit is shown. Code TN₁And code TN_TwoIs the light
Input terminal to which the voltage generated in the electric cell PV is input
Indicates a child. Code TN_ThreeAnd code TN_FourIs the grid line
The output terminal of the inverter circuit connected to UL is shown.

The connection relationship of the inverter circuit shown in FIG. 3 will be described. A switch SW is provided in parallel with the primary winding of the transformer TR.
A series circuit of ₁ and the switch SW ₂ is connected. In the example of FIG. 3, the switch SW ₁ is connected to one terminal of the primary winding W ₁₁ , the switch SW ₂ is connected to one terminal of the primary winding W ₁₂ , and the switch SW ₁ and the switch S
The connection point of W ₂ is connected to the input terminal TN ₂ . In the switch SW ₁ , the source of the n-type MOS transistor Q ₁ is connected to the anode of the diode D ₁ , and the drain of the n-type MOS transistor Q ₁ is connected to the primary winding W.
_{At 11} , the cathode of the diode D ₁ is connected to the output terminal TN ₂ , respectively. In the switch SW ₂ , the source of the n-type MOS transistor Q ₂ and the anode of the diode D ₂ are connected, the drain of the n-type MOS transistor Q ₂ is connected to the primary winding W ₁₂ , and the cathode of the diode D ₂ is connected to the output terminal. Connected to TN ₂ respectively.

One terminal of the secondary winding W ₂ has an n-type MOS.
It is connected to the output terminal TN ₃ via a series circuit of the transistor Q ₃₁ and the n-type MOS transistor Q _32, and the other terminal is connected to the output terminal TN ₄ . In the example of FIG. 3, the drain of the n-type MOS transistor Q ₃₁ is connected to the secondary winding W ₂ , the drain of the n-type MOS transistor Q ₃₂ is connected to the output terminal TN ₃ , and the n-type MOS transistor Q ₃₁ and The sources of the n-type MOS transistors Q ₃₂ are connected to each other. n-type MOS transistor Q
_A diode D ₃₁ is connected in parallel to the diode _{31 in} a forward direction from the source to the drain. n-type MOS
The diode D ₃₂ is also connected to the transistor Q ₃₂ in the forward direction from the source to the drain.
The capacitor C _i is connected between the input terminal TN ₁ and the input terminal TN ₂ , and the output terminal TN ₃ and the output terminal TN ₄ are connected.
A capacitor C _o is connected between them.

The control circuit 5 determines the n-type MOS transistor Q ₁ , the n-type MOS transistor Q ₂ , the n-type MOS transistor Q ₃₁ and the n-type MOS transistor Q ₃₂ according to the system voltage v _ac detected by the voltage detection circuit 4. By controlling the drive voltage of each of the
_ac and the in-phase output terminal of the alternating current _{i ac} of _(TN 3 -TN
₄ ) to output. That is, depending on the polarity of the alternating current i _ac , the n-type MOS transistor Q ₁ or the n-type MO transistor
One of the S-transistors Q ₂ is selected, and in the first mode, the selected n-type MOS transistor is made conductive and the switch SW ₃ is opened. First
In the second mode subsequent to the mode, the n-type MOS transistor made conductive in the first mode is opened and the switch SW ₃ is made conductive. Such a control of the first mode and the second mode by periodically repeated, to output a positive or negative current from the output terminal (TN 3 _{-TN 4).}

Here, the operation of the inverter circuit of FIG. 3 having the above-mentioned configuration and connection relationship will be described with reference to the drawings separately for the case where the system voltage v _ac is positive and the case where the system voltage v _ac is negative.

(V_ac> 0) FIG. 4 shows the system voltage v_acBut
Operation of the inverter circuit shown in FIG. 3 in the positive case
It is a diagram showing the state, the conduction state of each transistor is simplified
It has been shown as being transformed. In addition, FIG.
The waveform of each part of the inverter circuit and the conduction state of the transistor
FIG. System voltage v_acIs positive, it is shown in Figure 5D.
The n-type MOS transistor Q ₃₁Is always on
The n-type MOS transistor Q₃₂Is always
It is set to the dead state. Therefore, the current i of the secondary winding_TwoIs
Diode D₃₁Bypass diode D₃₂Through
Then flows to the output terminal. In addition, as shown in FIG.
MOS transistor Q_TwoIs always off and n
Type MOS transistor Q₁Is the operating mode (first mode
And on state or off state depending on the second mode)
Is set to.

That is, the n-type MOS transistor Q ₃₁
And n-type MOS switching transistor _{Q 3 2} In the system frequency (e.g., 50/60 Hz) is performed, n
Type MOS transistor Q ₁ and n type MOS transistor Q ₂ have a high frequency (for example, about 200 to 500 kHz).
Switching is performed.

First mode (period T ₁ ): n-type MOS transistor Q ₁ at the initial time point t ₁ of the _first mode
Is set from the off state to the on state. At this time, the DC voltage V of the input terminals (TN ₁ -TN ₂ ) is applied to the primary winding W _{11.
Since i} is applied, the current i ₁ increases linearly as shown in FIG. 5A.

Second mode (period T ₂ and period T ₃ ): n-type MOS transistor Q ₁ at time t ₂ .
Is set from the on state to the off state, the excitation energy accumulated in the primary winding W ₁₁ in the first mode is output as the current i ₂ from the secondary winding W ₂ . At this time, the diode D ₃₂ is forward biased and turned on as shown in FIG. 5E, and the current i ₂ flows to the output terminal via the diode D ₃₂ .

Further, as shown in Figure 5B, the current i ₂ of the secondary winding decreases with time in response to a decrease of the excitation energy stored in the transformer TR, the time the current i ₂ is zero t _{At 3} , the diode D ₃₂ changes from the on state to the off state. After the state in which the current i ₂ does not flow continues for the period T ₃ , one switching period T _s ends, and the operation mode shifts to the first mode again in the next switching period.

When the n-type MOS transistor Q ₁ switches from the off state to the on state at the time point t ₁ and when the diode D ₃₂ switches from the on state to the off state at the time point t ₃ , the current is zero. Since so-called zero current switching in which the conduction state is switched is realized, switching loss is effectively reduced in these elements.

(System voltage v _ac <0) FIG. 6 is a diagram showing the operating state of the inverter circuit shown in FIG. 1 when the system voltage v _ac is negative. The conduction state of each transistor is simplified. Shows. Further, FIG. 7 is a diagram showing the waveforms of the respective parts of the inverter circuit and the conduction states of the transistors in this case. When the system voltage _vac is negative,
Contrary to the case where the system voltage v _ac is positive, the n-type MOS transistor Q ₃₂ is always set to the ON state (FIG. 7D), n
The type MOS transistor Q ₃₁ is always set to the off state (FIG. 6). Therefore, the current i ₂ of the secondary winding bypasses the diode D ₃₂ and flows to the output terminal via the diode D ₃₁ . Further, as shown in FIG. 6, the n-type MOS transistor Q ₁ is always set to the off state,
Transistor Q ₂ is set to an on state or an off state according to the operation mode (first mode and second mode).

First mode (period T ₁ ): n-type MOS transistor Q ₂ at the initial time point t ₁ of the _first mode
Is set from the off state to the on state. At this time, the DC voltage V of the input terminals (TN ₁ -TN ₂ ) is applied to the primary winding W _{12.
Since i} is applied, the current i ₁ increases linearly (FIG. 7A).

Second mode (period T ₂ and period T ₃ ): n-type MOS transistor Q ₂ at time t ₂ .
Is set from the ON state to the OFF state, the excitation energy accumulated in the primary winding W ₁₂ in the first mode is output as the current i ₂ from the secondary winding W ₂ . At this time, the diode D ₃₁ is forward biased and turned on as shown in FIG. 7E, and the current i ₂ flows to the output terminal via the diode D ₃₁ .

The current i ₂ of the secondary winding decreases with time in accordance with the decrease of the excitation energy accumulated in the transformer TR, and at time t ₃ when the current i ₂ becomes zero, the diode D _{3 1} becomes Change from on state to off state. After the state in which the current i ₂ does not flow continues for the period T ₃ , one switching period T _s ends, and the operation mode shifts to the first mode again in the next switching period.

Even when the system voltage v _ac is negative, as in the above positive case, the n-type MOS transistor Q ₂
And since zero current switching is realized in the diode D ₃₁ , switching losses are effectively reduced.

Next, the relationship between the alternating current i _ac and the period T ₁ of the _first mode will be described. The peak current I ₁ of the current i ₁ at the end of the first mode is expressed by the following equation.

[0042]

[Equation 1]

However, in the equation (1), the code L ₁ is 1.
The self-inductance of the next winding W ₁₁ is shown. The current i ₂ flowing through the secondary winding W ₂ in the second mode is expressed by the following equation.

[0044]

[Equation 2]

However, in the equations (2) and (3), symbol I ₂ is the peak current of the current i ₂ flowing through the secondary winding, and symbol L ₂ is the self-inductance of the secondary winding L ₂ .
The symbol t indicates the elapsed time from the start of the second mode. The period T ₂ until the current i ₂ becomes zero from the peak current I ₂ is obtained by using the equation (2) as the following equation.

[0046]

[Equation 3]

The average value ia ₂ of the current i ₂ in the switching cycle T _s is obtained by the following equation using the equations (1) to (4).

[Equation 4]

Assuming that the system voltage v _ac can be expressed as a sine wave by a mathematical expression and the control circuit 5 can control the period T ₁ of the first mode in proportion to the system voltage V _ac . The following equation holds.

[0049]

[Equation 5]

However, the symbol V indicates the amplitude of the system voltage v _ac , and the symbol k indicates a constant satisfying 0 <k <1.
By substituting the equation (6) and the equation (7) into the equation (5), the alternating current ia _{ac obtained} by expanding the average value ia ₂ of the switching period T _s to the system period is expressed as the following equation. .

[0051]

[Equation 6]

As can be seen from equation (8), the first mode
Type MOS transistor Q in ₁Or n-type MOS
Transistor Q_TwoConduction period T₁Is the system voltage v_acTo
The output current i_ac
Is the system voltage v_acMake a sine wave similar to the waveform of
be able to.

As described above, the inverter circuit of FIG.
According to the road, the period T of the first mode ₁System voltage v_ac
Simple control that changes in proportion to_acTo
Similar sinusoidal output current i_acCan be easily obtained
Therefore, for example, the voltage type inverter circuit of FIG.
The negative feedback control to match the output current with the target value.
Simplify the circuit without special control circuit
You can

From the secondary winding W ₂ to the output terminal (TN ₃
The current i ₂ flowing to −TN ₄ ) is a current that is output as the excitation energy accumulated in the inductance of the transformer TR is released. Therefore, the current from this inductance is equivalently equivalent to the capacitor C _o and the output terminal ( TN ₃ −
It can be regarded as flowing into the TN ₄ ). Since this inductance has the effect of increasing the output impedance similarly to the inductor L ₁ of the smoothing filter in FIG. 23, it is not necessary to provide a smoothing inductor as in the voltage type inverter circuit of FIG. 23. Most of the high frequency ripple current included in the secondary winding current i ₂ flows to the capacitor C _out, and the harmonic distortion of the output current i _ac can be reduced. Therefore, it is possible to omit an inductance that is generally larger in size and expensive than other electronic components, and it is possible to reduce the size and cost of the device.

Further, according to the inverter circuit shown in FIG. 3, it is not necessary to boost the output voltage from the photovoltaic cell by using another DC / DC converter, and one converter can perform the boosting and the DC / AC conversion. Since they can be performed simultaneously, the circuit configuration can be simplified.

<Second Embodiment> A second embodiment will be described. In the second embodiment, a circuit for removing the ripple component of the system frequency contained in the input current of the inverter circuit is provided.

FIG. 8 is a schematic block diagram showing a configuration example of an inverter circuit according to the second embodiment of the present invention. 8 and FIG. 3 indicate the same components. Further, in FIG. 8, the symbols Q ₄ and Q ₅ are n-type MO.
Reference numerals D ₄ and D ₅ denote S-transistors and diodes, respectively. Reference numeral SW ₄ represents a switch having a parallel circuit of an n-type MOS transistor Q ₄ and a diode D ₄ . Reference numeral SW ₅ is an n-type MOS transistor Q
₅ shows a switch with a parallel circuit of ₅ and diode D ₅ . Reference symbol C _s indicates a capacitor. Reference numeral 5'denotes a control circuit. Reference numeral 6 indicates a drive circuit for the n-type MOS transistor Q ₄ , and reference numeral 7 indicates a drive circuit for the n-type MOS transistor Q ₅ . Reference numeral 8 indicates a current detection circuit that detects a current flowing from the tap TP to the primary winding.

The connection relationship of the inverter circuit shown in FIG. 8 will be described. A switch SW is provided in parallel with the primary winding of the transformer TR.
₄ and the switch SW ₅ are connected in series. In the example of FIG. 3, the switch SW ₄ is connected to one terminal of the primary winding W ₁₁ , the switch SW ₅ is connected to one terminal of the primary winding W ₁₂ , and the switch SW ₄ and the switch S
The connection point of W ₅ is connected to the input terminal TN ₁ via the capacitor C _s.
Connected to. A diode D ₄ is connected in parallel to the n-type MOS transistor Q ₄ of the switch SW _{4 in} the forward direction from the source to the drain, and the source thereof is 1
The drain of the next winding W ₁₁ is connected to the capacitor C _s . A diode D ₅ is connected in parallel to the n-type MOS transistor Q ₅ of the switch SW _{5 in} the forward direction from the source to the drain, and the source is connected to the primary winding W 5.
_{At 12} , the drain is connected to the capacitor C _s , respectively. The capacitor C _i is connected between the input terminal TN ₁ and the input terminal TN ₂ .

The rest of FIG. 8 is the same as that of FIG. 3 already explained, and therefore the explanation is omitted here.

The control circuit 5'describes the n-type MOS transistor Q ₁ and the n-type MOS transistor in accordance with the system voltage v _ac detected by the voltage detection circuit 4 and the primary winding current i ₁ detected by the current detection circuit 8. Q ₂ , n-type MOS
The drive voltage of each of the transistor Q ₄ , the n-type MOS transistor Q ₅ , the n-type MOS transistor Q _31, and the n-type MOS transistor Q ₃₂ is controlled to control the system voltage v.
_ac and the in-phase output terminal of the alternating current _{i ac} of _(TN 3 -TN
₄ ) to output. At that time, since the peak current of the input current I _i is controlled to be kept at a constant level corresponding to the command value i _dc ^* of the input current I _i, the component of the system frequency contained in the input current I _i is reduced To be done.

That is, either the n-type MOS transistor Q ₁ or the n-type MOS transistor Q ₂ is selected according to the polarity of the alternating current i _ac , and the selected n-type MOS transistor is made conductive in the first mode. At the same time, the switch SW ₃ is opened. In the second mode, the n-type MOS transistor made conductive in the first mode is opened and the switch SW ₃ is made conductive. These controls are similar to those of the control circuit 5 of FIG. 3 described above.

Further, the control circuit 5'has a first mode and a second mode.
It has a third mode between the second mode and the first mode.
In mode, switch SW_FourAnd switch SW₅
Are opened together, and the detected value of the current detection circuit 8 is the input current.
I_iCommand value i_dc ^*When the first mode is reached
To the third mode. In the third mode,
Switch SW₁, Switch SW_Two, And switch SW_Three
And open the input current I_iCommand value i
_dc ^*And AC current i _acCommand value i_ac ^*Comparison with
And the AC current i_acSwitch depending on the polarity of
SW_FourOr switch SW₅Conduct one of the
The detection value of the current detection circuit 8 is the alternating current i_acCommand value i
_ac ^*From the third mode to the second mode
Move to. In the second mode, the third mode
Switch SW made conductive by switch_FourOr switch SW₅To
Let it open.

Here, the above-described configuration and connection relationship are provided.
The operation of the inverter circuit of FIG._acof
Polarity (positive or negative) and alternating current i_acCommand value i
_ac ^*And input current I_iCommand value i_dc ^*Relationship with
The four cases will be described separately.

(V _ac > 0 and i _ac ^* <
i _dc ^* ) First, the operation when the system voltage v _ac is positive will be described. 9 to 12 are diagrams showing the operating state of the inverter circuit of FIG. 8 when the system voltage v _ac is positive, and show the conducting state of each transistor in a simplified manner. FIG. 13 is a diagram showing the waveform of each part of the inverter circuit and the conduction state of the transistors in this case.
When the system voltage v _ac is positive and the command value i _ac ^* of the alternating current i _ac is smaller than the command value i _dc ^* of the input current I _i , the n-type MOS transistor Q ₂ and the n-type MOS transistor
The transistor Q ₃₂ is set to the off state in all modes. The n-type MOS transistor Q ₁ is set to the ON state in the first mode and the OFF state in the other modes. The n-type MOS transistor Q ₃₁ is set to the on state in the second mode and the off state in the other modes. The n-type MOS transistor Q ₄ is set to the off state at least in the first mode and the second mode. In the third mode, the diode D ₄ is in the on state, so it may be set to either the off state or the on state. The n-type MOS transistor Q ₅ is set to the off state in all modes.

First mode (period T ₁ ): n-type MOS transistor Q ₁ at the initial time point t ₁ of the _first mode
Is set from the off state to the on state, and the n-type M
The OS transistor Q ₃₁ is set to the off state.

As shown in FIG. 9, since the DC voltage V _i of the input terminals (TN ₁ -TN ₂ ) is applied to the primary winding W ₁₁ , the current i ₁ is linear as shown in FIG. 13B. Increase. Note that FIG. 13A virtually shows the exciting current i _{TR of the} entire transformer TR in order to facilitate understanding of the excited state of the transformer TR, and an actual current flowing through each terminal of the transformer TR. Becomes discontinuous as shown in FIGS. 13B and 13D.

Third mode (period T ₄ ): When the current i ₁ reaches the command value i _dc ^* of the input current I _i (time point t ₄ ), the operation mode shifts from the first mode to the third mode. To be done. In the third mode, the n-type MOS transistor Q ₁ is set from the on state to the off state.

At this time, the current flowing through the primary winding W ₁₁ in the first mode is changed to the diode D as shown in FIG.
₄ through the flow into the capacitor _{C s,} the capacitor _{C s}
Electrostatic energy is stored in. This reduces the excitation energy stored in the transformer TR in the first mode, and the current i ₁ decreases linearly with time as shown in FIG. 13B.

Second mode (period T ₂ and period T ₃ ): When the decreasing current i ₁ in the third mode reaches the command value i _ac ^* of the alternating current i _ac (time point t ₂ ), the operation mode is changed. A transition is made from the third mode to the second mode. In the second mode, the n-type MOS transistor Q ₃₁ is set from the off state to the on state.

N-type MOS transistor Q₃₁Is on
Then, the capacitor C_sIs the diode D_Four, Transformer T
R and diode D₃₂Output terminal (TN_Three−
TN _Four) And is connected in parallel. Change of transformer TR
Considering the pressure ratio, the capacitor C_sVoltage v_csInteract with
Voltage v_acThe voltage v_csPeople interact
Voltage v_acFor larger size, diode D_FourIs o
F state, diode D ₃₂Turns on, and
As shown, the secondary winding W_TwoTo output terminal i_TwoFlow
Be done.

As the excitation energy accumulated in the transformer TR decreases, the current i ₂ of the secondary winding W ₂ decreases with time as shown in FIG. 13D, and when this current i ₂ becomes zero. At t ₃ , the diode D ₃₂ changes from the on state to the off state. After the state in which the current i ₂ does not flow continues for the period T ₃ , one switching period T _s ends and the next switching period starts.

(V _ac > 0 and i _ac ^* >
i _dc ^* ) when the system voltage v _ac is positive and the command value i _ac ^* of the alternating current i _ac is the command value i _{dc of the} input current I _i
If it is larger than ^* , the n-type MOS transistor Q ₂ and the n-type MOS transistor Q ₃₂ are set to the off state in all modes. The n-type MOS transistor Q ₁ is set to the ON state in the first mode and the OFF state in the other modes. The n-type MOS transistor Q ₃₁ is
The second mode is set to the on state, and the other modes are set to the off state. The control of these transistors is
This is the same as the above case (i _ac ^* <i _dc ^* ).

On the other hand, the n-type MOS transistor Q ₄
Is set to the off state in all modes. The n-type MOS transistor Q ₅ is set to the on state in the third mode and the off state in the other modes.

First mode (period T ₁ ′): At the initial time point t ₁ ′ of the _first mode, the n-type MOS transistor Q ₁ is set from the off state to the on state as shown in FIG. The n-type MOS transistor Q ₃₁ is set to the off state. Since the input voltage V _i is applied to the primary winding W ₁₁ , the current i ₁ linearly increases as shown in FIG. 13B.

Third mode (period T ₄ ′): When the current i ₁ reaches the command value i _dc ^* of the input current I _i (time point t ₄ ′), the operation mode changes from the first mode to the third mode. Will be moved to. In the third mode, the n-type MOS transistor Q ₁ is set from the on state to the off state, and the n-type MOS transistor Q ₅ is set from the off state to the on state.

[0076] In this case, the capacitor C to the primary winding _{W 12
When} the voltage v _{cs of s} is applied, the discharge current of the capacitor C _s flows as shown in FIG. The polarity of the current i ₁ flowing from the tap TP to the transformer TR is opposite to the polarity in the first mode as shown in FIG.
The exciting current i _TR of R has the same polarity as that in the first mode, and as shown in FIG. 13A, the exciting current i _TR
Increases with time. That is, a portion of the stored electrostatic energy in the capacitor C _s is converted back to the excitation energy is accumulated in the transformer TR.

Second mode (period T_TwoAnd period
T_Three): Current i increasing in the negative direction in the third mode
₁Is the alternating current i_acNegative polarity command value-i_ac ^*Reached
Then (time t_Two'), The operation mode is from the third mode
The mode is changed to the second mode. In the second mode, n
Type MOS transistor Q ₅Is set from on to off
N-type MOS transistor Q_{Three 1}Is o
It is set to the ON state from the OFF state.

N-type MOS transistor Q₃₁Is on
Then, the capacitor C_sIs the diode D_Four, Transformer T
R and diode D₃₂Output terminal (TN_Three−
TN _Four) And is connected in parallel. Change of transformer TR
Considering the pressure ratio, the capacitor C_sVoltage v_csInteract with
Voltage v_acThe voltage v_csPeople interact
Voltage v_acFor larger size, diode D_FourIs o
F state, diode D ₃₂Turns on, and
As shown, the secondary winding W_TwoTo output terminal i_TwoFlow
Be done. To reduce the excitation energy accumulated in the transformer TR
Depending on the secondary winding W_TwoCurrent i_TwoAs shown in Figure 13D
This current i decreases with time_TwoWhen is zero
Point t_Three'And diode D₃₂From on state to off state
Change. This current i _TwoAfter the state of no flow continues,
The next switching period begins.

(V _ac <0 and i _ac ^* <
i _dc ^* ) Next, the operation when the system voltage v _ac is negative will be described. 14 to 17 are diagrams showing the operating states of the inverter circuit shown in FIG. 8 when the system voltage v _ac is negative, and show the conducting states of the respective transistors in a simplified manner. FIG. 18 is a diagram showing the waveform of each part of the inverter circuit and the conduction state of the transistors in this case. When the system voltage v _ac is negative and the alternating current i
the command value of the command value _{i ac} ^* is input current _{I i} of _{ac i dc} ^*
If smaller, n-type MOS transistors Q ₁ and n
The type MOS transistor Q ₃₁ is set to the off state in all modes. The n-type MOS transistor Q ₂ has a first
In this mode, it is set to the on state, and in other modes it is set to the off state. The n-type MOS transistor Q ₃₂ is set to the on state in the second mode and the off state in the other modes. The n-type MOS transistor Q ₅ is set to the off state at least in the first mode and the second mode. In the third mode, since the diode D ₅ is turned on, it may be set to either the off state or the on state. n-type MOS transistor Q
₄ is set to the off state in all modes.

First mode (period T ₁ ): n-type MOS transistor Q ₂ at the initial time point t ₁ of the _first mode
Is set from the off state to the on state, and the n-type M
OS transistor _{Q 32} is set to the off state.

Since the DC voltage V _i is applied to the primary winding W ₁₂ as shown in FIG. 14, the current i ₁ increases linearly as shown in FIG. 18B. Note that FIG. 18A shows
The exciting current i _TR of the entire transformer TR is limited to showing virtually, in accordance with the polarity of the secondary winding current i _2, shows the polarity of exciting current i _TR reversed in FIG 13A.

Third mode (period T ₄ ): When the current i ₁ reaches the command value i _dc ^* of the input current I _i (time point t ₄ ), the operation mode shifts from the first mode to the third mode. To be done. In the third mode, the n-type MOS transistor Q ₂ is set from the on state to the off state.

At this time, the current flowing through the primary winding W ₁₂ in the first mode is changed to the diode D as shown in FIG.
₅ through the flow into the capacitor _{C s,} the capacitor _{C s}
Electrostatic energy is stored in. As a result, the excitation energy stored in the transformer TR in the first mode decreases, and the current i ₁ decreases linearly with time as shown in FIG. 18B.

Second mode (period T ₂ and period T ₃ ): When the decreasing current i ₁ in the third mode reaches the command value i _ac ^* of the alternating current i _ac (time point t ₂ ), the operation mode is changed to A transition is made from the third mode to the second mode. In the second mode, the n-type MOS transistor Q ₃₂ is set from the off state to the on state.

N-type MOS transistor Q₃₂Is on
Then, the capacitor C_sIs the diode D₅, Transformer T
R and diode D₃₁Output terminal (TN_Three−
TN _Four) And is connected in parallel. Change of transformer TR
Considering the pressure ratio, the capacitor C_sVoltage v_csInteract with
Voltage v_acThe voltage v_csPeople interact
Voltage v_acFor larger size, diode D₅Is o
F state, diode D ₃₁Turns on, and
As shown, output terminal to secondary winding W_TwoCurrent i_TwoFlow
Be done.

As the excitation energy accumulated in the transformer TR decreases, the current i ₂ of the secondary winding W ₂ decreases with time as shown in FIG. 18D, and when this current i ₂ becomes zero. At t ₃ , the diode D ₃₁ changes from the on state to the off state. After the state in which the current i ₂ does not flow continues for the period T ₃ , one switching period T _s ends and the next switching period starts.

(V _ac <0 and i _ac ^* >
i _dc ^* ) When the system voltage v _ac is negative and the command value i _ac ^* of the alternating current i _ac is the command value i _{dc of the} input current I _i
^{When it is} larger than ^* , the n-type MOS transistor Q ₁ and the n-type MOS transistor Q ₃₁ are set to the off state in all modes. The n-type MOS transistor Q ₂ is set to the ON state in the first mode and the OFF state in the other modes. The n-type MOS transistor Q ₃₂ is
The second mode is set to the on state, and the other modes are set to the off state. The control of these transistors is
This is the same as the above case (i _ac ^* <i _dc ^* ).

On the other hand, the n-type MOS transistor Q ₅
Is set to the off state in all modes. The n-type MOS transistor Q ₄ is set to the on state in the third mode and the off state in the other modes.

First mode (period T ₁ ′): At the initial time point t ₁ ′ of the _first mode, the n-type MOS transistor Q ₂ is set from the off state to the on state, and n
The type MOS transistor Q ₃₂ is set to the off state.
Since the DC voltage V _i is applied to the primary winding W ₁₂ , the current i ₁ linearly increases as shown in FIG. 18B.

Third mode (period T ₄ ′): When the current i ₁ reaches the command value i _dc ^* of the input current I _i (time point t ₄ ′), the operation mode changes from the first mode to the third mode. Will be moved to. In the third mode, the n-type MOS transistor Q ₂ is set from the on state to the off state, and the n-type MOS transistor Q ₄ is set from the off state to the on state.

At this time, a capacitor C is provided on the primary winding W _11.
When the voltage v _{cs of s} is applied, the discharge current of the capacitor C _s flows as shown in FIG. The polarity of the current i ₁ flowing from the tap TP to the transformer TR is opposite to the polarity in the first mode as shown in FIG. 18B, but the transformer T
The exciting current i _TR of R has the same polarity as in the first mode, and as shown in FIG. 18A, the exciting current i _TR
Increases with time. That is, a portion of the stored electrostatic energy in the capacitor C _s is converted back to the excitation energy is accumulated in the transformer TR.

Second mode (period T_TwoAnd period
T_Three): Current i increasing in the negative direction in the third mode
₁Is the alternating current i_acNegative polarity command value-i_ac ^*Reached
Then (time t_Two'), The operation mode is from the third mode
The mode is changed to the second mode. In the second mode, n
Type MOS transistor Q _FourIs set from on to off
N-type MOS transistor Q_{Three Two}Is o
It is set to the ON state from the OFF state.

N-type MOS transistor Q₃₂Is on
Then, the capacitor C_sIs the diode D₅, Transformer T
R and diode D₃₁Output terminal (TN_Three−
TN _Four) And is connected in parallel. Change of transformer TR
Considering the pressure ratio, the capacitor C_sVoltage v_csInteract with
Voltage v_acThe voltage v_csPeople interact
Voltage v_acFor larger size, diode D₅Is o
F state, diode D ₃₁Turns on, and
As shown, output terminal to secondary winding W_TwoCurrent i_TwoFlow
Be done. To reduce the excitation energy accumulated in the transformer TR
Depending on the secondary winding W_TwoCurrent i_TwoAs shown in Figure 18D
This current i decreases with time_TwoWhen is zero
Point t_Three'And diode D₃₂From on state to off state
Change. This current i _TwoAfter the state of no flow continues,
The next switching period begins.

As described above, according to the above-described inverter circuit of FIG. 8, the peak current of the input current I _i is controlled to be a constant level as shown in FIGS. 13C and 18C. That is, since the ripple current included in the input current I _i mostly has a high frequency component associated with switching and does not include a low frequency component corresponding to the system frequency, the capacitance of the capacitor C _i is A relatively small electrostatic capacitance is sufficient, which has a sufficiently low impedance for a high frequency ripple current. That is, FIG.
The capacitance of the input capacitor can be made very small as compared with the case where it is necessary to reduce the ripple current of low frequency as in the above inverter circuit. Since the capacitance of the capacitor can be reduced, it is possible to replace a large volume capacitor such as an electrolytic capacitor used in a conventional inverter circuit with a small volume capacitor such as a film capacitor, thereby reducing the size of the device and The weight can be reduced. Further, since the problem of the life peculiar to the electrolytic capacitor can be avoided, the failure occurrence rate of the device can be reduced.

<Simulation Example> An example of the simulation performed on the above-described inverter circuit of FIG. 8 will be described. Table 1 below shows the values of the respective circuit constants set in the simulation.

[0096]

[Table 1]

However, the inductor L _o is the capacitor C
and an inductor (not shown) is inserted into the connection line between the _o and the system line, the filter configured to smooth the output current i _ac inverter circuit by the inductor L _o a capacitor C _o.

FIG. 19 is a diagram showing simulation results of waveforms of respective parts of the inverter circuit in the case where the operation mode has the first mode and the second mode, as in the above-described inverter circuit of FIG. As can be seen from FIG. 19A, the peak value of the primary winding current i ₁ is as shown in FIG.
A rectified sine wave obtained by full-wave rectifying the system voltage v _{ac of} D is drawn. The peak value of the secondary winding current i ₂ is
As shown in FIG. 19B, a sine wave similar to the system voltage v _ac is drawn. Therefore, the alternating current i _ac output from the inverter circuit to the system line has a sine wave similar to the system voltage v _{ac as} shown in FIG. 19C.

FIG. 20 is an enlarged view of a part of the simulation result of FIG. 19 on the time axis. As can be seen from FIGS. 20A and 20B, the primary winding current i ₁ increases linearly in the first mode,
When the peak value corresponding to the command value i _dc ^* is reached,
The primary winding current i ₁ is transferred to the secondary winding current i ₂ .
The current i ₂ of the current i ₁ and the secondary winding of the primary winding is discontinuous, the zero current switching is realized in the n-type MOS transistors Q ₁ and n-type MOS transistor Q ₂ I understand.

FIG. 21 shows an example of the output current waveform of the inverter circuit observed in the experiment. As can be seen from FIG. 21, the output current of the inverter circuit is controlled to have a sine wave except for the zero cross period. The waveform distortion that occurs in the zero-cross period is caused by an error in the pulse width in the control circuit, and a drive circuit that can drive the n-type MOS transistor Q ₁ and the n-type MOS transistor Q ₂ at a higher speed is used. It can be improved by using or adding a circuit for performing feedback control of the output current.

FIG. 22 is a diagram showing a simulation result of the waveform of each part of the inverter circuit in the case where the third mode is provided between the first mode and the second mode.
As can be seen by comparing FIG. 22B and FIG. 19A, the peak current value of the primary winding current i ₁ becomes constant due to the above-described control in which the third mode is provided, and the system frequency included in FIG. The component has been removed in Figure 22B. Therefore, as shown in FIG. 22A, the input current I _dc of the inverter circuit is a constant current that does not include the system frequency component.

On the other hand, the voltage V _{cs of the} capacitor C _s
Contains a ripple voltage component having a frequency twice as high as the system frequency, and its amplitude is as high as 40 V _pp as shown in FIG. 22D. In this way, the ripple current of the system frequency almost flows into the capacitor C _s ,
The flow into the input capacitor C _i is prevented. Even if such a large ripple voltage is generated in the capacitor C _s , the input voltage and the current of the inverter circuit are not affected by this ripple voltage, so that the capacitance of the capacitor C _s is
For example, like 50μF in this simulation,
It can be set to a relatively small value.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made. For example, the switch used in the inverter circuit may be composed of an n-type MOS transistor and a diode as shown in FIGS. 3 and 8, or may be composed of another semiconductor switch (for example, an IGBT or a thyristor). Is also possible.

In the third mode in which the diode D ₄ or the diode D ₅ in FIG. 8 is in a conducting state, a transistor (n-type M
OS transistor Q ₄ , n-type MOS transistor Q ₅ )
May remain in the off state, but it may be controlled in the on state to reduce the conduction loss of the diode.

[0105]

According to the present invention, firstly, the structure can be simplified, and the size and cost can be reduced. Secondly, the ripple component of the system frequency included in the input current of the inverter circuit can be effectively reduced without using a large-capacity capacitor.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of an external appearance of a photovoltaic module according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a configuration example of a photovoltaic system in which a plurality of photovoltaic modules shown in FIG. 1 are connected in parallel.

FIG. 3 is a schematic circuit diagram showing a configuration example of an inverter circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an operating state of the inverter circuit of FIG. 1 when the system voltage is positive.

5 is a diagram showing waveforms of respective parts of the inverter circuit shown in FIG. 1 and conduction states of transistors when the system voltage is positive.

FIG. 6 is a diagram showing an operating state of the inverter circuit of FIG. 1 when the system voltage is negative.

FIG. 7 is a diagram showing waveforms of respective parts of the inverter circuit shown in FIG. 1 and conduction states of transistors when the system voltage is negative.

FIG. 8 is a schematic circuit diagram showing a configuration example of an inverter circuit according to a second embodiment of the present invention.

9 is a diagram showing an operation state in the first mode of the inverter circuit shown in FIG. 8 when the system voltage is positive.

10 is a diagram showing an operating state in a third mode of the inverter circuit shown in FIG. 8 when the system voltage is positive and the output current command value is smaller than the input current command value.

11 is a diagram showing an operating state in a second mode of the inverter circuit shown in FIG. 8 when the system voltage is positive.

12 is a diagram showing an operating state in a third mode of the inverter circuit shown in FIG. 8 when the system voltage is positive and the output current command value is larger than the input current command value.

13 is a diagram showing waveforms at various parts of the inverter circuit shown in FIG. 3 and conduction states of transistors when the system voltage is positive.

FIG. 14 is a diagram showing an operating state in the first mode of the inverter circuit shown in FIG. 8 when the system voltage is negative.

15 is a diagram showing an operating state in a third mode of the inverter circuit shown in FIG. 8 when the system voltage is negative and the output current command value is smaller than the input current command value.

16 is a diagram showing an operating state in the second mode of the inverter circuit shown in FIG. 8 when the system voltage is negative.

17 is a diagram showing an operating state in a third mode of the inverter circuit shown in FIG. 8 when the system voltage is negative and the output current command value is larger than the input current command value.

FIG. 18 is a diagram showing waveforms at various parts of the inverter circuit shown in FIG. 3 and conduction states of transistors when the system voltage is negative.

FIG. 19 is a diagram showing a result of simulation of waveforms at various parts of the inverter circuit in the case where the operation mode has the first mode and the second mode.

20 is a diagram showing an enlarged part of the simulation result of FIG. 19 on the time axis.

FIG. 21 shows an example of the output current waveform of the inverter circuit observed in the experiment.

FIG. 22 is a diagram showing simulation results of waveforms of various parts of the inverter circuit when the third mode is provided between the first mode and the second mode.

FIG. 23 is a circuit diagram showing a configuration of a general voltage type inverter circuit.

FIG. 24 is a diagram showing waveforms of an output current and an input current in the inverter circuit of FIG. 23.

FIG. 25 is a diagram showing a relationship between voltage and current and a relationship between voltage and power in a general solar cell.

[Explanation of symbols]

1-3, 6, 7, ... Drive circuit, 4 ... Voltage detection circuit, 5,
5 '... control circuit, 8 ... current detection _circuit, Q 1 _{to Q 32} ... n
Type MOS transistor, D _{1 to} D ₃₂ ... Diode, C
_i , C _s , C _o ... Capacitor, L _o ... Inductor, TR
... _{transformer, W 11,} W ₁₂ ... 1 winding, _{W 2} ... 2 windings, _SW 1 to SW 5 _... switch, _TN 1 ~TN 4 _... terminal, PN ... panel, CN ... connecting device, PV ... Photovoltaic cell, INV ... Inverter circuit.

Continued front page    (72) Inventor Mutsuo Ishikawa             No.12, No.12, 3-52, Ikebukuro, Toshima-ku, Tokyo             Electric Co., Ltd. (72) Inventor Kiyoto Yasui             No.12, No.12, 3-52, Ikebukuro, Toshima-ku, Tokyo             Electric Co., Ltd. F term (reference) 5H007 AA02 AA08 BB07 CA02 CB05                       CB06 CC07 CC32 DA03 DB01                       EA02

Claims (16)

[Claims] 1. An inverter circuit for converting an input DC voltage into an AC current, comprising: a transformer including a first winding having a tap and a second winding; A series circuit of a first switch and a second switch connected in parallel to the winding, a connection node of the first switch and the second switch, and a tap of the first winding. An input terminal for inputting the DC voltage between them, an output terminal for the AC current, a third switch inserted in series on the connection line between the second winding and the output terminal, and the AC current Depending on the polarity of the above, either one of the first switch or the second switch is selected, and in the first mode, the selected switch is made conductive and the third switch is opened, and In the second mode following the first mode An inverter circuit having a control circuit for opening the selected switch, turning on the third switch, and periodically repeating the control in the first mode and the second mode. 2. The third switch changes from a conduction state to an open state when the conduction current flowing from the second winding is cut off in the second mode, and the control circuit is configured to The inverter circuit according to claim 1, wherein the second mode shifts to the first mode in a state where the switch of No. 3 is opened. 3. The third switch includes a first diode and a second diode which are inserted in opposite directions on a connection line between the second winding and the output terminal, and the first switch. A first semiconductor switch connected in parallel to the diode; and a second semiconductor switch connected in parallel to the second diode, wherein the control circuit is configured to operate in accordance with the polarity of the alternating current. The inverter circuit according to claim 2, wherein one of the first semiconductor switch and the second semiconductor switch is made conductive. 4. A series circuit of a fourth switch and a fifth switch connected in parallel to the first winding, a connection node of the fourth switch and the fifth switch, and A capacitor connected between the first winding and the tap of the first winding; and a current detection circuit that detects a current flowing from the first tap to the first winding. A third mode is provided between the first mode and the second mode, and in the first mode, the fourth switch and the fifth switch are both opened to detect the current detection circuit. When the value reaches the command value of the input current flowing through the input terminal, the first
Mode to the third mode, and in the third mode, the first switch, the second switch,
And the third switch is opened, and the fourth switch or the fifth switch is opened depending on the result of comparison between the command value of the input current and the command value of the alternating current, and the polarity of the alternating current. One of the switches is turned on, and when the detected value of the current detection circuit reaches the command value of the alternating current, the third mode is shifted to the second mode, and the second mode is changed. The inverter circuit according to claim 1 or 2, wherein the fourth switch or the fifth switch which is made conductive is opened. 5. The inverter circuit according to claim 4, wherein each of the fourth switch and the fifth switch includes a parallel circuit of a diode and a semiconductor switch. 6. The fourth switch according to the comparison result of the command value of the input current and the command value of the alternating current in the third mode, and the polarity of the alternating current in the third mode. Alternatively, the inverter circuit according to claim 5, wherein any one of the semiconductor switches of the fifth switches is made conductive. 7. The fourth switch according to the comparison result of the command value of the input current and the command value of the alternating current in the third mode, and the polarity of the alternating current in the third mode. The inverter circuit according to claim 5, wherein one of the semiconductor switches of the fifth switches is made conductive, or both of the semiconductor switches are opened. 8. The inverter circuit according to claim 4, wherein each of the first switch and the second switch includes a series circuit of a diode and a semiconductor switch. 9. A photovoltaic device comprising at least one photovoltaic cell and an inverter circuit for converting a voltage generated in the photovoltaic cell into an alternating current and outputting it to a system line, wherein the inverter circuit comprises: A transformer including a first winding provided with a tap and a second winding, and a series circuit of a first switch and a second switch connected in parallel to the first winding. An input terminal for inputting the DC voltage between a connection node of the first switch and the second switch, and a tap of the first winding; an output terminal for the AC current; A third switch inserted in series on the connection line between the second winding and the output terminal, and either the first switch or the second switch depending on the polarity of the alternating current. Select and in the first mode The selected switch is made conductive, the third switch is opened, and the selected switch is opened and the third switch is made conductive in a second mode following the first mode. A photovoltaic device comprising: a control circuit that periodically repeats control of the first mode and the second mode. 10. The third switch changes from a conducting state to an open state when the conducting current flowing from the second winding is cut off in the second mode, and the control circuit is configured to The photovoltaic device according to claim 9, wherein the second mode shifts to the first mode in a state where the switch of No. 3 is opened. 11. The third switch includes a first diode and a second diode inserted in opposite directions on a connection line between the second winding and the output terminal, and the first switch. A first semiconductor switch connected in parallel to the diode; and a second semiconductor switch connected in parallel to the second diode, wherein the control circuit is configured to operate in accordance with the polarity of the alternating current. The photovoltaic device according to claim 10, wherein one of the first semiconductor switch and the second semiconductor switch is made conductive. 12. A parallel connection to the first winding,
A series circuit of a fourth switch and a fifth switch; a capacitor connected between a connection node of the fourth switch and the fifth switch; and a tap of the first winding; A current detection circuit for detecting a current flowing from the first tap to the first winding, wherein the control circuit sets a third mode between the first mode and the second mode. In the first mode, when the fourth switch and the fifth switch are both opened, and the detected value of the current detection circuit reaches the command value of the input current flowing through the input terminal, First above
Mode to the third mode, and in the third mode, the first switch, the second switch,
And the third switch is opened, and the fourth switch or the fifth switch is opened depending on the result of comparison between the command value of the input current and the command value of the alternating current, and the polarity of the alternating current. One of the switches is turned on, and when the detected value of the current detection circuit reaches the command value of the alternating current, the third mode is shifted to the second mode, and the second mode is changed. The photovoltaic power generation device according to claim 9 or 10, wherein the fourth switch or the fifth switch that is made conductive is opened. 13. The photovoltaic device according to claim 12, wherein the fourth switch and the fifth switch each include a parallel circuit of a diode and a semiconductor switch. 14. The control circuit according to the result of comparison between the command value of the input current and the command value of the alternating current in the third mode, and the polarity of the alternating current.
The photovoltaic device according to claim 13, wherein either one of the fourth switch and the fifth switch is made conductive. 15. The control circuit according to the result of comparison between the command value of the input current and the command value of the alternating current in the third mode, and the polarity of the alternating current.
The photovoltaic device according to claim 13, wherein either one of the fourth switch and the fifth switch is made conductive, or both semiconductor switches are opened. 16. The photovoltaic device according to claim 12, wherein each of the first switch and the second switch includes a series circuit of a diode and a semiconductor switch.