JP2003288202A - Display control semiconductor integrated circuit with single-port ram built therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems of a conventional display control semiconductor integrated circuit with a single-port RAM built in that the load of a CPU control system is increased, and the cycle time of transferring display data via the RAM is prolonged. <P>SOLUTION: This display control semiconductor integrated circuit 101 causes an internal synchronous control circuit 5 provided therein to control via a built-in single-port RAM 4 the transfer of display data between a CPU 2 and a display panel 3. This control of the display data transfer is effected in such a way that when a write access is made to the RAM 4 from the CPU 2 or a read access (write/read) is made to the CPU 2 from the RAM 4 to make a read access (display read) to the display panel 3 from the RAM 4 for the display data, write/read instructions are always given precedence over display read instructions without the need to output a ready signal to the CPU 2, regardless of whether or not the write/read instructions conflict with the display read instructions. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a single port R
The present invention relates to a display control semiconductor integrated circuit incorporating an AM.

[0002]

2. Description of the Related Art A conventional display control semiconductor integrated circuit incorporating a single port RAM will be described. As shown in FIG. 10, the display control semiconductor integrated circuit 1 includes a display device C
Built-in single-port RAM used for controlling display data transfer between the PU (Central Processing Unit) 2 and the display panel 3.
The display data transfer control is performed via 4. Using this display control semiconductor integrated circuit 1, a display data write access from the CPU 2 side to the RAM 4 / a read access from the RAM 4 to the CPU 2 side (hereinafter referred to as write / read) is performed by a command from the CPU 2, and the display control semiconductor When performing read access (hereinafter referred to as display read) of display data from the RAM 4 to the display panel 3 side by the internal clock synchronization (internal command) of the integrated circuit 1, write / read and display read are asynchronous with each other. In addition, RAM4,
Since there is only one word line, write / read and display read cannot be performed simultaneously. Therefore, when the write / read command is issued, the display control semiconductor integrated circuit 1 C
By outputting a ready signal to PU2, CP
CP is synchronized with U2 and the display control semiconductor integrated circuit 1.
Display data transfer control between U2 and the display panel 3 is performed (hereinafter, this control method is referred to as a ready control method).

The ready control method will be described below with reference to FIG.
This will be described with reference to the time chart of. When the Write / Read Command and the Display Read Command Do Not Conflict As shown in FIG. 11A, the write / read supplied from the CPU 2 to the display control semiconductor integrated circuit 1 is, for example,
When the write signal, which is a write command, changes to the "high" level at time t1, the display control semiconductor integrated circuit 1 causes the CPU 2 to
The ready signal supplied to the
It takes 0 ns and becomes "low" level at time t2
In 2, the conflict check with the display read is performed from time t2 to time t3, for example, requiring 170 ns. When it is confirmed that there is no conflict, the ready signal becomes "high" level, the write signal becomes "low" level at time t3, and the display data is written in the RAM 4. Therefore, even if the display read command does not occur during the writing, the time t3−t2 = 170 ns is required for the conflict check. When the setup / hold time of the write signal with respect to the display data is 60 ns as the period included in the time t3 to t2, the valid data is 60 ns with respect to the falling edge of the write signal.
Period is required and includes that period.

In the case of contention (when a display read command is generated during a write / read command), as shown in FIG. 11B, the write signal is transmitted at the same time as when the display read command is not generated during the writing. When the signal goes to the "high" level at t1, the ready signal goes to the "low" level at time t2, and the CPU 2 checks the display read conflict. When it is confirmed that there is a conflict, the display read is prioritized, and the write signal is at the “high” level until the conflict check + display read is completed at time t3 ′, which requires a time of, for example, 290 ns from time t2. Until now,
The ready signal remains at "low" level. Then, at the time t3 ', the ready signal becomes "high" level, the write signal becomes "low" level, and the display data becomes RAM4.
Written in. Therefore, when a display read command occurs during writing, time t3'-t2 = 290 ns (> t3-t2 = 170 ns) is required for conflict check + display read.

As described above, when a display read command is issued during write / read, it is common to suspend the write / read until the display read is completed, and the ready signal is sent before the write / read. Check is required,
There is a problem that the cycle time between write / read and display read becomes long. Further, since it is necessary to synchronize with the CPU side, the load of the control system on the CPU side becomes heavy.

[0006]

As described above, in the conventional display control semiconductor integrated circuit having the built-in single port RAM, the load on the control system on the CPU side becomes heavy, and the cycle of write / read and display read is increased. There is a problem that the time becomes long. In view of the above-mentioned problems, the present invention does not output a ready signal to the CPU,
An object of the present invention is to provide a display control semiconductor integrated circuit incorporating a single port RAM in which a write / read command from a PU is always prioritized over a display read command.

[0007]

A display control semiconductor integrated circuit of the present invention is a display control semiconductor integrated circuit having a built-in single-port RAM used for display data transfer control between a CPU and a display panel. Have,
Display data write access from the CPU side to the RAM or read access from the RAM side to the CPU side is performed by an instruction from the CPU, and the RAM is sent from the RAM to the display panel side asynchronously with the instruction from the CPU by an internal instruction synchronized with the internal clock. When performing read access to the display data of
The internal synchronization control circuit always gives priority to the instruction from the CPU side without outputting a ready signal to the CPU regardless of the competition or non-competition between the instructions. In the display control semiconductor integrated circuit, the internal synchronization control circuit controls the instruction from the CPU to give priority to the internal instruction, and a display panel from the RAM based on a signal from the controller. A display read signal generating circuit section for generating a display read signal for making a read access to display data to the side, and the CPU during the internal instruction based on a signal from the display read signal generating circuit section.
If there is an instruction conflict from the CPU side, it is judged whether or not the read access of the display data by the internal instruction is finished at that time, and if it is not finished, the internal data is read after the instruction from the CPU side is finished. And a determination flag signal generating circuit unit for generating a determination flag signal to the control unit so as to perform reread access to display data by an instruction.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A single port R according to the present invention will be described below.
An embodiment of a display control semiconductor integrated circuit incorporating an AM will be described. As shown in FIG. 1, the display control semiconductor integrated circuit 10
Reference numeral 1 is used for controlling display data transfer between the CPU 2 and the display panel 3 of the display device, and the internal synchronization control circuit 5 provided inside synchronizes write / read and display read, and also has a built-in single port RAM 4 The display data transfer control is performed via. This display control semiconductor integrated circuit 1
The display data transfer control by 01 does not require the ready signal that has been conventionally output to the CPU 2, and always uses the CPU regardless of the competition / non-competition between the write / read command and the display read command.
The write / read command from the 2 side has priority over the display read command.

First, write / read of the display data transfer control by the display control semiconductor integrated circuit 101 will be described. As shown in (a) to (c) of FIG.
Regardless of the competition or non-competition between the read command and the display read command, for example, when the write signal, which is a write command of the write / read supplied from the CPU 2 to the display control semiconductor integrated circuit 101, becomes the “high” level at time t1. , The write command is always prioritized, and the write signal starts from time t1, for example,
It takes 80 ns to reach the "low" level at time t2, and the display data is written in the RAM4. Therefore, in the case of this control method, since there is no need to perform a conflict check by a ready signal during the period from time t1 to t2 unlike the conventional ready control method, the time Tw required from the write command to writing in the RAM 4 is Only Tw = t2-t1 = 80 ns needs to be secured, which is a short time. As the period included in the time Tw, for example, when the setup / hold time of the write signal for the display data is 60 ns, the valid data requires a period of 60 ns for the falling edge of the write signal. Including the period.

Next, the display read of the display data transfer control by the display control semiconductor integrated circuit 101 will be described separately for the competition / non-competition between the write / read command and the display read command. In the case of non-conflict, as shown in FIG. 2A, there is no contention of the display read command during the period of time t1 to t2 when the write signal is at the "high" level, and there is no contention of the write command. Since there is a "high" level period of the display read signal in the period of time t3 when the signal rises to the "high" level, the display data is directly read from the RAM 4 during this period.

In the case of conflict (when a display read command occurs during a write / read command), as shown in FIG. 2B, the display read signal is in the period from time t1 to time t2 when the write signal is at "high" level. Is “high”
If you get up to the level and have a display read command conflict,
The "high" level period of the display read signal is delayed during the period of time t3 when the next write signal rises to the "high" level from the time t2 when there is no conflict between the write commands, and the display data is read from the RAM 4 for display during this period. To be done.

In case of conflict (when write / read command occurs during display read command), the display read signal is "high" as shown in FIG. 2 (c).
When the write signal rises to the “high” level and there is a write command conflict at the time t1 during the display read, the display read is stopped at that point, and the display read ends at that point. It is determined whether or not it is incomplete, and if it is not incomplete, a determination flag is set and the display read signal rises to the "high" level again at time t2 when the conflict of the write command is eliminated, and the display data is stored in the RAM.
Display lead from 4.

Next, an embodiment of the internal synchronization control circuit 5 will be described with reference to FIG. This circuit has a reset signal input terminal RES, a write / read signal input terminal WE bar /
RE bar, display read signal input end DRE bar, determination flag signal input end FLAG, enable signal output end EN and display read signal output end LAC bar, LAC1
Control unit 10 having a bar and a LAC2 bar, a reset signal input end RES and a display lead signal input end LAC1
Bar, LAC2 bar, display read signal generating circuit section 30 having display read signal output terminal LBE and trigger signal output terminal TRIG, reset signal input terminal RES, display read signal input terminal LBE and trigger signal input terminal TRI.
G and a decision flag signal generation circuit section 40 having a decision flag signal output terminal FLAG, and two OR circuits 50.
It has (1) and (2).

The input signal supplied to the internal synchronization control circuit 5 is supplied to the internal circuit as follows. Reset signal R
ES is supplied to one input of the OR circuit 50 (1).
The write / read signal WE bar / RE bar is supplied to the write / read signal input terminal WE bar / RE bar of the control unit 10 and the write / read signal output terminal WE bar / RE bar of the internal synchronization control circuit 5, respectively. Display read signal DR
E-bar is supplied to the display read signal input terminal DRE bar of the control unit 10 and also supplied to the other input of the OR circuit 50 (1). The output of the OR circuit 50 (1) is the control unit 1
It is supplied to the reset signal input terminal RES of each of the 0 and the determination flag signal generating circuit section 40 and also to one input of the OR circuit 50 (2). OR circuit 50
The output of (2) is supplied to the reset signal input terminal RES of the display read signal generation circuit section 30.

The output signal from the control unit 10 is supplied to other internal circuits as follows. Enable signal EN is OR
It is supplied to the other input of the circuit 50 (2). The display read signal LAC1 bar and LAC2 bar are the display read signal input terminals LAC1 bar and LA of the display read signal generation circuit section 30.
It is supplied to each C2 bar. Display read signal LAC
The bar is the display read signal output terminal LA of the internal synchronization control circuit 5.
Supplied to C bar.

The output signal from the display read signal generating circuit section 30 is supplied to other internal circuits as follows. The display read signal LBE is supplied to the display read signal output terminal LBE of the internal synchronization control circuit 5 and the display read signal input terminal LBE of the determination flag signal generation circuit section 40. The trigger signal TRIG is the determination flag signal generation circuit unit 4
0 is supplied to the trigger signal input terminal TRIG.

The determination flag signal FLAG, which is the output signal from the determination flag signal generation circuit section 40, is supplied to the determination flag signal input terminal FLAG of the control section 10.

The control unit 10, for example, as shown in FIG. 4, includes three AND circuits 11 (1) to 11 (3) and five O circuits.
R circuits 12 (1) to (5) and 10 NOT circuits 13
(1) to (10) and three D-furi flow 14 (1) to
(3), one first delay circuit 15 and one second delay circuit
Delay circuit 16 and two third delay circuits 17
It has (1) and (2) and one switch circuit 18. Then, in the above-mentioned configuration, the AND circuit 11
(1), using the NOT circuit 13 (1) and the second delay circuit 16, one input of the AND circuit 11 (1) is N
The first shot circuit 19 is connected to the other input via the OT circuit 13 (1) and the second delay circuit 16 and outputs a positive one-shot pulse at the rising edge of the input. Further, the OR circuits 12 (1), (2), N
OT circuits 13 (2) and (3) and third delay circuit 1
7 (1) and (2), the OR circuit 12 (1),
One input of (2) is connected to the other input via the NOT circuits 13 (2) and (3) and the third delay circuits 17 (1) and (2), and a negative edge is applied at the falling edge of the input. A second shot circuit 20 (1) that outputs a one-shot pulse,
It constitutes (2).

At each input terminal of the control unit 10, a write / read signal input terminal WE bar / RE bar is an AND circuit 11 (2).
, The determination flag signal input terminal FLAG is connected to the data input D of the D flip-flop 14 (1), and the reset signal input terminal RES is connected to the reset input R of the D flip-flop 14 (1). The signal input terminal DRE bar is connected to the reset input R of the D flip-flop 14 (2), the input of the first delay circuit 15 and the input of the first shot circuit 19. The output of the AND circuit 11 (2) is supplied to the clock inputs of the D-flip flow 14 (1) and the D-flip flow 14 (2) and the D-flip flow 14 via the NOT circuit 13 (4).
The data input D of (3) and the enable signal output terminal EN and the OR circuit 12 via the NOT circuit 13 (5)
It is connected to one of the inputs (3), (4) and (5). The output Q of the D flip-flop 14 (1) is output to the NOT circuit 13
It is connected to the input of the second shot circuit 20 (2) via (6). The output Q of the D-flip flow 14 (2) is NO
Input IN of the switch circuit 18 via the T circuit 13 (7)
Connected to 2. The output of the first delay circuit 15 is
It is connected to the data input D of the D flip-flop 14 (2) and the clock input of the D flip-flop 14 (3) via the NOT circuit 13 (8), and further to the input IN1 of the switch circuit 18 via the NOT circuit 13 (9). There is. The output of the first shot circuit 19 is the reset input R of the D flip-flop 14 (3).
It is connected to the. The output Q of the D-flip flow 14 (3) is
It is connected to the input SEL of the switch circuit 18. The output of the switch circuit 18 is connected to the input of the second shot circuit 20 (1) via the NOT circuit 13 (10). The outputs of the second shot circuits 20 (1) and (2) are A
2 inputs of ND circuit 11 (3) and OR circuit 12
It is connected to the other input of (3) and (4). AND
The output of the circuit 11 (3) is connected to the other input of the OR circuit 12 (5). OR circuits 12 (3), (4),
The output of (5) is the display read signal output end LAC1 bar,
It is connected to LAC2 bar and LAC bar, respectively.

The output signal EN is generated as a signal for recognizing the presence / absence of a write / read command by the input of the write / read signal WE bar / RE bar transferred from the CPU 2, and at the same time, LAC bar, LAC1 bar, which will be described later, L
Functions as each output enable of AC2 bar. The output signal LAC1 bar is generated as a display read signal for outputting a display read command when write / read and display read are not in conflict. The output signal LAC2 bar is generated as a display read signal for outputting a redisplay read command when the write / read conflicts with the display read, and feeds back the determination flag signal FLAG. The output signal LAC bar is generated as a display read signal for recognizing write / read cancellation from the CPU 2 from the output signals LAC1 bar and LAC2 bar. Further, the input signal RES has a system reset function.

The display read signal generating circuit section 30 includes, for example, as shown in FIG. 5, two AND circuits 31 (1),
(2), four OR circuits 32 (1) to (4), six NOT circuits 33 (1) to (6), and two D flip-flops 34 (1) and (2), Two fourth delay circuits 35
(1), (2) and two fifth delay circuits 36
(1), (2) and two sixth delay circuits 37
It has (1) and (2). Then, in the above configuration, the OR circuits 32 (1) and (2) and the NOT circuit 33.
(3), (4) and the fifth delay circuit 36 (1),
Using (2), one input of the OR circuits 32 (1), (2) passes through the NOT circuits 33 (3), (4) and the fifth delay circuits 36 (1), (2) and the other input. The third shot circuits 38 (1) and (2) are connected to the input and output a negative one-shot pulse at the falling edge of the input. Further, AND circuits 31 (1), (2), NO
T circuits 33 (5) and (6) and sixth delay circuit 37
Using the (1) and (2), the AND circuit 31 (1),
One input of (2) is connected to the other input through the NOT circuits 33 (5) and (6) and the sixth delay circuits 37 (1) and (2), and a positive one is input at the rising edge of the input. A fourth shot circuit 39 (1) for outputting a shot pulse,
It constitutes (2).

At each input terminal of the display read signal generating circuit section 30, the reset signal input terminal RES has a D flip-flop 34.
The display read signal input terminals LAC1 bar and LAC2 bar are connected to the respective reset inputs R of (1) and (2), and the D read flow 3 is connected via the NOT circuits 33 (1) and (2).
4 (1) and (2), and is connected to the respective data inputs D of D (4) and (4) via the fourth delay circuits 35 (1), (2) and the third shot circuits 38 (1), (2). 34 (1) and 34 (2) are connected to clock inputs C, respectively. Output Q of D-fli-flow 34 (1), (2)
Is ORed through the fourth shot circuits 39 (1) and (2).
The OR circuit 32 is connected to the two inputs of the circuit 32 (3).
The output of (3) is connected to the display read signal output terminal LBE. The other inputs of the OR circuits 32 (1) and (2) are connected to the two inputs of the OR circuit 32 (4), and the output of the OR circuit 32 (4) is connected to the trigger signal output terminal TRIG.

The output signal LBE is generated by the input signals LAC1 bar and LAC2 bar from the control unit 10 as a display read signal for outputting a display read command having a timing and a pulse width required at the time of competition or non-competition. . The necessary timing is the fourth delay circuit 35.
In (1) and (2), the necessary pulse width is adjusted by the sixth delay circuits 37 (1) and (2). Further, the output signal TRIG is generated as a trigger signal for determining whether or not the display read signal LBE has a pulse width sufficient to read the display data from the RAM 4. The input signal RES has a system reset function.

The determination flag signal generation circuit section 40 includes, for example, as shown in FIG.
(3) has one D flip-flop 42 and one seventh delay circuit 43. At each input end of the determination flag signal generation circuit section 40, the reset signal input end RES is connected to the reset input R of the D flip-flop 42, and the display read signal input end LBE is connected to the D flip-flop 42 via the NOT circuit 41 (1). It is connected to the data input D and the trigger signal input end T
RIG is the clock input C of the D flip-flop 42 via the NOT circuits 41 (2) and (3) and the seventh delay circuit 43.
It is connected to the. The output Q of the D flip-flop 42 is connected to the determination flag signal output terminal FLAG.

The output signal FLAG has a "high" pulse width of the display read signal LBE which is necessary for reading data from the RAM 4 according to the display read signal LBE and the trigger signal TRIG from the display read signal generating circuit section 30. In order to determine whether or not the seventh delay circuit 43
And the pulse width of the display read signal LBE is shorter than the delay time of the seventh delay circuit 43, for example,
The signal level is set to the “high” level and the control unit 10 receives RA.
It is generated as a determination flag signal for transmitting the display data read error determination from M4. Input signal RES
Has a system reset function.

Next, the operation of the internal synchronization control circuit 5 will be described with reference to FIGS. At time T0 in each figure, the CPU 2 supplies the internal synchronization control circuit 5 with the "high" level of the display read signal DRE bar and the write / read signal WE bar / RE bar, and the reset signal RES of "high" level is supplied. When the level is supplied, the control unit 1
0, the display read signal generation circuit section 30, and the D flag included in each of the determination flag signal generation circuit section 40 are reset, and the write / read signal WE bar / RE bar and the display read from the internal synchronization control circuit 5 to the RAM 4 side. "High" level of signal LAC bar and display read signal L
This is a state where the "low" level of BE is supplied. That is, at time T0, neither a write / read command nor a display read command is generated, and neither write / read nor display read is performed.

The conflict between the write / read command and the display read command and the non-conflict will be described below. In the case of non-conflict, as shown in FIG. 7, when the write signal WE, which is a write command, for example, is at the "low" level during the period from time T1 to T2, there is no conflict between the display read commands at this time. The display read signal DRE bar remains at "high" level, and the reset signal RES to the control unit 10, the display read signal generation circuit unit 30 and the determination flag signal generation circuit unit 40 also remains at "High" level. Therefore, since the display read signals LAC bar and LAC1 bar remain at the “high” level and the display read signal LBE remains at the “low” level, the write command is given priority,
The write signal WE bar becomes "high" level at time T2, and the display data is written in the RAM4. At this time, the display read signal LAC2 bar remains at the "high" level, and the trigger signal TRIG and the determination flag signal F
LAG remains at "low" level and time T2
There is no contention between the write command and the display read, and the display read signal DR is reached during the period from time T3 to T4 during which the write / read signal WE bar / RE bar is at the “high” level.
When the E-bar becomes "low" level, the reset signal RES to the control unit 10, the display read signal generating circuit unit 30 and the determination flag signal generating circuit unit 40 also becomes "Low" level. As a result, the display read signals LAC bar and LAC1 bar become "low" level, and the display read signal LBE and the trigger signal TRIG become "high" level, and the time T4
The display data is read from the RAM 4 during the period up to. At this time, the display read signal LAC2 bar is "high" level, and the determination flag signal FLAG is "low".
It remains at the level.

In case of conflict (when a display read command occurs during a write / read command) As shown in FIG. 8, the period from time T1 to T2 when the write signal WE bar becomes "low" level due to the generation of the write command. If there is a display read command and the display read signal DRE bar goes to "low" level at time T3 'in the middle of the time, and a conflict occurs between the write command and the display read command, the control unit 10 and the determination flag signal generation circuit unit 40 Reset signal R to
ES goes to "low" level, but at this time, the enable signal EN is at "high" level, and the reset signal RES to the display read signal generating circuit section 30 remains at "high" level. Therefore, the display read signal LAC bar, LA
Since the C1 bar remains at the “high” level and the display read signal LBE and the trigger signal TRIG remain at the “low” level, the write command is prioritized and the write signal W
The E-bar becomes "high" level at time T2, and the display data is written in the RAM4. Then, after the time T2, the write signal WE bar becomes "high" level and the conflict between the write command and the display read disappears, and the reset signal RES to the display read signal generation circuit section 30 also the display read signal DRE bar. It goes to "low" level until time T4 when it goes to "high" level. As a result, the display read signal LA
C bar and LAC1 bar are at "low" level, the display read signal LBE and the trigger signal TRIG are at "high" level, and the display data is RA during the period up to time T4.
Display read from M4. At this time, the display read signal LAC2 bar remains at the "high" level and the determination flag signal FLAG remains at the "low" level.

In case of conflict (when write / read command occurs during display read command) As shown in FIG. 9, there is a display read command at time T3 "before time T1 when the write command is generated, and there is a display read. When the signal DRE bar becomes "low" level, the control unit 10,
The reset signal RES to the display read signal generating circuit section 30 and the determination flag signal generating circuit section 40 also becomes "low" level, the display read signals LAC bar and LAC1 bar become "low" level, and the display read signal LBE and the trigger signal TRIG. Becomes "high" level, and display data starts to be read from the RAM4. However, when the write signal WE bar becomes "low" level at time T1,
Since the enable signal EN becomes "high" level, the reset signal RES to the display read signal generating circuit section 30 becomes "high" level. As a result, the display read signals LAC bar and LAC1 bar become "high" level, and the display read signal LBE and the trigger signal TRIG become "low" level, so that the display read is stopped at that point and the write command is given priority. The write signal WE bar becomes "high" level at time T2, and the display data is written in the RAM4. Further, when the write signal WE bar becomes "low" level at time T1, the trigger signal TRI from the display read signal generating circuit section 30 to the determination flag signal generating circuit section 40.
Depending on G and the display read signal LBE, the pulse width of the display read signal LBE is determined by the delay circuit inside the determination flag signal generation circuit unit 40 to determine whether the display read is completed or not completed during the period from time T3 ″ to T1. Judgment is made by comparing with the delay time of 1., and if it is not completed, a judgment flag is set, that is, the judgment flag signal FLAG from the judgment flag signal generating circuit section 40 to the control section 10 becomes “high” level, and the display data The display read command is made to wait until the time T2 when the writing to the RAM 4 ends, and when the determination flag signal FLAG is at the "high" level, the write signal WE bar becomes the "high" level after the time T2. The conflict between the write command and the display read is eliminated, and the reset signal RES to the display read signal generation circuit section 30 is also displayed. At time T4 when it goes high
It goes to "low" level. As a result, the display read signals LAC bar and LAC1 bar become "low" level, the display read signal LBE and the trigger signal TRIG become "high" level, and the display data is displayed and read from the RAM 4 until the time T4. .

As described above, the CPU is controlled by the internal synchronous control circuit 5 provided inside through the single port RAM 4 built in the display control semiconductor integrated circuit 101.
When controlling the display data transfer between the display 2 and the display panel 3, C
Without outputting a ready signal to PU2, regardless of the conflict / non-conflict between the write / read command and the display read command,
The write / read command from the CPU 2 side can always be prioritized over the display read command, the load on the control system on the CPU 2 side can be reduced, and the cycle time between write / read and display read can be shortened. it can.

[0031]

According to the present invention, according to the display control semiconductor integrated circuit incorporating the single port RAM of the present invention, the CP
The write / read command from the CPU can always be prioritized over the display read command without outputting a ready signal to U, and the load on the control system on the CPU side can be reduced and write / read can be performed. The cycle time with the display lead can also be shortened.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a display device using a display control semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a time chart explaining a display data transfer control method by the display control semiconductor integrated circuit of FIG.

3 is a circuit diagram showing an example of an internal synchronization control circuit included in the display control semiconductor integrated circuit of FIG.

FIG. 4 is a circuit diagram showing an example of a control unit that constitutes the internal synchronization control circuit of FIG.

FIG. 5 is a circuit diagram showing an example of a display read signal generation circuit section which constitutes the internal synchronization control circuit of FIG.

FIG. 6 is a circuit diagram showing an example of a determination flag signal generation circuit section that constitutes the internal synchronization control circuit of FIG.

7 is a time chart explaining the operation of the internal synchronization control circuit of FIG. 3 when there is no contention between a write command and a display read command.

8 is a time chart explaining the operation of the internal synchronization control circuit of FIG. 3 when a write command and a display read command conflict (when a display read command occurs during a write command).

9 is a time chart explaining the operation of the internal synchronization control circuit of FIG. 3 when a write command and a display read command conflict (when a write command occurs during the display read command).

FIG. 10 is a schematic configuration diagram of a display device in which a conventional display control semiconductor integrated circuit is used.

11 is a time chart explaining a display data transfer control method by the display control semiconductor integrated circuit of FIG.

[Explanation of symbols]

2 CPU 3 display panel 4 single port RAM 5 Internal synchronization control circuit 10 Control unit 30 Display read signal generation circuit 40 Judgment flag signal generation circuit section 101 Display control semiconductor integrated circuit

Claims (2)

[Claims] 1. A display control semiconductor integrated circuit having a built-in single-port RAM used for controlling display data transfer between a CPU and a display panel, having an internal synchronous control circuit, and having a CP from an instruction from the CPU.
From the U side, write access of the display data to the RAM or the read access from the RAM to the CPU side is performed.
When the read access of the display data from the RAM to the display panel side is performed by the internal instruction by the internal clock synchronization asynchronously with the instruction from the PU, the ready signal is output to the CPU regardless of the conflict or non-conflict between the respective instructions. Without doing
A display control semiconductor integrated circuit characterized in that the internal synchronization control circuit always gives priority to a command from the CPU side. 2. A control section for controlling the internal synchronization control circuit to give priority to an instruction from the CPU side over the internal instruction, and display data from the RAM to a display panel side based on a signal from the control section. When there is a conflict between the instructions from the CPU side in the internal instructions based on the signal from the display read signal generating circuit section for generating the display read signal for read access of At this point, it is determined whether or not the display data read access by the internal instruction is completed, and if it is not completed, the display data re-read access by the internal instruction is executed after the instruction from the CPU side is completed. 2. A display control semiconductor device as set forth in claim 1, further comprising: a determination flag signal generation circuit unit that generates a determination flag signal to the control unit. Circuit.