JP2003288055A - Display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the spurious profile of a moving picture inconspicuous without incurring the increase of a driving frequency while using a time-divided gradation displaying method. <P>SOLUTION: In a display device, a reset TFT element 13 is connected to the gate terminal of a TFT 12 for driving an organic EL element EL4 and the electricity conducting timing of the TFT element 13 is controlled by the electric potential of the capacitor C5 connected to the gate of the TFT element 13. At this time, a time-divided analog gradation displaying in which when one gradation displaying level is increased, a display period equivalent to one gradation is lengthened is realized by controlling reset timing for each pixel while gradually changing the electric potential for a frame period and, as a result, the spurious profile of the moving picture is suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to realize a gradation driving method for a display device such as a liquid crystal display or a thin film EL (Electro Luminescence) display which combines a switching element and an electro-optical element, and a gradation driving method therefor. The present invention relates to a display device having the pixel circuit configuration of.

[0002]

2. Description of the Related Art In recent years, research and development of flat panel organic displays have been actively conducted. In particular, organic EL (Electro Lu
minescence) display is expected to become popular as a self-luminous display capable of reducing power consumption.

This organic EL display has been commercialized as a simple matrix type, but it is considered that the active matrix type will become the mainstream in the future. this is,
The applied voltage-luminous efficiency characteristics of the organic EL are high luminous efficiency on the low luminance side and low voltage side, and low luminous efficiency on the high luminance side and high voltage side. Therefore, from the viewpoint of low power consumption and long life, it is always low. This is because the active matrix type, which emits light with brightness, is more advantageous than the simple matrix type, which emits light with high brightness in a time period corresponding to one scan line.

The active matrix type pixel can always emit light, but the simple matrix type pixel can emit light only for a period of time which is a fraction of the number of scanning lines. Therefore, in order to obtain the same brightness, the simple matrix type pixels need to emit light in a time that is several times as many scanning lines as the active matrix type pixels. Even if the light emission time of each pixel x the light emission brightness is constant, in the organic EL, the light emission efficiency for obtaining the light emission brightness is reduced on the high brightness side, and therefore the active matrix type light emission efficiency is better.

The active element for this active matrix type organic EL display can be driven even by an amorphous silicon TFT (thin film transistor), but the amount of current required to drive the organic EL is realized by a smaller TFT. Yes, single crystal silicon TFT (high TFT mobility), polysilicon TFT, CG (Contin
uous Grain) Silicon TFT is preferred. In particular, low-temperature polysilicon TFTs and CG silicon TFTs that can be formed on a glass substrate for direct view displays are preferred.

As shown in FIG. 19, a basic circuit of an active matrix type organic EL using the low temperature polysilicon TFT and the CG silicon TFT has two TFT elements T.
1, T2, a capacitor C1, and an organic EL element EL1. In this basic circuit, the gate line Gi
By the gate terminal control signal supplied via
When the element T1 becomes conductive, the data signal supplied through the source terminal line Si is transferred from the TFT element T1 to the TFT element T2.
Given to the gate terminal of. As a result, the TFT element T
When 2 becomes conductive, the power supply voltage supplied via the power supply wiring PS is applied to the organic EL element EL1 through the TFT element 2, and the organic EL element EL emits light. In addition, the voltage between the source terminal and the gate terminal of the TFT element T2 is the capacitor C
Since it is held by 1, the organic EL element EL1 can maintain the light emitting state.

In this basic circuit, the TFT
The element T2 (driving TFT) is arranged in series with the organic EL element EL1. Therefore, in this basic circuit, TF
If the threshold characteristics and mobility of the T element T2 vary, even if the same voltage is set to the capacitor C1, the value of the current flowing through the organic EL element varies, so there is a problem that the brightness of the pixel varies.

Therefore, the voltage applied to the capacitor C1 is
The TFT element T2 is set to a binary voltage of a voltage in which it is in a sufficiently low resistance state (conduction state) and a voltage in which it is in a non-conduction state.
Even if the threshold characteristics and the mobility of the FT element T2 vary, it is conceivable that the current value flowing through the organic EL element in the conductive state does not depend on the characteristic variation of the TFT to obtain display brightness. Then, it is conceivable to perform multi-gradation display by performing scanning a plurality of times within one frame period and independently setting the binary voltage values set in each scanning. This driving method is called a time division gradation driving method or a time division gradation driving method.

As such a time division gradation driving method,
In SID'00 Digest pp.924-927, "4.0-in. TFT-O
LED Displays and a Novel Digital Driving Method ”
The driving method announced by the Semiconductor Energy Laboratory is proposed. The circuit configuration described in this document is shown in FIG. 20, and its driving method is shown in FIG.

This circuit, as shown in FIG.
The circuit is formed by adding a TFT element T3. TF
The T element T2 has a gate terminal connected to the selection line Ei, a source terminal connected to the gate terminal of the TFT element T2, and a drain terminal connected to the power supply line PS.

Also in the driving method by this circuit, as shown in FIG. 21, scanning is performed a plurality of times (four times in this example) within one frame period, and the binary display value set in each scanning is independently set. The possible time division gradation display is performed. At this time, the TFT element T3 initializes the potential of the capacitor C1 (changes the voltage between the gate terminal and the source terminal of the TFT element T2 so that the TFT element T2 becomes non-conductive). The erasing scans (a) to (c) are carried out independently of the above scanning. Further, in each of the scans (1) to (4) in FIG. 21, the light emission period is set according to the weight of the gradation data set for each of the scans (1) to (4).

As a result, even if the threshold characteristics and the mobility of the driving TFT vary, the value of the current flowing through the organic EL element EL1 is less likely to vary, and a time-division gradation display with a short non-light emitting period is obtained.

As a countermeasure against the variation in the threshold characteristics and the mobility of the driving TFT, Sanyo Electric Co., Ltd. proposed EL'00 pp.3.
47-352, "Active Matrix OLED Displays wit
The circuit configuration shown in FIG. 22 was announced as "Low-Temperature Poly-Si TFT".

In this circuit configuration, a plurality of TFT elements T5 and T6 are arranged in parallel as driving TFTs connected in series to the organic EL element EL2, and the data signal passed through the TFT element T4 is transferred to the TFT elements T5 and T6. And the voltage between the source terminal and the gate terminal of the TFT elements T5 and T6 is held by the capacitor C2. With this circuit configuration,
By holding the voltage by the capacitor C2, each TFT element T5, T
The influence of the variation of 6 is suppressed.

Assuming that the TFT element T has the circuit configuration shown in FIG.
Let α (α <1) be the probability that a luminance error equal to or higher than the reference will occur due to the variation of the characteristic 2 above the allowable error. On the other hand, in the circuit configuration of FIG. 22, the luminance error is within the reference unless the characteristics of the TFT elements T5 and T6 both vary more than the allowable error. That is, in the circuit configuration of FIG. 22, the probability of causing a luminance error above the reference is α ² (α <1, so α ² <
α).

Furthermore, as a countermeasure against the variation in the threshold characteristics and the mobility of the driving TFT, Sony has made Asia Displ
In ay / IDW'01 pp.1395-1398, “Pixel-Driving Me
The circuit configuration shown in FIG. 23 was proposed as "thodfor Large-Size Poly-Si AM-OLED Displays".

In this circuit configuration, the TFT element T1 as a driving TFT connected in series with the organic EL element EL3.
A TFT element T9 is provided in parallel with 0, and a data signal supplied from the TFT element T7 as a switching element is applied to the gate terminals of the TFT elements 9 and 10 via the TFT element T8. The gate terminal of the TFT element T8 has a selection line Ei.
It is connected to the. Further, the voltage between the source terminal and the gate terminal of the TFT elements T9 and T10 is held by the capacitor C3.

In the above circuit configuration, when the TFT element T7 is conductive, the TFT element T8 is also conductive, so that the potential of the capacitor C3 and the TFT element T8 flow the current set by the source terminal line Sj. Automatically set to voltage. Then, by the TFT elements T9 and T10 forming the current mirror circuit, a current value proportional to the current value set in the TFT element T9 is applied to the TFT element T1.
It is configured to flow to the 0 side.

[0019]

However, in a TFT element formed of low temperature polysilicon or CG silicon, whether adjacent TFT elements are formed in the same single crystal region or different single crystal regions, Alternatively, it cannot be controlled whether it is formed between two single crystal regions. Therefore, it is impossible to control whether the characteristics of the adjacent TFT elements are uniform or vary.

Therefore, in the circuit configuration shown in FIG.
This is effective when the characteristics of the FT elements T5 and T6 vary, but is not effective when the characteristics are uniform. On the contrary, in the circuit configuration shown in FIG.
There is a problem that it is effective when the characteristics of the T elements T9 and T10 are uniform, but not effective when they vary.

Due to the above problems, the time-division gray scale display method is effective in which the light emission luminance of the organic EL does not depend on the characteristic variation of the driving TFT even if the threshold characteristic / mobility of the driving TFT varies.

However, P using the time division gradation display method
For DP (Plasma Display Panel), Mikoshiba describes “Dynamic False Cons” in IDW'96 pp.251-254.
There is a problem that a moving image false contour is generated as announced as “tours on PDPs-Fatal or Curable?”. The principle of generating this moving image false contour will be described with reference to FIG.

When one frame period is divided into four subfields having a time width ratio of 1: 2: 4: 8 for displaying 16 gradations, the non-emission state is set to the 0th gradation and the entire emission state is set. If the 15th gradation is used, the pixels displaying the 7th gradation
The time period during which light is emitted does not overlap with the pixel displaying the gradation. For example, pixel 1 emits light in the subfield period with a time width ratio of 1: 2: 4 to display the 7th gradation, while pixel 5 emits light in the subfield period with a time width of 8 to display the 8th gradation. is doing. However, these two display periods do not overlap in time.

Therefore, as shown by arrows A1 to A6 in FIG. 24, when the display object at the 8th gradation moves at a speed of 2 pixels / frame in the background at the 7th gradation, the line of sight of the human is the moving direction ( Move in the direction of the arrow). At this time, arrow A
As indicated by 2 and arrow A5, the line of sight passes through both the light emitting period of the 7th gradation and the light emitting period of the 8th gradation, which is significantly larger than the display of the 8th gradation in the moving direction of the display object. Gradation display can be seen, or conversely, a gradation much smaller than that of the 7th gradation display can be seen through the non-light emitting period. Such a phenomenon is generally called a moving image false contour.

In the PDP currently on the market, in order to make the above-mentioned moving picture false contour inconspicuous, the sub-frame of the upper bit is divided into a plurality of sub-frames (for example, 1: 2: 4:
4: 4), and the afterglow time of the phosphor is increased.

On the other hand, it is possible to make the false contour of the moving image inconspicuous by taking the same correspondence in the time division gradation display method using the organic EL or liquid crystal, but if the subframe period is divided, Since the number of subframes increases, the scanning frequency increases. Further, the increase of the driving frequency causes a new problem of increasing the power consumption of the driving circuit.

Further, since the afterglow time of the organic EL is extremely short, a method for adjusting the afterglow time like a phosphor has not been established. For example, a method is conceivable in which primary excitation light emission is performed by an organic EL, secondary excitation light emission is performed using the primary excitation light emission, and the afterglow time characteristic of the substance for the secondary excitation light emission is adjusted. , These have not been realized.

Even if the liquid crystal is driven in the time-division gray scale, the response speed of the liquid crystal is originally slow, so that the same effect as if the afterglow time is lengthened occurs and the false contour of the moving image is not conspicuous. To be However, it is not preferable to charge and discharge a capacitive load such as a liquid crystal many times during one frame period because it increases power consumption.

Such a problem is caused by the problems shown in FIGS.
2 and FIG. 23, capacitors C1 to
The same problem occurs in the organic EL in which C3 is arranged, but including this problem, the above is regarded as a problem that the power consumption of the drive circuit increases.

The present invention has been made in view of the above circumstances. As a countermeasure against the variation in the threshold characteristics and the mobility of the driving TFT, the driving frequency is increased while using the time division gray scale display method. An object of the present invention is to provide a time-division grayscale driving method that makes a false contour of a moving image inconspicuous without fail, and a display device having the circuit configuration thereof.

[0031]

In order to solve the above-mentioned problems, a display device of the present invention conducts an electro-optical element for electrically controlling the light brightness and an input display signal for controlling the light brightness. A first switching element which is applied to the electro-optical element in a state, a first wiring which supplies a switching signal for conducting or non-conducting the first switching element to the first switching element, and the display signal A display device comprising: a second wiring supplied to the switching element, wherein a first potential holding means for holding a potential of the electro-optical element and a holding potential of the first potential holding means are reset. And a second switching element for connecting or disconnecting the first potential holding means to a reset power supply for holding the potential of a conduction state control terminal of the second switching element. A position holding means is characterized by comprising a holding potential control means for controlling the holding potential of the second potential holding means.

In the above structure, the electro-optical element is a self-luminous element such as an organic EL element (see FIGS. 2 and 5).
11 and EL5 in FIG. 14) and a liquid crystal element (LCD 1 in FIGS. 4 and 8) which is a capacitive optical element. If the electro-optical element is a self-luminous element, the first potential holding means is a capacitive element such as a capacitor (C4 in FIGS. 2, 4, 5, 8 and 11 and C6 in FIG. 14). Is. On the other hand, if the electro-optical element is a capacitive optical element, itself (LCD 1 in FIGS. 4 and 8) also serves as the first potential holding unit.
The first switching element is a TFT element (see FIG. 2,
(T11 in FIGS. 4, 5, 8 and 11 and T21 in FIG. 14)
It consists of Further, the second switching element is
For example, the second potential holding means formed of a TFT element (T13 in FIGS. 2, 4, 5, 8 and 11 or T23 in FIG. 14) and connected to the conduction state control terminal (gate terminal) is For example, it is composed of a capacitive element (C5 in FIGS. 2, 4, 5, 8, 11 and C7 in FIG. 14).

In the above structure, the second switching element is brought into the non-conducting state, whereby the first potential holding means is disconnected from the reset power supply, and the holding potential of the first potential holding means is set. . On the contrary, when the second switching element becomes conductive, the first potential holding means is connected to the reset power supply, and the holding potential of the first potential holding means is reset. Accordingly, the display state set or reset state of the electro-optical element is switched by the operation of the second switching means.

The potential of the conduction state control terminal of the second switching means is held by the second potential holding means, and the holding potential is controlled by the holding potential control means. Thus, the potential of the conduction state control terminal of the second switching means is controlled by controlling the holding potential, so that the potential control means controls conduction or non-conduction of the second switching means. Therefore, the timing for setting or resetting the operation of the electro-optical element can be controlled by the holding potential of the second potential holding means.

As a result, it is possible to realize time-division gradation display (time-division analog gradation display) in which the display period for one gradation becomes longer as the gradation display level increases.

In such a time-division analog gray scale display, since the display periods are all overlapped between the adjacent gray scales (the low gray scale display period is entirely overlapped with the high gray scale display period), the false contour of the moving image is generated. It is possible to realize gradation display with almost no occurrence.

Moreover, since there are only two states of display or non-display as the brightness control state in each period, when an organic EL element is used as the electro-optical element, a driving active element (for driving the electro-optical element). TFT such as Figure 2
It is possible to obtain gradation display that is less affected by the threshold characteristic of 12) and the variation in mobility.

In the above display device, the potential control means outputs a holding potential control voltage for controlling the holding potential to the third wiring (eg GRAYi in FIG. 2),
The second potential holding means is a capacitive element (C5 in FIG. 2, FIG. 4, FIG. 5, FIG. 8, FIG. 11 or C7 in FIG. 14), one terminal of which is conductive to the second switching element. It is preferably connected to the state control terminal and the other terminal is connected to the third wiring.

In the above structure, when the potential of one terminal of the capacitive element is changed by gradually changing the holding potential control voltage output to the third wiring, the other terminal of the capacitive element is changed. The electric potential also changes accordingly. As a result, the potential of the conduction state control terminal of the second switching element changes, so that the timing at which the second switching element becomes conductive / non-conductive can be controlled by the holding potential control voltage applied to the capacitive element. it can.

In the above configuration, even if the holding potential of the second potential holding means is fixed to a constant value, the conduction / non-conduction of the second switching element is caused by the variation in the threshold characteristic of the second switching element. The start timing of conduction varies.

In order to avoid this problem, it is effective to increase the amplitude of the holding potential control voltage output to the third wiring (GRAYi). However, considering the breakdown voltage of the TFT element used as the second switching element,
The required amplitude may not be secured in some cases.

In such a case, the display device described above has a third switching element (see FIG. 5 and FIG. 8) that connects or disconnects the conduction state control terminal and the reset power supply connection side terminal in the second switching element. T15, Figure 1
1 T19 and T20 in FIG. 14) and a fourth switching element (T16 in FIGS. 5 and 8) for connecting or disconnecting the second switching element and the reset power supply.
11 and T25) and the potential control means for controlling the potential of the conduction state control terminal of the fourth switching element.

In such a configuration, the second switching element and the third switching element are brought into conduction while the fourth switching element is in non-conduction, whereby the holding potential of the second potential holding means is held. Can be set to the voltage of the display signal applied from the second wiring to the second switching element ± the threshold voltage of the second switching element.

Further, the third switching element is made non-conductive, the fourth switching element is made conductive, and the second switching element is made conductive.
The display time of the electro-optical element can be controlled by changing the potential of the potential holding means and bringing the second switching element into the conductive state.

For example, the second switching element is an n-type T
In the case of FT, the initialization voltage of the second potential holding means is
The maximum potential that can be given to the second switching element + the maximum variation voltage among the threshold variations of the switching element (of the variations in the threshold voltage, the threshold potential difference between the gate terminal and the source terminal of the switching element is regarded as the maximum. Voltage), the source terminal and the gate terminal of the second switching element are short-circuited through the third switching element, and the voltage remaining in the second potential holding means is the voltage applied to the second switching element. + The threshold voltage of the second switching element can be used.

The second switching element is a p-type TF.
At T, the initialization voltage of the second potential holding means is set to the maximum potential voltage among the minimum potential that can be given to the second switching element-the threshold variation of the switching element, and then the third switching element is used. The drain terminal and the gate terminal of the switching element of 2 are short-circuited,
The voltage remaining in the second potential holding means can be defined as (voltage applied to the second switching element) − (threshold voltage of the second switching element).

In the above display device, the electro-optical element is connected to a self-luminous optical element such as an organic EL element and a driving power source for driving the self-luminous optical element, or If the drive switching element to be disconnected (T12 in FIGS. 2, 5, 11 and T22 in FIG. 14) is used, the first potential holding means is a capacitor, and the drive switching element It is preferable that the switching characteristics of and the switching characteristics of the second switching element have the same tendency.

That is, when the driving switching element and the second switching element are both TFT elements, if the driving switching element has a p-ch structure, the second switching element also has a p-ch structure. Alternatively, if the driving switching element has an n-ch configuration, the second switching element also has an n-ch configuration.

With this configuration, when the second switching element is in the conducting state, the gate terminal of the driving switching element can be connected to the reset power supply, and the driving switching element can be brought into the reset state. .

This is because the driving switching element is p-c.
With the h configuration, it is preferable that the gate terminal potential for making the driving switching element non-conductive is higher than the source terminal potential of the driving switching element. When the above-mentioned gate terminal potential is provided between the potential of such a reset power supply and the potential of the gate terminal of the driving switching element equal to or lower than that potential, the configuration of the second switching element for controlling the conduction state is It is preferably p-ch.

The driving switching element is an n-ch.
With this configuration, it is preferable that the gate terminal potential that makes the driving switching element non-conductive is lower than the drain terminal potential of the driving switching element. If the above-mentioned gate terminal voltage is provided between the potential of such a reset power supply and the potential of the gate terminal of the driving switching element equal to or higher than that potential, the configuration of the second switching element for controlling the conduction state thereof Is preferably n-ch.

According to the present invention, by adopting the following driving method regardless of the constitution of any of the above display devices,
The above problems are solved.

That is, according to the driving method of the display device of the present invention, the electro-optical element for electrically controlling the light brightness and the input display signal for controlling the light brightness in the conductive state are applied to the electro-optical element. A switching element; and a first wiring for supplying a switching signal for conducting or non-conducting the first switching element to the first switching element,
A method of driving a display device including a second wiring that supplies the display signal to the switching element, for resetting a holding potential of a first potential holding unit that holds a potential of the electro-optical element. Setting the potential of the second potential holding means for holding the potential of the conduction state control terminal of the second switching element, which connects or disconnects the first potential holding means to the reset power source, in the first period, The display state of the electro-optical element is set in the second period after the first period, and the holding potential of the second potential holding means is changed in the third period after the second period. Thus, the second switching element is changed from the non-conductive state to the conductive state, and the state of the electro-optical element is set or reset from the state set in the first period.

In the above driving method, the potential of the second potential holding means is set in the first period, the display state of the electro-optical element is set in the second period after that, and then the third state is set in the third period. Two
The holding potential of the potential holding means is changed. As a result, when the second switching element is changed from the non-conducting state to the conducting state, the state of the electro-optical element is set or reset from the state set in the first period. Even with such a driving method, the timing for setting or resetting the operation of the electro-optical element can be controlled by the holding potential of the second potential holding means, and the time division is performed in the state where the moving image false contour is hardly generated. It is possible to realize analog gradation display. Moreover, since each of the periods has only two states of display or non-display as the brightness control state, when an organic EL element is used as the electro-optical element,
A driving active element (see FIG. 2) for driving the electro-optical element.
It is possible to obtain a gradation display that is less affected by variations in threshold characteristics of the TFT 12) and mobility.

In the above driving method, in the third period,
A holding potential control voltage for controlling the holding potential of the second potential holding means is generated, and a first terminal and a second terminal connected to the conduction state control terminal of the second switching element are provided. The second element comprising a capacitive element having
It is preferable to apply the holding potential control voltage to the first terminal of the potential holding means.

In this driving method, the timing at which the second switching element is turned on / off is controlled by the holding potential control voltage applied to the capacitive element, as in the display device using the holding potential control voltage described above. be able to.

Further, in the above driving method, the second switching element is connected or disconnected to the conduction state control terminal and the reset power supply connection side terminal in the second switching element in the first period. A fourth switching element that sets the holding potential of the second potential holding means through a third switching element and connects or disconnects the second switching element and the reset power supply during the third period. Is made conductive,
It is preferable to set or reset the state of the electro-optical element when the second switching element becomes conductive.

In such a driving method, in the first period,
The holding potential of the second potential holding means is set through the second and third switching means. Accordingly, the holding potential of the second potential holding unit can be set to the voltage of the display signal applied to the second switching element from the second wiring ± the threshold voltage of the second switching element. Further, when the fourth switching element is in the conducting state during the third period, and thus the second switching element is in the conducting state,
The state of the electro-optical element is set or reset. At this time, the display time of the electro-optical element can be controlled by changing the potential of the second potential holding unit and bringing the second switching element into the conductive state.

In this driving method, when the second switching element is of the n type, the potential of the second potential holding means is
Initialization is performed by setting the maximum voltage that can be applied to the source terminal of the second switching element + the allowable maximum value of the threshold variation of the second switching element, and the third switching element is turned on in the first period. , The gate terminal and the drain terminal of the second switching element are short-circuited, and the potential of the second potential holding means is set to the voltage applied to the source terminal of the second switching element + the threshold voltage of the second switching element, Compensating for the threshold characteristic of the second switching element,
By setting the third switching element in a non-conducting state during the second and third periods, setting the fourth switching element in a conducting state during the third period, and changing the potential of the second potential holding means, The switching element may be changed from the non-conducting state to the conducting state, and the state of the electro-optical element may be set or reset.

When the second switching element is a p-type, the potential of the second potential holding means is the minimum voltage that can be applied to the second switching element-the allowable maximum value of the threshold variation of the second switching element. By doing so, the third switching element is brought into conduction in the first period, thereby short-circuiting the gate terminal and the drain terminal of the second switching element, and the potential of the second potential holding means, The voltage applied to the second switching element minus the threshold voltage of the second switching element, the threshold characteristic of the second switching element is compensated, and the third switching element is turned off in the second and third periods. , The fourth switching element is brought into the conducting state during the third period and the potential of the second potential holding means is changed, so that the second switching element is changed from the non-conducting state to the conducting state. Allowed, it may be set or reset state of the electro-optical element.

[0061]

BEST MODE FOR CARRYING OUT THE INVENTION The following will describe one embodiment of the present invention with reference to FIGS. 1 to 18.

The switching element used in the present invention is
Although it is composed of a low-temperature polysilicon TFT, a CG silicon TFT, or the like, the CG silicon TFT is used in each embodiment described below.

Regarding the structure of this CG silicon TFT, SID 'shown above from the Semiconductor Energy Laboratory.
00 Digest pp.924-927 “4.0-in. TFT-OLED Displays
Since it has been published in "anda Novel Digital Driving Method" etc., its detailed description is omitted here.

Regarding the CG silicon TFT process, the AM-LCD 200 was also provided by Semiconductor Energy Laboratory.
0 pp.25-28 “Continuous Grain Silicon Technology”
Since it has been announced in “AndIts Applications for Active Matrix Display”, its detailed description is omitted here.

Regarding the constitution of the organic EL element which constitutes the electro-optical element used in the present embodiment, the AM-LCD '01
pp.211-214 “Polymer Light-Emitting Diodes for
Since it was announced in "usein Flat panel Display" etc.,
Here, the detailed description is omitted.

The liquid crystal element, which is an electro-optical element used in the present embodiment, is also sharpened by AM-LCD'0.
1 pp.101-102 “Development of high performance AS
V-LCDs using Continuous Pinwheel Alignment (CPA) mo
Since it was announced in "de" etc., its detailed description is omitted here.

First, an active matrix type display device common to the respective embodiments will be described.

Regarding the gate lines and the source lines having the same functions as the constituent elements in the following active matrix type device, the same reference numerals as those of the gate lines and source lines in the conventional active matrix type display device, that is, Gi and Sj are used. Is given.

As shown in FIG. 1, this active matrix type display device has a display panel 1, a gate driver 2, a source driver 3, a reference voltage generator 4, an opposite voltage generator 5, and a controller 6. It has and.

The display panel 1 includes a plurality of gate lines G1, G2, ..., Gi and a plurality of source lines S intersecting each other.
, Sj, and pixel display circuits A11, A12, ..., Aij arranged in a matrix (hereinafter, reference symbols common to the pixel display circuits will be referred to as Aij). ing. One pixel display circuit Aij is provided at each intersection of the gate line Gi and the source line Sj, and as will be described later, an electro-optical element that electrically controls the light brightness and an input light brightness control. And a switching element which supplies a display signal for use to the electro-optical element in a conductive state.

In the display panel 1, the gate lines G1,
Control lines CONT1, which are paired with G2, ..., Gi, respectively.
CONT2, ..., CONTi are gate lines G1, G2
,, and Gi are provided so as to be parallel to each other. The control line (hereinafter, the symbol i is used when commonly referred to as the control line) CONTi is a line for applying a control voltage to each pixel display circuit Aij, as described later.

Further, on the display panel 1, the source line S
1, S2, ..., Sj paired with power line POW
, POW2, ..., POWj are source lines S1, S2
, Sj are provided so as to be parallel to each other. The power lines POW, POW2, ..., POWj are provided in this way because the dots of each color of RGB that form one pixel are formed in a stripe shape along the source line Sj. The power supply line (hereinafter, the reference character j is used when commonly referred to as the power supply line) POWj is a wire for applying a power supply voltage required to each pixel display circuit Aij, as described later.

The power supply line POWj is necessary for the display panel 1 in which the optical element provided in each pixel display circuit Aij is an organic EL element, but is not necessary when the optical element is a liquid crystal element.

When a liquid crystal element is used as the electro-optical element, the counter voltage generator 5 applies it to a counter electrode (not shown) provided on the display panel 1 based on a control signal given from the controller 6. This is a circuit that generates the counter voltage Vref. The counter electrode is provided commonly to each pixel display circuit Aij, and a DC potential is applied to the organic EL element. On the other hand, an AC potential may be applied to the counter electrode when a liquid crystal element is used. These counter electrodes are electrodes provided so as to face a pixel electrode (not shown) provided for each pixel display circuit Aij so as to keep a constant space.

The reference voltage generator 4 is based on the gradation data for display supplied from the controller 6 and the source driver 3
It is a circuit that generates a reference voltage that serves as a reference of the grayscale voltage Vs generated from a D / A conversion circuit (not shown) provided in the. Depending on the configuration of the display panel 1, a grayscale voltage generating unit may be provided instead of the reference voltage generating unit 4, and the source driver 3 may not be provided with the D / A conversion circuit.
Whichever configuration is adopted, the number of gradation voltages Vs corresponding to the number of gradations that can be displayed on the display panel 1 from the source driver 3 is obtained.
To occur.

The gate driver 2 is a circuit that outputs a selection signal (switching signal) for selecting each gate line Gi based on a timing signal such as a synchronization signal or a clock given from the control unit 6. This selection signal is
It is output in a pulse shape in one selection period described later (see Gi potential in FIG. 3). The gate driver 2 also controls the control line CON based on the control signal supplied from the control unit 6.
The control voltage given to Ti is generated. Details of the control voltage will be described later.

The source driver 3 is a circuit for generating or sampling the gradation voltage Vs to be output to each source line Sj based on a timing signal such as a synchronizing signal or a clock given from the control section 6. In addition, the display driver 3
Generates the power supply voltage applied to the power supply line POWj based on the voltage from the power supply circuit. Details of the power supply voltage will be described later.

[First Embodiment] As shown in FIG. 2, the matrix type display device according to the present embodiment includes a pixel display circuit AAij as the pixel display circuit Aij of FIG.

The pixel display circuit AAij is provided at each intersection of the source line Sj, which is the second wiring, and the gate line Gi, which is the first wiring, and is an organic E as an electro-optical element.
The L element 4, TFT elements T11 to T14, and capacitors C4 and C5 are provided. Source line Sj
Supplies a data signal as a display signal to the TFT element T11, while the gate line Gi supplies a switching signal to the TFT element T11 for making the same and non-conducting.

In the TFT element T11 which is the first switching element, the gate terminal is connected to the gate terminal line Gi,
The source terminal is connected to the source line Sj, and the drain terminal is connected to the gate terminal of the TFT element T12. In the TFT element T12 which is a switching element for driving, the source terminal is connected to the power supply wiring PS and the drain terminal is organic E
It is connected to the anode of the L element EL4. Organic EL element E
The cathode of L4 is connected to the counter electrode Ref. First
Of the TFT element T
Twelve gate terminals and source terminals are connected.

The second terminal is connected to the gate terminal of the TFT element T12.
The drain terminal of the TFT element T13, which is a switching element, is connected, and the reset power supply wiring PRES is connected to the source terminal of the TFT element T13. Also,
To the gate terminal (conduction state control terminal) of the TFT element T13, one terminal of the capacitor C5 which is the second potential holding means is connected, and the drain terminal of the TFT element T14 is connected. Further, the gradation control line GRAYi is connected to the other terminal of the capacitor C5, and TF
The scanning line LOADi is connected to the gate terminal of the T element T14. The source terminal line Sj is connected to the source terminal of the TFT element T14.

The gradation control line GRAYi and the scanning line LOADi are provided as the control line CONTi, and the power supply line PS and the reset power supply line PRE are provided.
S is provided as the power supply line POWj described above.

Grayscale control line GRAYi as the third wiring
Is a wiring for applying the gradation control voltage output from the gate driver 2 as the holding potential control means to the capacitor 5. This gradation control voltage is a voltage applied to the capacitor C5 in order to control the potential of the capacitor C5, as will be described later, and realizes analog gradation display.

The scanning line LOADi is provided to supply the scanning signal output from the gate driver 2 to the gate terminal of the TFT element T14. The scanning signal is output in a pulse shape at a timing different from that of the above selection signal in one selection period described later (see the LOADi potential in FIG. 3).

The power supply wiring PS is a wiring for applying a constant voltage for driving the organic EL element EL4 to each pixel display circuit AAij (Aij). The potential of the power supply line PS is different for each RGB dot in one pixel.

The reset power supply wiring PRES is a wiring for supplying a reset voltage for bringing the TFT element T12 into a non-conducting state to the TFT element T13 for resetting.

The above-mentioned TFT elements T11 to T14
Are all p-type TFTs. Further, since there is almost no physical difference between the drain terminal and the source terminal of the TFT element, it is possible to replace the source terminal and the drain terminal in this embodiment.

The switching elements (TFT elements T11 and T14) used in this embodiment are the above-mentioned CG silicon TFT elements, and the electro-optical element is the organic EL element E.
It is composed of L4 and a TFT element T12. Since the configurations of the organic EL element and the TFT element are described in the above-mentioned documents and the like, detailed description thereof will be omitted here.

Next, in the present embodiment, the operation of the pixel display circuit AAij will be described with reference to the timing chart shown in FIG. Note that here, the pixel display circuit A
The symbol “i” of Aij corresponds to i, which means the number of the gate terminal line Gi. The symbol "j" corresponds to j, which means the number of the source terminal line Sj. That is, it shows that the pixel display circuits AAij in FIG. 2 are arranged in a matrix.

The selection period of this display circuit AAij is as shown in FIG.
As shown as time, the period is 6Th from 7Th to 12Th. Before this selection period, as an initialization period,
GRAYi potential of FIG. 3 (potential of gradation control line GRAYi)
Is returned to V0 (= 4V). After the selection period, as the gradation control operation, the operation of gradually changing the GRAYi potential from V0 to V0-3V is performed.

Then, at time 8Th (first period) within the selection period, the LOADi potential (scan line LOA of FIG.
(Di potential) decreases to -4V, so that the scan line L
When OADi is selected, the Sj potential (source terminal line Sj
Potential) is stored in the capacitor C5 (C5 potential in FIG. 3). After that, at a time 11Th (second period) within the selection period, when the gate line Gi is selected by lowering the Gi potential (potential of the gate terminal line Gi) in FIG. 3 to −4 V, Si in FIG. 0 V (C4 potential in FIG. 3) is stored in the capacitor C4 as the potential (potential of the source terminal line Sj).

In the pixel display circuit AAij shown in FIG.
Power supply wiring PS, reset power supply wiring PRES, counter electrode R
The potentials of 6V, 7V, and 0V are set to ef, respectively.

Therefore, as described above, when the potential of 0V is set to the capacitor C4, the TFT element T12 becomes conductive and a voltage of about 6V is applied to the organic EL element EL4. Further, since the ON resistance of the TFT element T12 is preferably set to about 1/10 or less of the ON resistance of the organic EL element EL4, the voltage drop in the TFT element T12 is about 0.6 V or less, and the organic EL element EL4 The voltage applied to is about 5.4 V or more. As a result, organic E
The L element EL4 is in a light emitting state.

If a potential of about 7 V or more is set to the capacitor C4, the TFT element T12 becomes non-conductive and no current is supplied to the organic EL element EL4, so that the organic EL element EL4 becomes non-light emitting state. In addition, this TF
The potential for bringing the T element T12 into the non-conducting state is preferably as high as 8 V or more, but since the withstand voltage of the TFT element could not be sufficiently secured, it is set to 7 V in this embodiment.

In the present embodiment, this TFT element T13
The threshold voltage (depending on the process conditions because it depends on the threshold characteristic of the TFT element T13) is set to, for example, 2V.

In the case of such a threshold voltage, the capacitor C
When the potential of 5 (potential of the node N31) becomes a value obtained by subtracting the threshold voltage (2V) from the VRES potential (potential of the reset power supply wiring VRES) Voff (7V), that is, 5V, the TFT
The element T13 becomes conductive. Therefore, the potential set to the capacitor C5 by the Sj potential during this selection period is 5 to
The range is 8V.

Therefore, if a voltage of 7 V is applied to the capacitor C4 in the above selection period, the display state of the gradation 0 level is obtained. If a voltage of 0 V is applied to the capacitor C4 and a voltage in the range of 5 to 8 V is applied to the capacitor C5, gradation display of gradation 1 to maximum gradation level can be obtained.
For example, when a voltage of 0V is applied to the capacitor C4 and the gradation control line GRAYi is V0, a voltage of 6V is applied to the capacitor C5, the gradation control line GRAYi is V0-1V.
Then, the potential of the capacitor C5 drops to 5V, and the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

When a voltage of 0V is applied to the capacitor C4 and the gradation control line GRAYi is V0, the voltage is 7V to the capacitor C5.
If a voltage of V is applied, the gradation control line GRAYi is V0-
When the voltage becomes 2V, the potential of the capacitor C5 is 5V as well.
Therefore, the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

When a voltage of 0 V is applied to the capacitor C4 and the gradation control line GRAYi is V0, 8 is applied to the capacitor C5.
If a voltage of V is applied, the gradation control line GRAYi is V0-
Similarly, when it becomes 3V, the potential of the capacitor C5 is 5V.
Therefore, the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

Therefore, the voltage applied to the capacitor C5 is changed by changing the GRAYi potential in a period (third period) after time Th14, which is a period in which the GRAYi potential in FIG. 3 changes from V0 to V0-3. When the voltage is continuously changed within the range of 5 to 8 V, the light emitting state of the organic EL element EL4 is controlled regardless of the value of the Si potential, so that it is possible to realize analog gray scale even though it is time division gray scale.

In such a time-division gradation driving method, the higher the gradation level, the longer the organic EL element EL4 changes from the light emitting state to the non-light emitting state. As a result, between adjacent gradations (for example, between the 7th gradation level and the 8th gradation level), the display period having the lower gradation level is always included in the display period having the higher gradation level (7th floor). (8 gradation levels always emit light during the period when the gradation level emits light).
Therefore, as shown in FIG. 22, the light emission time between adjacent pixels is not overlaid, and a false contour of a moving image is less likely to appear in time-division gray scale display. Also, even if some false contours remain in the video,
It is not a level that can be perceived by humans.

Further, when the time-division gray scale display is performed, there are problems that the scanning frequency is multiplied by the number of bits and that necessary timing conversion needs to be performed using the frame memory. However, the time division as in the present invention has an effect that such a problem does not occur as in other analog gradation display.

In order to control the potential of the capacitor C5, several configurations other than the configuration shown in FIG. 2 can be considered.

For example, one terminal of the capacitor C5 has a gate terminal of the TFT element T13 and a switching element (not shown) whose conduction / non-conduction is controlled by the gradation control voltage from the gradation control line GRAYi. It is connected and the other terminal of the capacitor C5 is grounded. In such a configuration, the electric potential of one terminal of the capacitor C5 can be controlled by controlling the amount of charge discharged from the capacitor C5 by the switching element.

Although other circuit configurations are possible, whichever configuration is adopted, the potential of one terminal of the capacitor C5 is gradually changed, and the TF is changed by the changed potential.
The timing at which the T element T13 becomes conductive / non-conductive is controlled to set or reset the display state of the electro-optical element (organic EL element EL4).

However, it is considered difficult to control the amount of charge discharged from the capacitor C5 with the above circuit configuration. Therefore, it is preferable to use the circuit configuration shown in FIG.

In the embodiment of the present invention, the electro-optical element is composed of the TFT element T12 and the organic EL element EL4. However, as shown in FIG.
It may be composed of one.

When the pixel display circuit ABij as the pixel display circuit Aij of FIG. 1 is used, as shown in FIG. 4, the capacitor C4, the TFT element T12, the organic EL element EL4 and the power supply in the pixel display circuit AAij of FIG. The wiring PS is simply replaced with the liquid crystal element LCD1, and the other circuit configuration and driving method are the same as the driving method of the pixel display circuit AAij shown in FIG. 2, and therefore detailed description thereof is omitted here.

In such a pixel display circuit ABij, the pixel electrode connected to the TFT element T11 is the TFT
It is connected to the source line Sj via the drain terminal and the source terminal of the element T11, and the gate terminal of the TFT element T11 is connected to the gate line Gi. In addition, the counter electrode Re
The counter voltage Vref output from the counter voltage generator 5 is applied to f.

As a result, the difference (Von or Voff) between the voltage (signal voltage) of the display signal given from the source line Sj and the counter voltage Vref is applied to the liquid crystal element LCD1 while the TFT element T11 is conducting. Then, the transmittance or reflectance of the liquid crystal filled between the pixel electrode and the counter electrode Ref is modulated, and allows the pixel display circuit ABij to transmit or reflect light with the brightness according to the gradation data. Further, in each pixel display circuit ABij, the charge accumulated in the liquid crystal element LCD1 is held for a certain period, so that the display state is maintained accordingly even when the TFT element T11 is in the non-conducting state.

Even in such a structure, the liquid crystal element LC
By controlling the timing at which the voltage applied to D1 is switched from Von to Voff, time division analog gradation can be realized.

[Second Embodiment] In the first embodiment, the threshold voltage of the TFT element T13 is assumed to be 2V.
The threshold voltage actually changes depending on the process conditions, and moreover, the formation of a TFT element such as whether each TFT element is formed in a single crystal region or formed over different single crystal regions in the same panel. It also depends on factors such as the condition.

Therefore, in this embodiment, the TFT element T
A circuit configuration and a driving method when the threshold voltage of 13 varies in the range of, for example, 1 to 4 V will be illustrated.

In this case, in the circuit configuration of the first embodiment shown in FIG. 2, even if the potential 0V is applied to the same capacitor C4 and the voltage in the range of 6V is applied to the capacitor C5, the threshold voltage of the TFT element T13 is 1V. If so, the TFT element T13 becomes conductive immediately after the end of the selection period, and the organic EL element E
L4 is in a non-light emitting state (that is, about one gradation level).
If the threshold voltage of the TFT element T13 is 4V, T
The FT element T13 is in the non-conducting state until immediately before the next selection period, and the organic EL element EL4 has the maximum light emission period (that is, the maximum gradation level).

As described above, in the configuration of the first embodiment, the second
If the threshold voltage of the TFT element T13, which is the switching element, varies, there is a problem that the gradation level varies.

Therefore, in the present embodiment, in order to solve such a problem, the pixel display circuit ABij shown in FIG. 5 is used.
And the driving method shown in FIG. 6 is presented.

In the case of using the pixel display circuit ACij as the pixel display circuit Aij of FIG. 1, the TFT of FIG.
Instead of omitting the element T14, the TFT element T1 which is the third switching element is provided between the drain terminal and the gate terminal of the TFT element T13 which is the second switching element.
5 are provided. Specifically, the TFT element T13 is connected to the drain terminal and the gate terminal of the TFT element T13, respectively.
The TFT element T15 is arranged so that the drain terminal and the source terminal of 15 are connected.

A TFT element T16, which is a fourth switching element, is newly arranged to cut off and connect between the source terminal of the TFT element T13 and the reset power supply wiring PRES. The source terminal and the drain terminal of the TFT element T16 are connected to the source terminal of the TFT element T13 and the reset power supply wiring PRES, respectively.

The compensation control line COMPi is connected to the gate terminal of the TFT element T15, and the erase control line ERASE is connected to the gate terminal (conduction state control terminal) of the TFT element T16.
i is connected.

The compensation control line COMPi is connected to the scan driver 2
It is provided to supply the compensation control signal output from the gate terminal of the TFT element T19. The compensation control signal is output as a signal of a level for making the TFT element T19 conductive shortly before the selection period described later (FIG. 6).
(See COMPi Potential).

The erase control line ERASEi is provided to supply the erase control signal output from the scan driver 2 as the potential control means to the gate terminal of the TFT element T16. The erase signal is supplied to the TFT after the selection period described later.
It is output as a signal of a level for making the element T16 conductive (see the ERASEi potential in FIG. 6).

The other structure of the pixel display circuit ACij is the same as the structure of the pixel display circuit AAij of FIG. 2, and therefore the description thereof is omitted here.

Although all the TFT elements T15 to T16 are p-type TFTs, they may be replaced with n-type TFTs.

In this embodiment, the operation of the pixel display circuit ACij will be described below with reference to the timing chart shown in FIG.

Further, in the pixel display circuit ACij of FIG.
Power supply wiring PS, reset power supply wiring PRES, counter electrode R
The potentials of 6V, 7V, and 0V are set to ef, respectively.

The selection period of the pixel display circuit ACij is as shown in FIG.
As shown as time, it is a 7Th period of 8Th to 14Th. Before the selection period, the GRAYi potential of FIG. 6 is V0 + 4V at time 6Th as an initialization period.
Then, the COMPi potential (compensation control line CO
The potential of MPi) becomes the selected state (-4V). At this time, the ERASEi potential (erase control line ERAS of FIG.
The potential of Ei) is in the selected state (-4V). For this reason,
The TFT element T16 and the TFT element T15 become conductive, and the gate terminal of the TFT element T13 connected to the capacitor C5 becomes short-circuited with the reset power supply wiring PRES.
This gate terminal potential becomes the reset potential Voff (7V), and the holding potential of the capacitor C5 is set (first
Period).

Next, time 7Th before and after this selection period
During 15 Th, the ERASEi potential in FIG. 6 is in the non-selected state (12 V), and the TFT element T16 is in the open state. As a result, the TFT element T13 is separated from the reset power supply wiring PRES.

Next, the selection period comes, and the time is from 9Th to 13th.
In Th (second period), the Gi potential in FIG. 6 is -4V.
As a result, the gate terminal line Gi is selected. Further, during the time period 6Th to 11Th, the COMPi potential in FIG. 6 drops to -4V, and the compensation control line COMPi is brought into the selected state. Therefore, a voltage corresponding to the display gradation level is applied from the source line Sj to the gate terminal of the TFT element T13 through the TFT elements T11, T13, T15.

Further, at time 10Th, G of FIG.
The RAYi potential is lowered by the maximum value (-4V) of the variation range of the TFT threshold voltage to V0. At this time, a potential difference of -4 V or more occurs between the drain terminal and the gate terminal of the TFT element T13. And T
Since the FT element T13 is a p-type TFT, this potential difference causes the TFT element T13 to be in a conductive state, and electric charges move from the drain terminal of the TFT element T13 toward the gate terminal.

When the charge transfer is completed, the TFT element T
The voltage between the drain terminal and the gate terminal of 13 is determined by the threshold voltage of the TFT element T13. That is, the gate terminal voltage of the TFT element T13 becomes the drain terminal voltage of the TFT element T13-the threshold voltage of the TFT element T13.

As described above, in the pixel display circuit ACij and the driving method thereof according to the present embodiment, the TFT element T15 is provided and the operation of the TFT element T15 is controlled by the COMPi potential, so that the second switching element TF.
The threshold voltage of the T element T13 is compensated.

Next, at time 12Th, CO of FIG.
By setting the MPi potential to the non-selected state (12V), TF
The T element T15 becomes non-conductive, and the gate terminal and the source terminal of the TFT element T13 are disconnected.

Next, at time 13Th, the source line S
A binary gradation display voltage (0 V or 7 V) from j is set in the capacitor C4, and the Gi potential in FIG.
By setting V), the selection period ends.

After that, at the end of the time 15Th, by switching the ERASEi potential of FIG. 6 to the selected state (-4V), the TFT element T16 becomes conductive, and the source terminal of the TFT element T13 and the reset power supply wiring PRES are short-circuited. To do. Further, similarly to the driving example of the first embodiment shown in FIG. 3, the GRAYi potential of FIG. 6 is gradually lowered from V0 to V0-3V (third period).

Therefore, the Sj potential is set to the data voltage (data signal voltage) Vda during the above time 9Th to 11Th.
If set to ta, the potential V of the capacitor C5 immediately after that is set to
C5 is expressed as VC5 = Vdata-Vth. Here, Vth is a threshold voltage of the TFT element T13.

After that, if the potential of the capacitor C4 is set to 0 V at time 13Th, display of gradation 1 to maximum gradation level can be obtained. On the other hand, if the potential of the capacitor C4 is set to 7V at the time of 13Th, the display of the gradation 0 level is obtained.

For example, if the potential of the capacitor C4 is set to 0V and the Sj potential is set to 7V during the time 9Th to 11Th, the potential of the capacitor C5 becomes 7V-Vth. Therefore, when the GRAYi potential is V0, the TFT element T13 becomes conductive and the organic EL element EL4 changes from the light emitting state (set) to the non-light emitting state (reset).

If the potential of the capacitor C4 is set to 0V and the Sj potential is set to 8V during the time 9Th to 11Th, the voltage of the capacitor C5 becomes 8V-Vth. Therefore, when the GRAYi potential is V0-1V, the TFT element T13 becomes conductive and the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

If the potential of the capacitor C4 is set to 0V and the Sj potential is set to 9V during the time 9Th to 11Th, the voltage of the capacitor C5 becomes 9V-Vth. Therefore, when the GRAYi potential is V0-2V, the TFT element T13 becomes conductive and the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

If the potential of the capacitor C4 is set to 0V and the Sj potential is set to 10V during the time 9Th to 11Th, the voltage of the capacitor C5 becomes 10V-Vth. Therefore, when the GRAYi potential is V0-3V, the TFT element T13 becomes conductive and the organic EL element EL4 changes from the light emitting state to the non-light emitting state.

Therefore, by continuously changing the Sj potential in the range of 7 to 10 V during the time 9 Th to 11 Th, the organic EL element EL4 changes the timing from the light emitting state to the non-light emitting state at the TFT element T13. Since the control can be performed without depending on the threshold voltage of, the time division analog gradation can be realized without depending on the threshold voltage of the TFT element T13, unlike the case of the first embodiment.

Here, the result of simulation for confirming that the variation in the threshold voltage of the TFT element T13 can be compensated when the pixel display circuit ACij in FIG. 5 is driven by the driving method in FIG. 6 will be described with reference to FIG. To do.

In FIG. 7, when the threshold voltage of the TFT element T13 is -1V, -2V, -3V, the time is 9Th to 11th.
The potential of the capacitor C5 (node N31) and the potential of the capacitor C4 (node N11) are shown under the condition that the Sj potential is set to 9 V during Th.

In FIG. 7, the potential change of the node N11 starts from the range of about 7V to 5V at the node N31. At this time, the potential of the node N31 is higher than the expected potential 7V-Vth of the reset power supply wiring PRES by about 1V. This is the TFT element T13
It is considered that the leakage current of 1 starts to rise from a potential higher than the threshold voltage by 1 V, and the charge of the capacitor C4 starts to move.

As described above, even if the threshold voltage of the TFT element T13 varies and the potential of the capacitor C5 varies accordingly, the potential of the capacitor C4 becomes almost the same value. This makes it possible to realize time-division analog gradation display regardless of variations in threshold voltage.

In the embodiment of the present invention, the electro-optical element is composed of the TFT element, the capacitor, and the organic EL element. However, as shown in FIG.
It may be composed of CD1.

When the pixel display circuit ADij as the pixel display circuit Aij of FIG. 1 is used, as shown in FIG. 8, the capacitor C4, the TFT element T12, the organic EL element EL4 and the power source in the pixel display circuit ADij of FIG. The wiring PS is simply replaced with the liquid crystal element LCD1, and the other circuit configuration and driving method are the same as the driving method of the pixel display circuit ACij shown in FIG. 5, and therefore detailed description thereof is omitted here.

Even in such a structure, the liquid crystal element LC
By controlling the timing at which the voltage applied to D1 is switched from Von to Voff, time division analog gradation can be realized.

[Embodiment 3] In the present embodiment, assuming that the electro-optical element is composed of an organic EL element, an active element (TFT element) and a capacitor, an active element (TFT) that constitutes the electro-optical element is assumed. The difference from the pixel display circuit ACij in FIG. 5 described above will be described by describing the channel configuration of the element) and the channel configuration of the TFT element that is the second switching element.

In the pixel display circuit ACij of FIG. 5,
The active element is already p-type and the first switching element is also p-type. On the other hand, as shown in FIG. 9, in the pixel display circuit AEij, the active element is p
And the second switching element is n-type.

Considering the use of the pixel display circuit AEij as the pixel display circuit Aij of FIG. 1, in this configuration, the p-type TFT in the pixel display circuit ACij of FIG. 5 is used.
The elements T11, T13, T15, T16 are replaced with n-type TFT elements T17, T18, T19, T20.
In addition, the reset power supply wiring PRES is arranged not in the direction along the source line Sj but in the direction along the gate line Gi. Even with such a configuration, the reset power supply voltage is output from the display driver 3 to the reset power supply wiring PRES.

Since the pixel array is normally lined up with RGB in the horizontal direction (wiring direction of the gate line Gi), the potential of the reset power supply wiring PRES is different for each RGB. Therefore, as shown in FIG. 5, the reset power supply wiring PRES is arranged in the direction along the source line Sj. However, when the potentials of the reset power supply lines PRES are the same for RGB, the reset power supply lines PRES are adjacent to each other (here, one pixel is composed of RGB, and RGB constituting one pixel is counted as a total of 3 dots). Common wiring can be achieved with. This is
As shown in FIG. 3, the reset power supply wiring PRES is preferable because it can be shared by two adjacent dots.

This pixel display circuit AEij is used in the second embodiment.
In order to drive the pixel display circuit ACij of FIG.
, The Gi potential, GRAYi potential, ERASE
The polarities of the i potential and the COMPi potential may be inverted with respect to each potential of FIG.

Also in this embodiment, as in the second embodiment, when the TFT element T is driven by the driving method of FIG.
A simulation was performed to confirm that the variation in the threshold voltage of No. 13 can be compensated. However, in the pixel display circuit AEij, the voltage that can pass between the source terminal and the drain terminal of the TFT element T18, which is the second switching element, depends on the gate terminal voltage of the TFT element T18. Is maintained at 0V for a period according to the potential of the capacitor C5, and then gradually increases to 7V as the GRAYi potential rises.
It turned out to change toward.

That is, in the pixel display circuit AEij, in one frame period, the period in which the TFT element T12 is driven in the binary drive state (the voltage to the capacitor C4 where the TFT element T12 is in a sufficiently low resistance state and the non-conduction state). , Which is a period in which a binary voltage of the following voltage is applied and a voltage of 1 V or lower or 5 V or higher is applied to the gate terminal of the TFT element T12), the threshold characteristics and mobility of the TFT element T12 cannot be secured. It was found to be unfavorable due to the influence of the variation of.

On the other hand, as shown in FIG. 11, the TFT element T13 of the pixel display circuit AEij is replaced with a p-type TFT element T13.
In the pixel display circuit AFij replaced with, the polarities of the Gi potential, the ERASEi potential, and the COMPi potential are inverted with respect to the corresponding potentials in FIG. Then, the same result as the simulation result of FIG. 7 was obtained.

In addition, the pixel display circuit AGij shown in FIG.
In the pixel display circuit AFij of FIG.
Type TFT elements T12 and T13 are replaced with n type TFT elements T22 and T23, respectively.
25 are all n-type TFTs, and organic EL elements EL
Instead of 4, an organic EL element EL5 whose polarity is inverted is provided.

In this structure, the power supply wiring PS and the counter electrode R
ef and the reset power supply wiring PRES have potentials of 0 V and 6
It is set to V and 0V.

In driving the pixel display circuit AGij, the Gi potential, the ERASEi potential, the CO potential shown in FIG.
The polarities of the MPi potential and the GRAYi potential are inverted with respect to the corresponding potentials shown in FIG. 6, and a drive waveform in which each potential is adjusted is used.

FIG. 16 shows a simulation result confirming that the variation of the threshold voltage of the TFT element T22 which is the second switching element can be compensated when the pixel display circuit AGij is driven by the driving method according to the driving waveform of FIG. Show.

FIG. 16 shows the time 9Th to 1 in FIG. 15 when the threshold voltage of the TFT element T22 is set to 1V, 2V and 3V.
Under the condition that the Sj potential is set to -4 V for 1 Th, the potential of the capacitor C5 (node N31) and the capacitor C4 are
The potential of the (node N11) is shown. In this case, similar to the simulation result of FIG. 7 for the pixel display circuit Cij of FIG. 5, even if the threshold voltage of the TFT element T23 varies and the potential of the capacitor C5 varies accordingly, the potential of the capacitor C4 is almost the same. It becomes a value. This makes it possible to realize time-division analog gradation display regardless of variations in threshold voltage.

From these results, the channel polarities of the active elements (TFT elements T12 and T22) forming the electro-optical element and the second switching element are higher than those of the pixel display circuit AEij shown in FIG. It is understood that the channel polarities of the TFT elements T13 and T23 are preferably the same.

It should be noted that the output voltage of the driver circuit for supplying the analog gradation voltage to the source terminal wiring Sj has a variation in offset characteristic.

This variation in the offset voltage shifts the gradation characteristic for each source line Sj, so that it is recognized as a vertical line and the image quality is deteriorated.

Therefore, as shown in FIG. 17, in the dot in the vertical direction (wiring direction of the source line Sj), the gate line G
The source line Sj connected for each i is made different. For example,
The dot AFijg connected to the gate line Gi is connected to the source line Sjrg, and the dot AFi + 1jg connected to the gate line G1 + i is connected to the source line Sjgb.
As a result, the influence of the output offset voltage of the display driver 3 is dispersed in the respective colors of RGB in a dot shape, so that the vertical line is changed from the solid line shape to the broken line shape so as to be inconspicuous, and the image quality deterioration can be reduced.

Therefore, in this way, the pixel display circuit AFij
It is preferable that the source line Sj is connected to the source line Sj, and a signal required for display of each pixel display circuit AFij is allocated to the source line Sj for control and output according to the connection.

Since one pixel is formed in a shape close to a square, the size of each RGB dot is such that the horizontal side is 1 / vertical to the vertical side.
It will be about 3. In this pixel structure, when the organic EL film is formed by the ink jet method or the like, it is conceivable that high accuracy is required for forming in the lateral direction due to its short dimension.

Therefore, as shown in FIG. 18, the centers of the targets T of the organic EL film indicated by ellipses are shifted from each other between the adjacent dots, and the target T is made to have a shape close to a circle from an ellipse to the same shape. With inkjet deposition accuracy,
It is preferable to arrange a pixel electrode such as an ellipse shown in FIG. 22 that enables RGB pixels having a narrower pixel pitch to be separately colored.

In the embodiment of the present invention, the electro-optical element is composed of the TFT element, the capacitor, and the organic EL element. Instead of this, FIGS. 4 and 8 are used.
Similar to the configuration (1), it may be configured by a liquid crystal element (not shown).

Even in such a structure, time division analog gradation can be realized by controlling the timing at which the voltage applied to the liquid crystal element is switched from Von to Voff.

[0171]

As described above, in the display device of the present invention, the electro-optical element for electrically controlling the light brightness and the input display signal for controlling the light brightness are applied to the electro-optical element in a conductive state. A first switching element, and a first wiring for supplying a switching signal for conducting or non-conducting the first switching element to the first switching element,
Second wiring for supplying the display signal to the switching element, first potential holding means for holding the potential of the electro-optical element, and reset power supply for resetting the holding potential of the first potential holding means. A second switching element for connecting or disconnecting the first potential holding means to
The configuration is provided with second potential holding means for holding the potential of the conduction state control terminal of the second switching element and holding potential control means for controlling the holding potential of the second potential holding means.

As a result, the potential of the conduction state control terminal of the second switching means is controlled by controlling the holding potential, so that the second switching means controls conduction and non-conduction by the potential control means. To be done. Therefore, the timing for setting or resetting the operation of the electro-optical element can be controlled by the holding potential of the second potential holding means. As a result, it is possible to realize time-division gray scale display (time-division analog gray scale display) in which the display period for one gray scale becomes longer as the one gray scale display level increases. In such time division analog gradation display,
Since the display periods are all overlapped between the adjacent gradations, it is possible to realize the gradation display in which the false contour of the moving image is hardly generated.
Moreover, since there are only two states of display or non-display as the brightness control state in each period, when the organic EL element is used as the electro-optical element, the threshold characteristic of the driving active element for driving the electro-optical element or It is possible to obtain gradation display that is less affected by the variation in mobility.

Therefore, even if the threshold characteristic and the mobility of the driving active element are varied, the false contour of the moving image can be made inconspicuous without increasing the driving frequency while using the time division gradation display method. Play.
In addition, it is possible to solve the problems that have been problematic in the conventional time-division gray scale display, such that the scanning frequency is not multiplied by the number of bits and the frame memory is unnecessary.

In the above display device, the potential control means outputs a holding potential control voltage for controlling the holding potential to the third wiring, and the second potential holding means is a capacitive element, Since one terminal thereof is connected to the conduction state control terminal of the second switching element and the other terminal is connected to the third wiring, the potential of the common state control terminal of the second switching element is increased. Changes, so
The timing at which the second switching element is turned on / off can be controlled by the holding potential control voltage applied to the capacitive element. Therefore, it is possible to easily control the operating state of the electro-optical element with a simple circuit configuration.

In the display device, the third switching element that connects or disconnects the conduction state control terminal and the reset power supply connection side terminal of the second switching element, the second switching element, and the third switching element. A configuration is provided that includes a fourth switching element that connects or disconnects a reset power supply, and a potential control unit that controls the potential of the conduction state control terminal of the fourth switching element.

Thus, while the fourth switching element is in the non-conducting state, the second switching element and the third switching element are brought into the conducting state so that the holding potential of the second potential holding means becomes the second potential. The voltage of the display signal applied to the second switching element from the wiring can be set to ± the threshold voltage of the second switching element. Further, the third switching element is brought into a non-conducting state, the fourth switching element is brought into a conducting state, and the potential of the second potential holding means is changed,
The display time of the electro-optical element can be controlled by setting the switching element of 1 to the conductive state. Therefore, the voltage remaining in the second potential holding means in advance can be corrected by the threshold voltage of the second switching element. Therefore, the conduction timing of the second switching element can be controlled without depending on the variation in the threshold voltage of the second switching element. Therefore, it is possible to cancel the influence of the variation of the threshold voltage of the second switching element and obtain a uniform display regardless of the variation of the TFT threshold characteristic.

In the above display device, the electro-optical element is connected to a self-emission type optical element such as an organic EL element and a driving power source for driving the self-emission type optical element. Alternatively, in the case of a structure including a driving switching element to be disconnected, the first potential holding means is a capacitor, and the switching characteristics of the driving switching element and the switching characteristics of the second switching element have the same tendency. With this configuration, when the second switching element is in the conductive state, the gate terminal of the driving switching element can be connected to the reset power supply, and the driving switching element can be brought into the reset state. Since it is possible to secure a long period in which the driving switching element is driven in the binary driving state in one frame period, it is possible to obtain a uniform display regardless of variations in threshold characteristics of the driving switching element.

The driving method of the display device of the present invention is such that the electro-optical element for electrically controlling the light luminance and the input display signal for controlling the light luminance in the conductive state are applied to the electro-optical element.
Switching element, a first wiring for supplying a switching signal for conducting or non-conducting the first switching element to the first switching element, and a second wiring for supplying the display signal to the switching element. A method for driving a display device including wiring, wherein the first potential holding means is connected to a reset power supply for resetting the holding potential of the first potential holding means for holding the potential of the electro-optical element. Alternatively, the potential of the second potential holding unit that holds the potential of the conduction state control terminal of the second switching element to be disconnected is set in the first period, and the potential is set in the second period after the first period. By setting the display state of the electro-optical element and changing the holding potential of the second potential holding means in the third period after the second period, the second
Of the switching element is changed from the non-conducting state to the conducting state, and the state of the electro-optical element is set or reset from the state set in the first period.

As a result, the timing for setting or resetting the operation of the electro-optical element can be controlled by the holding potential of the second potential holding means, and the time division analog floor can be generated in the state where the false contour of the moving image is hardly generated. Key display can be realized. Moreover, since there are only two states of display or non-display as the brightness control state in each period, when the organic EL element is used as the electro-optical element, the threshold characteristic of the driving active element for driving the electro-optical element or It is possible to obtain gradation display that is less affected by the variation in mobility. Therefore, even if the threshold characteristics and the mobility of the driving active element vary, the effect that the moving image false contour can be made inconspicuous without increasing the driving frequency while using the time-division gray scale display method is produced.

In the above driving method, in the third period,
A holding potential control voltage for controlling the holding potential of the second potential holding means is generated, and a first terminal and a second terminal connected to the conduction state control terminal of the second switching element are provided. The second element comprising a capacitive element having
By applying the holding potential control voltage to the first terminal of the potential holding means, the second switching element is turned on / off similarly to the display device using the holding potential control voltage.
The timing of non-conduction can be controlled by the holding potential control voltage applied to the capacitive element. Therefore, it is possible to easily control the operating state of the electro-optical element with a simple circuit configuration.

In the above driving method, the second switching element and the conduction state control terminal and the reset power supply connection side terminal in the second switching element are connected or disconnected in the first period. A fourth switching element that sets the holding potential of the second potential holding means through a third switching element and connects or disconnects the second switching element and the reset power supply during the third period. Is made conductive, and the state of the electro-optical element is set or reset so that the holding potential of the second potential holding means during the first period becomes
Since the voltage is set through the second and third switching means, the holding potential of the second potential holding means is the voltage of the display signal applied to the second switching element from the second wiring ± the threshold value of the second switching element. Can be set to voltage. In addition, the state of the electro-optical element is set or reset by bringing the fourth switching element into the conductive state in the third period. At this time, the display time of the electro-optical element can be controlled by changing the potential of the second potential holding unit and bringing the second switching element into the conductive state.
Therefore, the voltage remaining in the second potential holding means in advance can be corrected by the amount of the threshold voltage of the second switching element.
The conduction timing of the second switching element can be controlled without depending on the variation in the threshold voltage of the switching element.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an active matrix type display device common to each embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a configuration of a pixel display circuit of the first embodiment provided in the active matrix type display device.

3 is a drive waveform diagram showing a time-division gray scale drive operation of the pixel display circuit of FIG.

FIG. 4 is an equivalent circuit diagram showing another configuration of the pixel display circuit of the first embodiment.

FIG. 5 is an equivalent circuit diagram showing a configuration of a pixel display circuit of a second embodiment provided in the active matrix display device.

6 is a drive waveform diagram showing a time-division gray scale drive operation of the pixel display circuit of FIG.

7 is an operation characteristic diagram showing a simulation result for confirming the effect of time division gray scale driving of the pixel display circuit of FIG.

FIG. 8 is an equivalent circuit diagram showing another configuration of the pixel display circuit of the second embodiment.

FIG. 9 is an equivalent circuit diagram showing a configuration of a pixel display circuit of a comparative example with respect to the pixel display circuit of the third embodiment provided in the active matrix display device.

10 is a drive waveform diagram showing a time division gray scale drive operation of the pixel display circuit of FIG.

FIG. 11 is an equivalent circuit diagram showing a configuration of a pixel display circuit according to a third embodiment provided in the active matrix display device.

12 is a drive waveform diagram showing a time-division gray scale drive operation of the pixel display circuit of FIG.

13 is a circuit diagram showing an application example of the pixel display circuit of FIG.

FIG. 14 is an equivalent circuit diagram showing another configuration of the pixel display circuit of the third embodiment.

15 is a drive waveform diagram showing a time-division gray scale drive operation of the pixel display circuit of FIG.

16 is an operational characteristic diagram showing a simulation result for confirming the effect of time-division gray scale driving of the pixel display circuit of FIG.

17 is a circuit diagram showing an application example of the pixel display circuit of FIG.

FIG. 18 is a circuit diagram showing another application example of the pixel display circuit of FIG.

FIG. 19 is an equivalent circuit diagram showing a configuration of a pixel display circuit provided in a conventional active matrix display device.

FIG. 20 is an equivalent circuit diagram showing a configuration of a pixel display circuit provided in a conventional active matrix display device that performs time division gray scale driving.

FIG. 21 is a diagram showing a time division gray scale driving method of the pixel display circuit of FIG. 20.

FIG. 22 is an equivalent circuit diagram showing a configuration of a pixel display circuit provided in a conventional active matrix type display device and provided with measures against variations in threshold characteristics and mobility of driving TFT elements.

FIG. 23 is an equivalent circuit diagram showing a configuration of a pixel display circuit provided in a conventional active matrix type display device and provided with measures against variations in threshold characteristics and mobility of driving TFT elements.

FIG. 24 is a diagram showing a principle of generating a false contour of a moving image in a conventional PDP.

[Explanation of symbols]

2 gate driver (holding potential control means, potential control means) C4, C6 capacitors (first potential holding means) C5, C7 capacitors (second potential holding means) EL4, EL5 organic EL element LCD1 liquid crystal element Gi gate line ( First wiring) Sj Source line (second wiring) GRAYi Gradation control line (third wiring) T11, T21 TFT element (first switching element) T12, T22 TFT element (driving switching element) T13, T23 TFT element (second switching element) T15, T19, T24 TFT element (third switching element) T16, T25, T20 TFT element (fourth switching element)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641E 641R 3/30 3/30 H H05B 33/14 H05B 33/14 A F term (reference) 2H093 NA16 NA51 NB01 NB07 NB11 NC34 NC35 ND06 ND49 ND53 3K007 AB17 DB03 GA04 5C006 AA14 AF44 BB16 BC06 BC12 BF34 BF37 EB05 FA29 5C080 AA06 AA10 BB05 DD30 EE29 FF11 JJ04JJ03 JJ02JJ03 JJ03

Claims (7)

[Claims] 1. An electro-optical element for electrically controlling light brightness, a first switching element for applying an input display signal for light brightness control to the electro-optical element in a conductive state, and the first switching element. A display device comprising: a first wiring for supplying a switching signal for conducting or non-conducting an element to the first switching element; and a second wiring for supplying the display signal to the switching element. A first potential holding means for holding the potential of the electro-optical element, and a first power source holding means for connecting or disconnecting the first potential holding means to a reset power supply for resetting the holding potential of the first potential holding means. Second switching element, a second potential holding means for holding the potential of the conduction state control terminal of the second switching element, and a holding potential for controlling the holding potential of the second potential holding means. A display device comprising: a holding potential control means. 2. The potential control means outputs a holding potential control voltage for controlling the holding potential to a third wiring, the second potential holding means is a capacitive element, and one terminal of which is a capacitive element. The display device according to claim 1, wherein the second switching element is connected to a conduction state control terminal and the other terminal is connected to the third wiring. 3. A third switching element for connecting or disconnecting the conduction state control terminal and the reset power supply connection side terminal in the second switching element; and connecting the second switching element and the reset power supply, or The display device according to claim 1, further comprising: a fourth switching element to be disconnected, and a potential control unit that controls a potential of a conduction state control terminal of the fourth switching element. 4. The electro-optical element comprises a self-emission type optical element and a drive switching element for connecting or disconnecting the self-emission type optical element to a drive power source for driving the self-emission type optical element. The first potential holding means is a capacitor, and the switching characteristics of the driving switching element and the switching characteristics of the second switching element are:
The display device according to claim 1, wherein the display device has the same tendency. 5. An electro-optical element for electrically controlling light brightness, a first switching element for applying an input display signal for light brightness control to the electro-optical element in a conductive state, and the first switching element.
And a second wiring for supplying the display signal to the switching element, and a second wiring for supplying the switching signal for making the switching element conductive or non-conductive to the first switching element. A second switching method for driving, comprising connecting or disconnecting the first potential holding means to a reset power supply for resetting the holding potential of the first potential holding means for holding the potential of the electro-optical element. Second for holding the potential of the conduction state control terminal of the element
The potential of the potential holding means is set in a first period, the display state of the electro-optical element is set in a second period after the first period, and the display state of the electro-optical element is set in a third period after the second period. Changing the holding potential of the second potential holding means during the period to change the second switching element from the non-conducting state to the conducting state,
A driving method of a display device, wherein the state of the electro-optical element is set or reset from the state set in the first period. 6. A holding potential control voltage for controlling the holding potential of the second potential holding means is generated in the third period, and the first terminal is electrically connected to the second switching element. 6. The holding potential control voltage is applied to the first terminal of the second potential holding means formed of a capacitive element having a second terminal connected to the state control terminal. Driving method for display device. 7. A third switching element for connecting or disconnecting the second switching element and the conduction state control terminal and the reset power supply connection side terminal in the second switching element in the first period. The holding potential of the second potential holding means is set through, and the fourth switching element that connects or disconnects the second switching element and the reset power supply is brought into a conductive state during the third period, and 7. The method for driving a display device according to claim 5, wherein the state of the electro-optical element is set or reset.