JP2003282878A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device fabricated in an SOI substrate, and its fabricating method, in which the potential of a supporting substrate can be set at the ground level or an arbitrary bias level even after packaging. <P>SOLUTION: In the semiconductor device, a substrate contact hole is provided in a buried oxide film and an electrode having electrical contact with a supporting substrate is formed on surface side of an SOI substrate. When a face-up packaging method is employed, a multi-power supply circuit capable of using a plurality of power supply voltages properly can be constituted and the advantages of the SOI substrate are utilized. Since the potential of the supporting substrate can be set at the ground level or an arbitrary bias level even when a face-down packaging method is employed, potential of the supporting substrate is not brought into floating state. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SO in which a buried oxide film and a surface silicon layer are provided on a silicon support substrate.
The present invention relates to a semiconductor device in which a plurality of semiconductor elements are formed on a buried oxide film using an I (Silicon On Insulator) substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art An SOI substrate is a substrate in which a buried oxide film and a surface silicon layer are formed on a silicon support substrate.
A semiconductor device manufactured using this SOI substrate has many advantages as compared with a semiconductor device manufactured using bulk silicon. For example, it has high resistance to temperature and radiation, is easy to realize high-speed operation, and has low power consumption. Here, the structure of a semiconductor device using a conventional SOI substrate will be described with reference to FIG.

FIG. 2 is an enlarged sectional view showing an essential part of an IC chip which is a semiconductor device using a conventional SOI substrate. In the SOI substrate 53, the buried oxide film 3 is provided on the support substrate 7 made of silicon, and the surface silicon layer is provided thereon. However, in FIG. 2, the surface silicon layer is separated and formed in a plurality of island-shaped element regions, and impurities are injected and diffused into each of the element regions, so that the low concentration N-type region 15 and the low concentration P-type region are formed. It is 13. A P-channel field effect transistor (hereinafter referred to as “P-channel FET”) 33 is provided on the low-concentration N-type region 15, and an N-channel field-effect transistor (hereinafter referred to as “N-channel FET”) is provided on the low-concentration P-type region 13. 35 is the insulating film 3
9 and the field oxide film 57 are provided so as to be insulated from each other.

In the P-channel FET 33, a gate electrode 37 is formed in the center of the low-concentration N-type region 15 via a gate oxide film 17, and a P-type drain layer 23 and a P-type source layer 25 are formed on both sides of the gate electrode 37. The gate electrode 37, the P-type drain layer 23, and the P-type source layer 25 are provided with the metal electrodes 11 extending on the insulating film 39 through the contact holes 31, respectively.

In the N-channel FET 35, a gate electrode 37 is formed in the center of the low-concentration P-type region 13 via a gate oxide film 17, and an N-type drain layer 27 and an N-type source layer 29 are formed on both sides of the gate electrode 37. The gate electrode 37, the N-type drain layer 27, and the N-type source layer 29 are also provided with the metal electrodes 11 extending on the insulating film 39 through the contact holes 31, respectively.

In both the P-channel FET 33 and the N-channel FET 35, the metal electrode connected to the gate electrode 37 is
It is not shown in FIG. 2 because it is provided at a sectional position different from that in FIG. Although not shown in the drawing, a pad portion provided with an input / output terminal is formed on one of the many metal electrodes 11 that is connected to the outside.

P-channel FET 33 and N-channel FET
35, the conductivity types of the low-concentration region and the drain layer and the source layer are opposite, but the basic configuration is common.
The pair of P-channel FET 33 and N-channel FET 35 constitutes a CMOS transistor. A passivation film 41 is provided as a protective film on the entire surface of the IC chip except the pad portion.

Although only one set of CMOS transistors is shown in FIG. 2, a large number of CMs are included in an actual IC chip.
An OS transistor, another FET, a bipolar transistor, a resistor, a capacitor, etc. are provided. Of course, all of these are created by SOI technology.

When operating an IC chip which is a semiconductor device using an SOI substrate as described above, it should be noted that the support substrate must be grounded or biased. For example, in the case of the IC chip shown in FIG.
The silicon support substrate 7 should be grounded or biased. Thereby, the operation of the IC chip can be stabilized. This is important as a problem when mounting an IC chip on a lead frame of a package, a circuit board, or the like.

There are roughly two types of methods for mounting an IC chip, a face-up mounting method and a face-down mounting method. The face-up mounting method is to bond the IC chip with the element surface (face) facing upward, and to bond it onto a mounting board such as a lead frame of a package or a circuit board.
This is a method of connecting the terminals (which are electrically connected to the above-mentioned pad portion) provided on the element surface of the chip and the connection terminals on the mounting substrate side by wire bonding. The face-down mounting method is a method of forming bumps or the like on the element surface of an IC chip, which are projections that are electrically connected to the above-described pad portion, and directs the surface downward to lead electrodes (conduction pattern) on the mounting substrate. It refers to a mounting method of directly contacting with and electrically connecting and adhering.

According to the face-up mounting method, the back surface of the IC chip (the surface opposite to the element surface), that is, the back surface of the support substrate can be electrically contacted with the ground portion on the mounting substrate. Therefore, in the case of the IC chip shown in FIG. 2, by adding a process for obtaining a good electrical contact with the ground portion on the mounting substrate side on the back surface side of the supporting substrate 7 of the SOI substrate 53, the supporting substrate 7 Can be electrically connected to the grounding portion on the mounting board side to be grounded.

However, this mounting method has a problem that the potential of the supporting substrate of the IC chip is limited to the ground potential on the mounting substrate side. Therefore, in the IC chip using the SOI substrate, although it is possible to configure a multi-power supply circuit that selectively uses a plurality of power supply voltages, the bias voltage of the support substrate cannot be set arbitrarily, which is an advantage. There is a problem that you can not make use of.

Further, in the face-down mounting method, since the back surface of the supporting substrate and the lead electrode forming surface of the mounting substrate such as a lead frame do not contact each other, it is difficult to bias or ground the supporting substrate itself, and the silicon substrate Difficult to get an electrical connection with. Therefore, there is a problem that the potential of the supporting substrate is in a floating state.

Next, a conventional technique for manufacturing the semiconductor device formed on the SOI substrate shown in FIG. 2 will be described with reference to the drawings. 2 to 9 are cross-sectional views showing a method of manufacturing a semiconductor device in the related art in the order of steps.

As shown in FIG. 3, the SOI substrate 53 has a structure in which the buried oxide film 3 is provided on the support substrate 7 and the surface silicon layer 1 is provided on the buried oxide film 3. First, heat treatment is performed in an oxidizing atmosphere to form a pad oxide film 61 on the surface of the surface silicon layer 1. Then C
A silicon nitride film 63 is formed by the VD method.

Subsequently, a photoresist 43 is formed on the entire surface of the surface silicon layer 1 by a spin coating method. Next, an exposure process using a predetermined photomask,
A development process is performed, and the photoresist 43 is patterned so as to remain on the element region.

Subsequently, as shown in FIG. 4, the silicon nitride film 63 in the opening of the photoresist 43 is completely removed.
Subsequently, the pad oxide film 6 in the opening of the photoresist 43 is formed.
Completely remove 1. Further, the surface silicon layer 1 in the opening of the photoresist 43 is etched until the film thickness becomes half. Then, the photoresist 43 is removed.

Subsequently, as shown in FIG. 5, heat treatment is performed in an oxidizing atmosphere to form a field oxide film 57. As a result, the field oxide film 57 in the element isolation region and the buried oxide film 3 are in contact with each other, and each element region is formed in an island shape. Subsequently, the silicon nitride film (not shown) and the pad oxide film (not shown) are etched and completely removed.

Next, as shown in FIG. 6, the SOI substrate 5
A photoresist (not shown) is formed on the entire surface of No. 3 by spin coating. Next, an exposure process and a development process are performed using a predetermined photomask, and the P channel F
The photoresist is patterned so that the region where ET is formed is opened. Then, an N-type impurity (not shown) is ion-implanted using the photoresist as an ion-implantation blocking film. Then, the photoresist is removed using sulfuric acid.

Further, a photoresist (not shown) is formed on the entire surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the region where the N-channel FET is formed is opened.
Subsequently, P-type impurities (not shown) are ion-implanted using the photoresist as the ion-implantation blocking film. Then, the photoresist is removed using sulfuric acid. continue,
Heat treatment is performed to diffuse the impurities, and the low concentration P-type region 13
And a low concentration N type region 15 is formed.

Next, as shown in FIG. 7, oxidation treatment is performed to form a gate oxide film 17. Subsequently, a gate electrode material (not shown) is formed on the entire upper surface of the SOI substrate 53. Subsequently, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so as to remain on the region where the gate electrode 37 is formed. Subsequently, etching is performed until the gate electrode material in the photoresist opening is completely removed to form the gate electrode 37. Then, the photoresist is removed.

Next, as shown in FIG. 8, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region for forming a P-channel FET is opened. Then, using a photoresist as an ion implantation blocking film, P type impurities (not shown) are ion implanted to form the P type drain layer 23 and the P type source layer 25. Then, the photoresist is removed.

Subsequently, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the region where the N-channel FET is formed is opened. Next, using photoresist as an ion implantation blocking film,
N-type impurities (not shown) are ion-implanted to form an N-type drain layer 27 and an N-type source layer 29. Then, the photoresist is removed.

Next, as shown in FIG. 9, an insulating film 39 is formed on the entire surface. Then, heat treatment is applied in a nitrogen atmosphere. As a result, the P-type drain layer 23 and P
Type source layer 25, N type drain layer 27, and N type source layer 2
The impurities ion-implanted into 9 and 9 are activated. The heat treatment in the nitrogen atmosphere also serves to flatten the surface of the insulating film 39.

Next, a photoresist 43 is formed on the entire upper surface of the insulating film 39 by spin coating. Continuing,
An exposure process and a development process are performed using a predetermined photomask, and the photoresist 43 is patterned so that a region where a contact hole is formed is opened. Continuing,
The contact hole 31 is formed by etching until the insulating film 39 in the opening of the photoresist 43 is completely removed. Then, the photoresist 43 is removed.

Subsequently, as shown in FIG. 2, the SOI substrate 5
A metal electrode material (not shown) for forming the metal electrode 11 is film-formed on the entire upper surface of 3. Next, a photoresist (not shown) is formed on the entire upper surface of the metal electrode material (not shown) by a spin coating method. Then, using a predetermined photomask, perform exposure processing and development processing,
A photoresist (not shown) is patterned so as to remain on the region to be the metal electrode 11.

Subsequently, using a photoresist (not shown) as an etching mask, etching is performed until the metal electrode material in the photoresist opening is completely removed to form a metal electrode 11. Then, the photoresist is removed.

In this way, as shown in FIG. 2, the P-channel FE formed on the SOI substrate according to the conventional technique is formed.
The T33 and the N-channel FET 35 can be manufactured.

[0029]

The SOI as described above
In a semiconductor device using a substrate, when mounting an IC,
In the face-up mounting method, it is necessary to add a process for forming a good electrical contact on the back surface of the supporting substrate, and the potential of the supporting substrate is limited to the ground potential on the mounting substrate side. In the face-down mounting method, it is difficult to bias or ground the supporting substrate.

[Object of the Invention] The object of the present invention is to solve the above-mentioned problems and to use S
An object of the present invention is to provide a semiconductor device in which a supporting substrate of a semiconductor device using an OI substrate can be easily grounded or biased, and a manufacturing method thereof.

[0031]

In order to achieve the above object, a semiconductor device and a manufacturing method thereof according to the present invention employ the structure and manufacturing method described below.

In the semiconductor device of the present invention, a plurality of semiconductor elements insulated from each other by an insulating film are provided on the buried oxide film of the SOI substrate having the buried oxide film provided on the silicon support substrate. In the semiconductor device, a substrate contact hole which is provided in a region insulated from each of the semiconductor elements by the insulating film and penetrates the insulating film and the buried oxide film, and the support in the opening portion by the substrate contact hole are provided. A high-concentration diffusion layer of the same conductivity type as that of the supporting substrate provided on the surface of the substrate and the high-concentration diffusion layer filled in the substrate contact hole and electrically connected, and a pad portion is formed on the insulating film. It has a metal electrode extended.

The semiconductor device of the present invention is provided with a protective film that covers each of the semiconductor elements, and a connection electrode that is connected to the pad portion from above the protective film through an opening provided in the protective film. And

The semiconductor device of the present invention is characterized in that the support substrate has a rectangular or rectangular shape, and the connection electrodes are provided along the peripheral edge of the support substrate.

The semiconductor device of the present invention is characterized in that the opening of the insulating film forming the substrate contact hole is larger than the opening of the buried oxide film.

In the semiconductor device of the present invention, the plurality of semiconductor elements are provided on the plurality of element regions formed by the surface silicon layer of the SOI substrate, with the gate electrode and the drain layer on both sides thereof via the gate oxide film. And a source layer, and a single drain type field effect transistor in which a metal electrode extending on the protective film is provided on each of the gate electrode, the drain layer, and the source layer.

In the semiconductor device of the present invention, the plurality of semiconductor elements are provided on the plurality of element regions formed by the surface silicon layer of the SOI substrate, with the gate electrode and the drain layer on both sides thereof through the gate oxide film. And a source layer are formed, the gate electrode has a sidewall, and a low-concentration drain layer is formed under the sidewall, and the gate electrode, the drain layer, and the source layer each extend over the protective film. It is a field effect transistor provided with an electrode.

In the semiconductor device of the present invention, the plurality of semiconductor elements are formed on the plurality of element regions formed by the surface silicon layer of the SOI substrate, with the gate electrode and the drain layer on both sides thereof via the gate oxide film. And a source layer, an offset region is provided between the gate electrode and the drain layer, and the gate electrode, the drain layer, and the source layer are each provided with a metal electrode extending on the protective film. Is characterized in that.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate having a surface silicon layer formed on a silicon supporting substrate with a buried oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a step of forming each of the low-concentration P-type or N-type regions. Forming a drain layer and a source layer by selectively ion-implanting impurity atoms having conductivity types opposite to those of the region on both sides of the gate electrode; and selectively etching the buried oxide film and the field oxide film. The step of forming a substrate contact hole on the supporting substrate, and ion-implanting an impurity atom of the same conductivity type as that of the supporting substrate into a portion of the supporting substrate exposed in the substrate contact hole for high concentration diffusion. A step of forming a layer, and after forming an insulating film on the entire surface of the supporting substrate, a photo-etching process is performed to form each gate electrode, drain layer, and saw in each element region. Forming element contact holes at positions corresponding to the layers individually, and forming contact holes at positions corresponding to the substrate contact holes, and the entire surface of the insulating film and all the contact holes. After forming the metal electrode layer, a photoetching process is performed to form an independent metal electrode for each contact hole. At that time, the metal electrode formed in the substrate contact hole extends over the insulating film. And a metal electrode forming step of forming a pad portion as well.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate with a buried oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a step of forming each of the low-concentration P-type or N-type regions. Forming a low concentration drain layer by selectively ion-implanting impurity atoms opposite in conductivity type to the both sides of the gate electrode; and forming a sidewall of a silicon oxide film on both sides of each gate electrode. And a region outside the sidewall on both sides of the gate electrode in each of the low-concentration P-type or N-type regions is selectively ion-implanted with an impurity atom having the same conductivity type as that of the low-concentration drain layer. Forming a layer and a source layer; forming a substrate contact hole on the supporting substrate by selectively etching the buried oxide film and the field oxide film; Forming a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as the supporting substrate into a portion of the supporting substrate exposed in the substrate contact hole; and forming an insulating film on the entire surface of the supporting substrate. After that, by performing a photo-etching process, device contact holes are formed at the positions corresponding to the respective gate electrodes, drain layers, and source layers of the device regions, respectively, and at positions corresponding to the substrate contact holes. Also, a step of forming a contact hole, and after forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, a photoetching process is performed to form an independent metal electrode for each contact hole. And a pad portion extending on the insulating film is also formed on the metal electrode formed in the substrate contact hole. And a step of forming a metal electrode to be formed.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate having a surface silicon layer formed on a silicon supporting substrate with a buried oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a step of forming each of the low-concentration P-type or N-type regions. A step of selectively ion-implanting an impurity atom whose conductivity type is opposite to the region on one side of the gate electrode to form an offset region; and a step of performing heat treatment to diffuse the impurity atom of the offset region, A drain layer and a source layer are formed by selectively ion-implanting impurity atoms having the same conductivity type as that of the offset region into regions of the low-concentration P-type or N-type region on both sides of the gate electrode except the offset region. And a step of forming a substrate contact hole on the supporting substrate by selectively etching the buried oxide film and the field oxide film, the supporting substrate A step of ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate to form a high-concentration diffusion layer in a portion exposed in the substrate contact hole; By performing the etching process, element contact holes are formed at the positions corresponding to the respective gate electrodes, drain layers, and source layers of the respective element regions, and contact is also made to the positions corresponding to the substrate contact holes. After forming a metal electrode layer in the step of forming a hole and the entire surface of the insulating film and all the contact holes, an independent metal electrode is formed for each contact hole by performing a photoetching process, At that time, a pad portion extending on the insulating film is also formed on the metal electrode formed in the substrate contact hole. And a metal electrode forming step.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate electrode on each of the low concentration P-type or N-type regions via a gate oxide film, and a step of forming each of the low concentration P-type or N-type regions. Reverse the order of the step of selectively implanting impurity atoms having a conductivity type opposite to that of the region to form the offset region and the step of diffusing the impurity atoms of the offset region by performing heat treatment, The impurity atoms in the offset region are diffused by performing a step of selectively ion-implanting an impurity atom having a conductivity type opposite to that of the low concentration P-type or N-type region to form an offset region and heat treatment. After the step, the step is performed after the step of forming a gate electrode on each of the low concentration P-type or N-type regions via a gate oxide film.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate with a buried oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and a step of forming the buried oxide film and the field oxide film. A step of forming a substrate contact hole on the supporting substrate by selectively etching; and impurity atoms having a conductivity type opposite to that of the gate electrode in each of the low concentration P type or N type regions. A drain layer and a source layer are formed by selective ion implantation. At this time, impurity atoms of the same conductivity type as those of the supporting substrate are ion-implanted into a portion of the supporting substrate exposed in the substrate contact hole. After forming a concentration diffusion layer and forming an insulating film on the entire surface of the supporting substrate,
By performing the photo-etching process, device contact holes are formed at the positions corresponding to the respective gate electrodes, drain layers, and source layers of the device regions, and at the positions corresponding to the substrate contact holes. A step of forming a contact hole, and after forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, a photoetching process is performed to form an independent metal electrode for each contact hole. At that time, a metal electrode forming step of forming a pad portion extending on the insulating film on the metal electrode formed in the substrate contact hole is also included.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate having a surface silicon layer formed on a silicon support substrate with an embedded oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a step of forming each of the low-concentration P-type or N-type regions. Forming a low concentration drain layer by selectively ion-implanting impurity atoms opposite in conductivity type to the both sides of the gate electrode; and forming a sidewall of a silicon oxide film on both sides of each gate electrode. And a step of forming a substrate contact hole on the supporting substrate by selectively etching the buried oxide film and the field oxide film, and the gate of each of the low concentration P-type or N-type regions. Drain layers and source layers are formed by selectively ion-implanting impurity atoms having the same conductivity type as the low-concentration drain layer into regions outside the sidewalls on both sides of the electrode. A step of forming a high concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate into a portion of the supporting substrate exposed in the substrate contact hole, and forming an insulating film on the entire surface of the supporting substrate. After that, by performing a photo-etching process,
Forming a contact hole for an element at a position corresponding to each gate electrode, a drain layer, and a source layer of each element region, and forming a contact hole at a position corresponding to the substrate contact hole;
After forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, an independent metal electrode is formed for each contact hole by performing a photoetching process, and at that time, the substrate contact hole is formed. A metal electrode forming step of forming a pad portion extending on the insulating film on the metal electrode formed on the substrate.

According to the method of manufacturing a semiconductor device of the present invention, an SOI substrate having a surface silicon layer formed on a silicon supporting substrate with a buried oxide film interposed is prepared, and a pad oxide film is formed on the surface of the surface silicon layer. Forming a silicon nitride film and performing a photoetching process to perform patterning so that the silicon nitride film and the pad oxide film remain on the device region; and forming a field oxide film on the device isolation region of the SOI substrate. And forming a plurality of independent device regions by the surface silicon layer, removing the silicon nitride film and the pad oxide film, and adding impurity atoms having a P-type or N-type conductivity A step of selectively ion-implanting a plurality of element regions to form a plurality of low-concentration P-type or N-type regions; Is a step of diffusing impurity atoms in the N-type region, a step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and a step of forming the gate electrode in each of the low-concentration P-type or N-type regions. A step of selectively implanting an impurity atom having a conductivity type opposite to that of the region to form an offset region; a step of performing a heat treatment to diffuse the impurity atom of the offset region; and the buried oxide film and Forming a substrate contact hole on the supporting substrate by selectively etching the field oxide film, and a region excluding the offset region on both sides of the gate electrode in each of the low concentration P type or N type regions. To form a drain layer and a source layer by selectively ion-implanting impurity atoms whose conductivity type is the same as that of the offset region. A step of forming a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate into a portion exposed in the supporting substrate, and a photo-etching process after forming an insulating film on the entire surface of the supporting substrate. By doing so, the device contact holes are formed at the positions corresponding to the respective gate electrodes, drain layers, and source layers of the device regions, and contact holes are also formed at the positions corresponding to the substrate contact holes. Forming step, and after forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, an independent metal electrode is formed for each contact hole by performing a photoetching process. A metal electrode forming step of forming a pad portion extending on the insulating film on the metal electrode formed in the substrate contact hole, It is characterized by having.

The method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a step of forming each of the low-concentration P-type or N-type regions. Reverse the order of the step of selectively implanting impurity atoms having a conductivity type opposite to that of the region to form the offset region and the step of diffusing the impurity atoms of the offset region by performing heat treatment, The impurity atoms in the offset region are diffused by performing a step of selectively ion-implanting an impurity atom having a conductivity type opposite to that of the low concentration P-type or N-type region to form an offset region and heat treatment. After the step, a step of forming a gate electrode on each of the low concentration P-type or N-type regions via a gate oxide film is performed.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method of manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method for manufacturing a semiconductor device of the present invention, after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the protective film corresponds to the pad portion. It is characterized by including a step of forming an opening at a position and a step of forming a connection electrode on the protective film through the opening and connecting to the pad section.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method for manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Characterize.

[Operation] In the semiconductor device of the present invention, since an electrode having electrical contact with the support substrate is formed on the front surface of the IC chip, no matter what mounting method is used,
The support substrate can be set to ground or any bias.

[0064]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the present invention will be described below with reference to the drawings.

[Structure of Semiconductor Device: FIG. 1] FIG. 1 is a schematic cross-sectional view showing an enlarged main part of a semiconductor device according to an embodiment of the present invention. In the following description, parts corresponding to those of the conventional example shown in FIGS. 2 to 9 are designated by the same reference numerals.

The semiconductor device 10 shown in FIG. 1 is similar to the conventional semiconductor device described with reference to FIG. 2 in that a buried oxide film 3 is provided on a silicon support substrate 7, and a surface silicon layer is provided thereon. The buried SOI film 53 is used, and the P-channel FET 33 and the N-channel FET 35, which are a plurality of semiconductor elements insulated from each other by the insulating film 39 and the field oxide film 57, are provided on the buried oxide film 3. It is an IC chip.

The buried oxide film 3 provided on the support substrate 7 of the SOI substrate 53 has a film thickness of about 0.1 to 1 μm, and the film thickness on the buried oxide film 3 is 0.1 to 5 μm. A degree of surface silicon layer is provided. However, in FIG. 1, the surface silicon layer is partially removed to form a plurality of island-shaped element regions, and impurities are injected and diffused into the respective element regions, so that the low concentration N-type regions 15 and It is a concentration P-type region 13.

In the P-channel FET 33, a gate electrode 37 is formed in the center of the low-concentration N-type region 15 via a gate oxide film 17, and a P-type drain layer 23 and a P-type source layer 25 are formed on both sides of the gate electrode 37. And its gate electrode 37, P
The metal electrode 11 extending on the insulating film 39 through the contact hole 31 is provided in each of the type drain layer 23 and the P type source layer 25.

In the N-channel FET 35, a gate electrode 37 is formed in the center of the low-concentration P-type region 13 via a gate oxide film 17, and an N-type drain layer 27 and an N-type source layer 29 are formed on both sides of the gate electrode 37. The gate electrode 37, N
The metal electrode 11 extending on the insulating film 39 through the contact hole 31 is provided in each of the type drain layer 27 and the N type source layer 29.

In both the P-channel FET 33 and the N-channel FET 35, the metal electrode connected to the gate electrode 37 is
It is not shown in FIG. 1 because it is provided at a sectional position different from that in FIG. Further, a pad portion provided with an input / output terminal is formed on one of the many metal electrodes 11 that is connected to the outside.

Low concentration N-type region 15 and N-type drain layer 27
Phosphorus atoms are used as impurities in the N-type source layer 29 and boron atoms are used as impurities in the low-concentration P-type region 13, the P-type drain layer 23, and the P-type source layer 25. Polycrystalline silicon is used for the gate electrode 37. A silicon oxide film is used for the gate oxide film 17.

P-channel FET 33 and N-channel FET
35, the conductivity types of the low-concentration region and the drain layer and the source layer are opposite, but the basic configuration is common.
The pair of P-channel FET 33 and N-channel FET 35 constitutes a CMOS transistor.

This semiconductor device 10 differs from the conventional semiconductor device shown in FIG. 2 in the following points. That is, the P-channel FET 33 and the N-channel FET 35
Is a region insulated by the insulating film 39 and the field oxide film 57, and the substrate contact hole 5 is formed in the buried oxide film 3 and the field oxide film 57.
This is that a contact hole 30 larger than that is formed at a position corresponding to the substrate contact hole 5 of the substrate 9. The contact hole 30 in the insulating film 39 also constitutes a substrate contact hole.

Further, a high-concentration diffusion layer 9 of the same conductivity type as that of the supporting substrate 7 is formed on the surface of the supporting substrate 7 in the opening formed by the substrate contact hole 5, and is filled in the substrate contact hole 5 and the contact hole 30. That is, the metal electrode 11 made of aluminum, which is electrically connected to the high-concentration diffusion layer 9 and has the pad portion 47 extended on the insulating film 39, is provided. The high-concentration diffusion layer 9 is formed by implanting and diffusing boron atoms which are P-type impurities when the conductivity type of the support substrate 7 is P-type and phosphorus atoms which are N-type impurities when it is N-type.

Further, in this embodiment, a passivation film 41 is provided as a protective film for covering the P-channel FET 33 and the N-channel FET 35 which are semiconductor elements and the metal electrode 11, and the passivation film 41 is provided through the opening 65 provided in the passivation film 41. A connection electrode 67 that is connected to the pad portion 47 from above 41 is provided.

The size of the contact hole 30 of the insulating film 39 is made larger than the substrate contact hole 5 of the buried oxide film 3 and the field oxide film 57 because the inner peripheral shape of the entire substrate contact hole is stepped. This is to enhance the adhesiveness when forming the metal electrode 11 by sputtering aluminum.

This semiconductor device 10 has its element surface (see FIG.
The pad portion 47 and the connection electrode 67 are provided on the upper surface) and are electrically connected to the support substrate 7 through the metal electrode 11 and the high-concentration diffusion layer 9.

Therefore, in the semiconductor device 10, the pad portion 47 of the metal electrode 11 or the connecting electrode 67 is used regardless of whether the mounting method on the mounting substrate such as the lead frame is the face-up mounting method or the face-down mounting method.
Can be electrically connected to a terminal or a lead electrode on the mounting substrate side. Thereby, the support substrate 7 of the semiconductor device 10 can be set to the ground or an arbitrary bias, so that the operation of the semiconductor device 10 can be easily stabilized.

Even when the conventional semiconductor device is mounted by the face-up mounting method, if a process for forming a good electrical contact on the back surface of the supporting substrate is added, the supporting substrate is provided with lead electrodes on the mounting substrate side. Although it can be grounded through the above, in the case of the semiconductor device 10 according to the present invention described above, it is not necessary to add such a process. Moreover, the potential of the support substrate 7 is controlled by the potential from the outside connected through the metal electrode 11 and is not limited to the ground potential of the package. Therefore, it is possible to drive multiple power sources in which a plurality of voltages can be used properly. The advantages of the semiconductor device manufactured using the SOI substrate can be utilized.

Even when the semiconductor device 10 is mounted by the face-down mounting method, the supporting substrate 7 can be easily grounded or biased, so that the potential of the supporting substrate can be stabilized and the floating state can be achieved. It will never happen.

[First Embodiment of Method for Manufacturing Semiconductor Device: FIGS. 1, 3 to 8, 10, and 11] Next, as a first embodiment of the method for manufacturing a semiconductor device according to the present invention, A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 1, 3 to 8, 10, and 11.
Will be explained. FIG. 1, FIG. 3 to FIG. 8, FIG. 10 and FIG. 11 are schematic cross-sectional views sequentially showing the state in each step for explaining the method of manufacturing the semiconductor device.

First, as shown in FIG. 3, a buried oxide film 3 having a film thickness of 0.1 to 1 μm is provided on a support substrate 7 made of silicon. 1 to 5
SOI substrate 5 provided with a surface silicon layer 1 of about μm
Prepare 3. Then, on the SOI substrate 53, as shown in FIG.
The P-channel FET 33 and the N-channel FET 35, which are the semiconductor elements shown in, are formed as follows.

First, at a temperature of 1000 in an oxidizing atmosphere.
Heat treatment is performed at a temperature of 60 ° C. for about 60 minutes to form a pad oxide film 61 with a thickness of about 30 nm on the surface of the surface silicon layer 1.
To form. Then, dichlorosilane (Si
A silicon nitride film 63 having a film thickness of about 150 nm is formed by a chemical vapor deposition (CVD) method using H2Cl2) and ammonia (NH3).

Subsequently, on the entire upper surface of the SOI substrate 53,
A photoresist 43 is formed on the entire upper surface by spin coating. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 43 is patterned so as to remain on the element region.

Then, as shown in FIG. 4, the silicon nitride film 63 in the opening of the photoresist 43 is completely removed by reactive ion etching using sulfur hexafluoride (SF6) and helium (He) as a reaction gas. Remove. Further, hydrofluoric acid (HF) is used as an etching solution to completely remove the pad oxide film 61 in the opening of the photoresist 43.

Subsequently, carbon tetrafluoride (CF
4) and the surface silicon layer 1 in the opening of the photoresist 43 is slightly etched by more than half the film thickness by reactive ion etching using chlorine (Cl2). If the surface silicon layer 1 has a thickness of 1 μm, it is etched by about 0.7 μm. Then, the photoresist 43 is removed using sulfuric acid (H2SO4).

Next, as shown in FIG. 5, a film thickness of 8 is obtained under the conditions of a temperature of 1000 ° C. and a time of about 3 hours in an oxidizing atmosphere.
A field oxide film 57 having a thickness of about 00 nm is formed. As a result, the field oxide film 57 and the buried oxide film 3 in the element isolation region are in contact with each other, and each element region is formed in an island shape. Subsequently, the silicon nitride film (not shown) is completely removed by using phosphoric acid (H3PO4) as an etching solution.
After that, the pad oxide film (not shown) is removed by using hydrofluoric acid as an etching solution.

Next, as shown in FIG. 6, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the region to be the low concentration N-type region 15 is opened. Subsequently, using a photoresist as an ion implantation blocking film, N-type impurities (not shown) are ion-implanted under the conditions of implantation energy of 50 KeV and implantation dose of about 1 × 10 12 cm −2. A phosphorus atom is used as the N-type impurity. Then, the photoresist is removed using sulfuric acid.

Next, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the region to be the low-concentration P-type region 13 is opened. Next, using photoresist as an ion implantation blocking film,
Implant energy 50 KeV, Implant dose 1 ×
P-type impurities (not shown) are ion-implanted under the condition of about 1012 cm-2. A boron atom is used as the P-type impurity. Then, the photoresist is removed using sulfuric acid.

Then, in a nitrogen atmosphere, the temperature is set to 1000.
Heat treatment is performed at a temperature of about 3 hours for diffusing the N-type impurity and the P-type impurity ion-implanted in the above step,
A low concentration N-type region 15 and a low concentration P-type region 13 are formed.

Next, as shown in FIG. 7, in a mixed atmosphere of oxygen and nitrogen in which oxygen and nitrogen are mixed to reduce the pressure of oxygen, oxidation treatment is performed under the conditions of a temperature of 1000 ° C. and a time of about 30 minutes. Then, a gate oxide film 17 having an oxide film thickness of about 20 nm is formed on the entire surface of the SOI substrate 53 including the low concentration P type region 13 and the low concentration N type region 15.

Further, monosilane (SiH
4) is used to remove a gate electrode material (not shown) made of polycrystalline silicon from the gate oxide film 17 by using the CVD method.
A film having a film thickness of about 350 nm is formed on the entire upper surface.

Subsequently, a photoresist (not shown) is formed on the entire surface of the gate electrode material (not shown) by a spin coating method, an exposure process and a development process are performed using a predetermined photomask, and a gate is formed. The photoresist is patterned so as to remain on the region where the electrode is formed.

Subsequently, reactive ion etching using carbon tetrafluoride and chlorine as a reaction gas is performed to completely remove the gate electrode material in the opening of the photoresist (not shown).
The gate electrode 37 is formed. By this etching, a gate electrode 37 is formed on the low-concentration N-type region 15 and the low-concentration P-type region 13 through the gate oxide film 17 in the respective central portions. Then, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 8, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask. The photoresist is patterned so that the position corresponding to the low concentration N-type region 15 is opened.

Subsequently, using a photoresist (not shown) as an ion implantation blocking film, an implantation energy of 2 was used.
A P-type impurity (not shown) is selectively ion-implanted on both sides of the gate electrode 37 on the low-concentration N-type region 15 under the conditions of 5 KeV and a dose amount of about 3 × 10 15 cm −2. Thereby, the P-type drain layer 23 and the P-type source layer 25 are formed. A boron atom is used as the P-type impurity. Then, the photoresist is removed using sulfuric acid.

Next, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 53 by a spin coating method,
An exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that the position corresponding to the low concentration P-type region 13 is opened.

Then, using a photoresist (not shown) as an ion implantation blocking film, an implantation energy of 5 is applied.
An N-type impurity (not shown) is selectively ion-implanted on both sides of the gate electrode 37 on the low-concentration P-type region 13 under the conditions of 0 KeV and a dose amount of 3 × 10 15 cm −2. Thereby, the N-type drain layer 27 and the N-type source layer 29 are formed. A phosphorus atom is used as the N-type impurity. Then, the photoresist is removed using sulfuric acid.

Next, steps specific to the method for manufacturing a semiconductor device according to the present invention will be described. First, as shown in FIG. 10, a photoresist 43 is formed on the entire upper surface of the SOI substrate 53 by a spin coating method, an exposure process and a development process are performed using a predetermined photomask, and a region to be a substrate contact hole is formed. The photoresist 43 is patterned so as to be opened. Subsequently, using the photoresist 43 as an etching mask, hydrofluoric acid is used as an etching solution to completely remove the field oxide film 57 and the buried oxide film 3 in the opening of the photoresist 43.

Further, using the photoresist 43 as an ion implantation blocking film, the same conductivity type impurity as that of the supporting substrate 7 is selectively ion-implanted into the portion of the supporting substrate 7 exposed in the substrate contact hole 5. When implanting N-type impurities, phosphorus atoms are ion-implanted under the conditions of implantation energy of 50 KeV and implantation dose of about 3 × 10 15 cm −2. When implanting P-type impurities, implantation energy is 25 KeV and implantation dose is 3 × 1015.
Boron atoms are ion-implanted under the condition of about cm −2.
Then, when the photoresist 43 is removed using sulfuric acid, the high-concentration diffusion layer 9 is formed in the substrate contact hole 5 near the surface of the supporting substrate 7.

Next, as shown in FIG. 11, an insulating film 3 made of a silicon oxide film containing phosphorus and boron as impurities is formed by a CVD method using monosilane and phosphine (PH3) and diborane (B2H6) as reaction gases.
9 is formed on the entire surface of the SOI substrate 53 with a film thickness of about 0.5 μm.

Then, in a nitrogen atmosphere, the temperature was set to 900 ° C.
Heat treatment is performed for about 0 minutes. Thereby, the P-type impurity and the N-type impurity are electrically activated to form the P-type drain layer 23, the P-type source layer 25, the N-type drain layer 27, the N-type source layer 29, and the high-concentration diffusion layer 9. . The heat treatment in the nitrogen atmosphere also serves to flatten the surface of the insulating film 39.

Next, a photoresist 43 is formed on the entire upper surface of the insulating film 39 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask. Thereby, the gate electrode 37 and the drain layer 2 in each element region are formed.
The photoresist 43 is patterned so that the holes corresponding to the holes 3, 27, the source layers 25, 29, and the substrate contact hole 5 are individually opened. However, the opening at a position corresponding to the gate electrode 37 is formed in a cross section different from that in FIG.

Subsequently, the insulating film 39 and the gate oxide film 17 in the opening of the photoresist 43 are completely removed by reactive ion etching using carbon tetrafluoride, methane trifluoride (CHF3) and helium as reaction gases. Etching is performed to form contact holes 30 and 31.
Then, the photoresist 43 is removed using sulfuric acid.

As a result, element contact holes 31 are formed in the insulating film 39 in respective element regions at positions corresponding to the gate electrode 37, the drain layers 23 and 27, and the source layers 25 and 29, respectively, and the substrate contact is performed. The contact hole 30 is also at the position corresponding to the hole 5.
To form. However, the element contact hole corresponding to the gate electrode 37 is formed at a cross-sectional position different from that shown in FIG.

Subsequently, a metal electrode forming step is performed. First,
As shown in FIG. 1, a metal electrode material (not shown) for forming a metal electrode is formed to a thickness of about 1 μm on the entire surface of the insulating film 39 and all the contact holes 30 and 31 by a sputtering method. To form a film. Aluminum is used as the metal electrode material.

Next, a photoresist (not shown) is formed on the entire upper surface of the metal electrode material (not shown) by a spin coating method, and an exposure process is performed using a predetermined photomask.
A development process is performed, and the photoresist is patterned so as to remain on the region to be the metal electrode 11.

Subsequently, by using a photoresist (not shown) as an etching mask, reactive ion etching using boron trichloride (BCl3) and chlorine as a reaction gas was performed to remove a portion not covered with the photoresist. Etching is performed until the metal electrode material is completely removed to form the metal electrode 11. Then, the photoresist is removed using nitric acid (HNO3).

As a result, the gate electrode 37, the P-type drain layer 23, and the P-type source layer 25 on the low concentration N-type region 15 are formed.
, The metal electrode 11 connected individually through the element contact holes 31 is formed (however, the metal electrode connected to the gate electrode 37 is formed at a cross-sectional position different from that in FIG. 1), and the P-channel FET 33 is formed. Is completed.

Further, on the gate electrode 37, the N-type drain layer 27, and the N-type source layer 29 on the low-concentration P-type region 13, the metal electrodes 11 which are individually connected through the contact holes 31 for the element are formed. (However, the gate electrode 37
The metal electrode connected to is formed at a cross-sectional position different from that of FIG. 1), and the N-channel FET 35 is completed.

Further, the contact hole 3 of the insulating film 39
0, and a metal electrode 11 connected to the high-concentration diffusion layer 9 of the supporting substrate 7 through the substrate contact hole 5 is also formed, and the metal electrode 11 has a pad portion 47 extending on the insulating film 39.
There is one that has.

Next, a passivation film 41 made of a silicon nitride film having a thickness of 0.8 μm is formed on the entire surface of the insulating film 39 including the respective metal electrodes 11 by a CVD method using monosilane and ammonia as a reaction gas. A film is formed to some extent. Further, a photoresist (not shown) is formed on the entire upper surface of the passivation film 41 by a spin coating method. Then, using a predetermined photomask, an exposure process and a development process are performed, and the photoresist is patterned so that the region to be the pad portion 47 is opened.

Then, this photoresist (not shown)
Is used as an etching mask, by reactive ion etching using carbon tetrafluoride and oxygen as a reaction gas,
Etching is performed until the passivation film 41 in the photoresist opening is completely removed. Then, the photoresist is removed using nitric acid. As a result, an opening is formed in the passivation film 41 and the pad portion 47 of the metal electrode 11 is exposed.

The semiconductor device (IC chip) 10 is completed by gold-plating the pad portion 47 to form the connection electrode 67 shown in FIG. Although not shown, such a connection electrode 67 is also formed on the pad portion of the metal electrode 11 of the semiconductor element that is connected to the outside.

According to this manufacturing method, the P-channel FET 33 and the N-channel FE as semiconductor elements are formed on the SOI substrate.
While forming T35, the metal electrode 11 which is in electrical contact with the high-concentration diffusion layer 9 is provided on the surface side of the support substrate 7, and the connection electrode 67 provided on the pad portion 47 is exposed on the upper surface of the semiconductor device. Can be formed. Therefore, in the semiconductor device 10, the support substrate 7 can be grounded or set to an arbitrary bias regardless of the mounting method.

The plane shape of the semiconductor device 10 is the same as the plane shape of the supporting substrate 7, but when it is rectangular or rectangular as shown in FIG. 12, it is along the peripheral edge of the supporting substrate 7. Connection electrodes 67 electrically connected to the support substrate 7 and connection electrodes 68 provided on some of the metal electrodes 11 of the semiconductor element can be arranged on the semiconductor device 10 at a required position.

By using the plurality of connection electrodes 67, it is possible to set the grounding of the support substrate 7 or an arbitrary bias at a desired position. However, the arrangement of the connection electrode 67 is not limited to the peripheral portion of the support substrate 7, and it can be arranged at any position. For example, it may be arranged at a position corresponding to the central portion of the support substrate 7 on the semiconductor device 10.

[Second Embodiment of Semiconductor Device: FIG. 13]
In the first embodiment described above, the semiconductor device in which the field effect transistor (MOSFET) having the single drain structure is formed as the semiconductor element on the SOI substrate has been described. Next, the second embodiment of the semiconductor device according to the present invention will be described. As an LDD (Lightly Do) on the SOI substrate.
A MOSFET having a ped drain structure will be described.

FIG. 13 is a schematic sectional view similar to FIG. 1 showing an enlarged main part of the semiconductor device, and the portions corresponding to FIG. 1 are designated by the same reference numerals. The semiconductor device 70 is different from the semiconductor device 10 of the first embodiment shown in FIG. 1 only in that a MOSFET having an LDD structure is formed as a semiconductor element, and the other points are common. Therefore, in the following description, the description of the MOSFET will be centered, and the description of the other parts will be omitted or simplified.

The semiconductor device 70 shown in FIG.
As a semiconductor element on the buried oxide film 3 of the I substrate 53, a P-channel FET 71 and an N-channel F having an LDD structure are used.
ET73 is formed.

The P-channel FET 71 is formed on the low-concentration N-type region 15 in the element region, and has the following differences from the P-channel FET 33 in the semiconductor device 10 of the first embodiment. That is, the P-channel FET 71 has the sidewalls 49 on both side surfaces of the gate electrode 37, and the P-type low-concentration drain layer 51 is provided on the low-concentration N-type region 15 below each of the sidewalls 49. That is the point. Therefore, the P-type low-concentration drain layer 51 is provided between the gate electrode 37 and the P-type drain layer 23 and between the P-type source layer 25.

The N-channel FET 73 is formed on the low-concentration P-type region 13 in the element region, and has the following differences from the N-channel FET 35 in the semiconductor device 10 of the first embodiment. That is, the N-channel FET 73 has the sidewalls 49 on both side surfaces of the gate electrode 37, and the N-type low-concentration drain layer 52 is provided on the low-concentration P-type region 13 below each of the sidewalls 49. That is the point. Therefore, the N-type low-concentration drain layer 52 is provided between the gate electrode 37 and the N-type drain layer 27 and between the N-type source layer 29.

In the semiconductor device 70 of the second embodiment, as in the semiconductor device 10 of the first embodiment, the metal electrode 11 connected to the support substrate 7 by the high-concentration diffusion layer 9 is also included.
Through the substrate contact hole 5 and the contact hole 30 formed in the insulating film 39.
To the insulating film, the pad portion 47 is extended, and the connection electrode 67 by gold plating is provided there.

Therefore, also with this semiconductor device 70, the same effect as that of the semiconductor device 10 of the first embodiment can be obtained. Further, since the P-channel FET 71 and the N-channel FET 73 are provided with the low-concentration drain layer 51 or 52 between the gate electrode 37 and the drain layer 23 or 27 and between the source layer 25 or 29, respectively, The electric field concentration near the boundary between the drain layer and the channel can be relaxed and the breakdown voltage can be increased.

Moreover, the low-concentration drain layers 51 and 52 are
Since it is formed by self-aligning with the sidewalls 49 provided on both side surfaces of the gate electrode 37, it is possible to form a fine semiconductor element and it can be applied to an IC chip having a high integration density.

Second Embodiment of Method for Manufacturing Semiconductor Device: FIGS. 3 to 7 and FIGS. 13 to 16 Next, as a second embodiment of the method for manufacturing a semiconductor device according to the present invention, the above-mentioned drawings will be described. A method for manufacturing the semiconductor device 70 shown in FIG. 13 will be described with reference to FIGS. 3 to 7, 13 to 16 and the like.

The second embodiment of the method of manufacturing the semiconductor device is a step of forming a semiconductor element as compared with the first embodiment described with reference to FIGS. 1, 3 to 8, 10 and 11. That is, since the steps of forming the P-channel FET 71 and the N-channel FET 73 are partially different, the different steps will be mainly described.

The steps of FIGS. 3 to 7 in the first embodiment are the same in this second embodiment. Therefore, the field oxide film 57 is formed on the surface silicon layer 1 provided on the buried oxide film 3 of the SOI substrate 53 to form the island-shaped separated surface silicon layer 1 in the element region. N-type or P-type impurity atoms are selectively ion-implanted therein, and then heat treatment is performed to form a low-concentration P-type region 13 and a low-concentration N-type region 15. Then, a gate electrode 37 is formed in the central portion on the low-concentration P-type region 13 and the low-concentration N-type region 15 via the gate oxide film 17, respectively, and the state shown in FIG. 7 is obtained.

Next, as shown in FIG. 14, the SOI substrate 5
A photoresist (not shown) formed on the entire surface of 3 is patterned so that the low concentration N-type region 15 is opened.
Then, using the photoresist as an ion implantation blocking film, the conductivity type has a low concentration on both sides of the gate electrode 37 in the low concentration N type region 15 under the conditions of the implantation energy of 25 KeV and the implantation dose amount of about 1 × 10 13 cm −2. P-type impurities opposite to the N-type region 15 are selectively ion-implanted,
A P type low concentration drain layer 51 is formed. A boron atom is used as the P-type impurity. Then, the photoresist is removed using sulfuric acid.

Subsequently, a photoresist (not shown) formed on the entire surface of the SOI substrate 53 is patterned so that the low concentration P type region 13 is opened. Then, using the photoresist as an ion implantation blocking film, the implantation energy is 25 KeV and the implantation dose is 1 × 1013c.
Under the condition of about m−2, on both sides of the gate electrode 37 in the low concentration P-type region 13, the conductivity type N opposite to the low concentration P-type region 13 is set.
A type impurity is selectively ion-implanted to form an N type low concentration drain layer 52. A phosphorus atom is used as the N-type impurity. Then, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 15, a PSG film is formed on the entire surface to a film thickness of about 0.3 μm by the CVD method using monosilane and phosphine as a reaction gas. Then, the PS of the flat part was removed by reactive ion etching using methane trifluoride and carbon tetrafluoride as reaction gases.
Etching is performed until the G film is completely removed. As a result, the sidewall 49 made of the PSG film is formed on the sidewall of the gate electrode 37.

Then, in a mixed atmosphere of oxygen and nitrogen in which nitrogen is mixed with oxygen to reduce the pressure of oxygen, the temperature is set to 90
Oxidation at 0 ° C for about 30 minutes, film thickness 20 nm
A silicon oxide film is formed to some extent. This silicon oxide film becomes a buffer film for implanting desired ions at the time of ion implantation described later.

After that, in the same process as described in the first embodiment with reference to FIG. 8, P-type impurity ions are selectively implanted into both sides of the gate electrode 37 in the low-concentration N-type region 15 to reduce the low-concentration. Ion implantation of N-type impurities is selectively performed on both sides of the gate electrode 37 in the P-type region 13.

As a result, as shown in FIG. 16, the low concentration N
The P-type drain layer 23 and the P-type source layer 25 are formed in the mold region 15.
However, the N-type drain layer 27 and the N-type source layer 29 are formed in the low-concentration P-type region 13. However, since impurities are not ion-implanted directly under the sidewalls 49 on both sides of the gate electrode 37, the regions self-aligned with the sidewalls 49 remain as P-type and N-type low-concentration drain layers 51, 52.

After that, the first embodiment shown in FIG.
The substrate contact hole 5, the high-concentration diffusion layer 9, the insulating film 39, the contact holes 30 and 31, the metal electrode 1 are subjected to the same steps as those described with reference to FIGS. 10 and 11.
1, the passivation film 41, and the connection electrode 67 are sequentially formed to complete the semiconductor device 70 shown in FIG.

[Third Embodiment of Semiconductor Device: FIG. 17]
Next, a third embodiment of the semiconductor device according to the present invention is shown in FIG.
Explained by. FIG. 17 is a schematic sectional view showing an enlarged main part of the semiconductor device.

The semiconductor device 80 shown in FIG. 17 is SOI.
As a plurality of semiconductor elements on the buried oxide film 3 of the substrate 53,
Offset drain structure field effect transistor (MO
The difference from the semiconductor device 10 of the first embodiment shown in FIG. 1 and the semiconductor device 70 of the second embodiment shown in FIG. 13 is that the SFET) is formed. Therefore, in FIG. 17, parts common to those in FIGS. 1 and 13 are designated by the same reference numerals, and description thereof will be omitted.

In the semiconductor device 80 of the third embodiment shown in FIG. 17, P channel FET 75 and N channel FET 77 having an offset drain structure are formed on buried oxide film 3 of SOI substrate 53, respectively. With this, similarly to the P-channel FET 71 and the N-channel FET 73 having the LDD structure in the semiconductor device 70 shown in FIG. 13, the electric field concentration between the drain layer and the channel can be relaxed and the breakdown voltage can be increased. Further, in the offset drain structure, the length of the offset region can be adjusted by the photomask, so that it is possible to obtain a higher breakdown voltage than the LDD structure.

The P-channel FET 75 is formed in the low-concentration N-type region 15 in the element region, and differs from the P-channel FET 33 of the semiconductor device 10 shown in FIG. 1 in the following points. That is, the formation position of the gate oxide film 17 and the gate electrode 37 in the low concentration N-type region 15 is shifted to the P-type source layer 25 side, and the P-type between the gate electrode 37 and the P-type drain layer 23. The offset region 19 is provided.

The N-channel FET 77 is formed in the low concentration P-type region 13 in the element region, and differs from the N-channel FET 35 of the semiconductor device 10 shown in FIG. 1 in the following points. That is, the formation positions of the gate oxide film 17 and the gate electrode 37 in the low concentration P-type region 13 are shifted to the N-type source layer 29 side, and the N-type between the gate electrode 37 and the N-type drain layer 27. The offset area 21 is provided.

Also in this semiconductor device 80, the metal electrode 11 and the connection electrode 67 electrically connected to the support substrate 7 of the SOI substrate 53 are provided on the element surface side, that is, the semiconductor device 10 of each of the above-described embodiments. , 70, and whatever the mounting method, the supporting substrate 7 can be grounded or set to an arbitrary bias.

In the first to third embodiments of the semiconductor device described above, an example in which three types of CMOS transistors are formed as semiconductor elements on the buried oxide film of the SOI substrate has been described, but the semiconductor device according to the present invention is described. Are not limited to these, and other field effect transistors (FE
It is also applicable to semiconductor devices having various semiconductor elements such as T) and bipolar transistors. In that case as well, it is possible to obtain the same operational effects as those of the above-described respective embodiments.

[Third Embodiment of Manufacturing Method of Semiconductor Device: FIGS. 3 to 6 and FIGS. 17 to 20] Next, as a third embodiment of the manufacturing method of the semiconductor device according to the present invention, the above-mentioned drawings will be described. A method of manufacturing the semiconductor device 80 shown in FIG. 17 will be described with reference to FIGS. 3 to 6 and FIGS.

The third embodiment of the method of manufacturing the semiconductor device is a step of forming a semiconductor element as compared with the first embodiment described with reference to FIGS. 1, 3 to 8, 10 and 11. That is, since the steps of manufacturing the P-channel FET 75 and the N-channel FET 77 are partly different, the different steps will be mainly described.

The steps of FIGS. 3 to 6 in the first embodiment are substantially the same in this third embodiment. Therefore, the field oxide film 57 is formed on the surface silicon layer 1 provided on the buried oxide film 3 of the SOI substrate 53 to form the island-shaped separated surface silicon layer 1 in the element region. N-type or P-type impurity atoms are selectively ion-implanted therein, and then heat treatment is performed to form a low-concentration P-type region 13 and a low-concentration N-type region 15. Then, as shown in FIG. 18, a gate electrode 37 is formed on the low-concentration P-type region 13 and the low-concentration N-type region 15 through the gate oxide film 17, respectively.

However, in this embodiment, at this time, as shown in FIG. 18, the source layer is formed not in the central portions on the low-concentration N-type region 15 and the low-concentration P-type region 13, but in a later step. Gate electrodes 37 are formed at positions slightly shifted to the left (to the left in FIG. 18) via the gate oxide film 17.

Next, a photoresist (not shown) is applied to the entire surface including the element region on the buried oxide film 3, and as shown in FIG. 19, one side of the gate electrode 37 on the low concentration N-type region 15 is coated. The photoresist is patterned so that the region (on the side where a drain layer is formed in a later step) is opened.

Subsequently, the photoresist (not shown)
As the ion implantation blocking film, the implantation energy is 50 KeV, and the implantation dose is 1 × 1013 cm-2.
Under a condition of about P, a P-type impurity having a conductivity type opposite to that of the low-concentration N-type region 13 is selectively ion-implanted into a region on one side of the P-type offset region 19 shown in FIG.
To form. A boron atom is used as the P-type impurity. Then, the photoresist is removed using sulfuric acid.

Subsequently, a photoresist 43 is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask to open a region on one side of the gate electrode 37 on the low concentration P-type region 13 (a side where a drain layer is formed in a later step). Thus, the photoresist 43 is patterned.

Then, using the photoresist 43 as an ion implantation blocking film, the implantation energy is 50 Ke.
Under conditions of V and implantation dose of about 1 × 10 13 cm −2, an N-type impurity having a conductivity type opposite to that of the low-concentration P-type region 15 is selectively ion-implanted into a region on one side of the low-concentration P-type region 15. The N-type offset region 21 shown in FIG. 19 is formed. A phosphorus atom is used as the N-type impurity. Then, the photoresist 43 is removed using sulfuric acid.

Subsequently, at a temperature of 1100 in a nitrogen atmosphere.
The P-type offset region 1 and the N-type offset region 21 are diffused by ion-implanting the P-type offset region 19 and the N-type offset region 21 by heat treatment at a temperature of about 4 hours.
9 and the N-type offset region 21 are formed.

Subsequently, in a mixed atmosphere of oxygen and nitrogen in which nitrogen is mixed with oxygen to reduce the pressure of oxygen, the temperature is set to 90
Oxidation at 0 ° C for about 30 minutes, film thickness 20nm
A silicon oxide film (not shown) is formed to some extent. This silicon oxide film serves as a buffer film for implanting desired ions at the time of ion implantation described later.

Then, as shown in FIG. 20, a photoresist (not shown) is spin-coated on the SOI substrate 53.
Is formed on the entire upper surface of the. Next, using a predetermined photomask, an exposure process and a development process are performed, and a photoresist is formed so as to open a region in the element region where the P-type drain layer 23 and the P-type source layer 25 of the P-channel FET 75 are formed. Pattern.

Then, this photoresist (not shown)
Is used as an ion implantation blocking film, and the implantation energy is 2
Under conditions of 5 KeV and a dose amount of about 3 × 10 15 cm −2, a P-type impurity having the same conductivity type as the P-type offset region 19 is selectively ion-implanted, and the P-type drain layer 23 and the P-type source layer shown in FIG. 25 is formed. A boron atom is used as the P-type impurity. Then, the photoresist is removed using sulfuric acid.

Then, a photoresist 43 is formed on the entire upper surface of the SOI substrate 53 by a spin coating method. Using a predetermined photomask, perform exposure processing and development processing,
N-type drain layer 2 of N-channel FET 77 in the device region
7 and the photoresist 43 is patterned so that the region where the N-type source layer 29 is formed is opened.

Then, using the photoresist 43 as an ion implantation blocking film, the implantation energy is 40 KeV,
Under the condition that the implantation dose amount is about 3 × 10 15 cm −2,
An N-type impurity having the same conductivity type as that of the N-type offset region 21 is selectively ion-implanted, and the N-type drain layer 27 shown in FIG.
And an N-type source layer 29 are formed. A phosphorus atom is used as the N-type impurity. Then, the photoresist 43 is removed using sulfuric acid.

After that, the first embodiment will be described with reference to FIG.
0, the steps similar to those described with reference to FIGS. 11 and 1, the substrate contact hole 5, the high-concentration diffusion layer 9, the insulating film 39, the contact holes 30 and 31, the metal electrode 1.
1, the passivation film 41, and the connection electrode 67 are sequentially formed to complete the semiconductor device 80 shown in FIG.

The first method of manufacturing a semiconductor device described above
In the third embodiment, the gate electrode 37 and the drain layer 23 of the semiconductor element (P-channel FET 33 and N-channel FET 35 in the first embodiment) are provided in the element regions on the buried oxide film 3 of the SOI substrate 53. , 27 and the source layers 25 and 29 are formed, the substrate contact hole 5
Was formed, and the high-concentration diffusion layer 9 was formed by ion-implanting the impurity having the same conductivity type as that of the supporting substrate 7 in the vicinity of the surface of the supporting substrate 7 exposed thereby.

However, by changing this, after forming each gate electrode 37 of the semiconductor element in each element region on the buried oxide film 3, predetermined regions of the buried oxide film 3 and the field oxide film 57 are formed. The substrate contact hole 5 is formed by selective etching, and then the P-type drain layer 2 of the semiconductor element is formed.
3 and P-type source layer 25, N-type drain layer 27 and N
The high-concentration diffusion layer 9 is formed by injecting impurities also into the vicinity of the surface of the support substrate 7 exposed in the substrate contact holes 5 at the time of injecting P-type or N-type impurities for forming the source regions 29. May be formed.

In this way, the supporting substrate exposed in the substrate contact hole 5 is formed at the same time as either the P-type impurity implantation or the N-type impurity implantation for forming the drain layer and the source layer of the semiconductor element. A high-concentration diffusion layer 9 can be formed by injecting an impurity having the same conductivity type as that of the support substrate 7 near the surface of 7. Therefore, the number of impurity implantation steps can be reduced by one.

In each of the above embodiments, S
The substrate contact hole 5 is formed in the OI substrate 53, the high-concentration diffusion layer 9 is formed in the vicinity of the surface of the support substrate 7 exposed there, and then the insulating film 39 is formed on the buried oxide film 3. 39 was selectively etched to form a contact hole 30 larger than the substrate contact hole 5.

However, by changing this, the SOI substrate 53
After forming the gate electrode, the drain layer, and the source layer of each semiconductor element in each element region on the buried oxide film 3, the insulating film 39 is formed on the entire surface of the buried oxide film 3, and the substrate is formed on the upper surface thereof. A photoresist having an opening only in the contact hole formation region is formed, and the insulating film 39, the field oxide film 57, and the buried oxide film 3 are selectively etched in the same step using the photoresist as a mask to penetrate to the support substrate 7. The high-concentration diffusion layer 9 may be formed in the vicinity of the surface of the support substrate 7 exposed in the substrate contact hole.

Further, in the above-described third embodiment, the P-type or N-type offset regions 19 and 21 are formed after the gate electrode 37 is formed. However, by changing this, after performing ion implantation and heat treatment for forming the low-concentration P-type region 13 and the low-concentration N-type region 15 in each element region on the buried oxide film 3, the P-type offset is performed. Area 1
9 and N-type offset region 21 may be ion-implanted, followed by heat treatment for diffusing the offset region, and thereafter, gate oxide film 17 and gate electrode 37 may be formed.

In this way, after the gate electrode 37 is formed, the heat treatment for diffusing the offset region can be performed at a high temperature as compared with the case where the offset region is formed, so that the breakdown voltage can be further increased. it can.

[0165]

As is apparent from the above description, in the semiconductor device according to the present invention, the metal electrode electrically connected to the support substrate of the SOI substrate is provided on the element surface side of the semiconductor device, and the pad portion of the metal electrode is provided. Since a connection electrode can be provided on the substrate, it becomes possible to establish an electrical connection with the outside through the metal electrode. Therefore, regardless of how the package is mounted on the mounting substrate such as the lead frame, the supporting substrate can be easily grounded or set to an arbitrary bias, and its operation can be stabilized.

Further, when the mounting method is the face-up mounting method, it is possible to construct a multi-power supply circuit capable of properly using a plurality of power supply voltages, and the advantage of using the SOI substrate is brought out. Even when the mounting is performed by the face-down mounting method, the supporting substrate can be grounded or set to an arbitrary bias, so that the potential of the supporting substrate does not become a floating state.
Then, according to the method of manufacturing a semiconductor device of the present invention,
The semiconductor device of the present invention having such effects can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure of a semiconductor device and a method for manufacturing the same in a conventional technique.

FIG. 3 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 4 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 5 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 6 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 7 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 8 is a cross-sectional view showing a structure of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention and a conventional technique.

FIG. 9 is a cross-sectional view showing a structure of a semiconductor device and a method of manufacturing the same according to a conventional technique.

FIG. 10 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 12 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention.

[Explanation of symbols]

1 Surface silicon layer 3 Buried oxide film 5 PCB contact hole 7 Support substrate 9 High concentration diffusion layer 10, 70, 80 Semiconductor device 11 metal electrodes 13 Low concentration P-type region 15 Low concentration N type region 17 Gate oxide film 19 P type offset area 21 N-type offset area 23 P-type drain layer 25 P-type source layer 27 N-type drain layer 29 N-type source layer 31 contact holes 33, 71, 75 P-channel FET 35, 73, 77 N-channel FET 37 Gate electrode 39 Insulating film 41 passivation film 43 Photoresist 47 Pad section 49 Sidewall 51, 52 Low concentration drain layer 53 SOI substrate 57 Field oxide film 61 Pad oxide film 63 Silicon nitride film 65 opening 67 Connection electrode

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F038 CA10 CD04 EZ06 EZ13 EZ14                       EZ15 EZ17 EZ20                 5F110 AA15 AA16 BB04 CC02 DD05                       DD13 DD22 EE09 EE32 EE45                       FF02 FF23 GG02 GG12 GG24                       GG32 GG52 GG58 HJ01 HJ04                       HJ13 HJ23 HL03 HL14 HL23                       HM12 HM14 HM15 NN03 NN04                       NN22 NN24 NN35 NN62 NN66                       QQ11

Claims (31)

[Claims] 1. A semiconductor device in which a plurality of semiconductor elements insulated from each other by an insulating film are provided on an embedded oxide film of an SOI substrate in which an embedded oxide film is provided on a silicon support substrate. A substrate contact hole provided in a region insulated from each of the semiconductor elements by the insulating film and penetrating the insulating film and the buried oxide film, and provided on a surface of the support substrate in an opening formed by the substrate contact hole. A high-concentration diffusion layer having the same conductivity type as that of the supporting substrate, and a metal electrode filled in the substrate contact hole and electrically connected to the high-concentration diffusion layer, and a pad portion extending on the insulating film. A semiconductor device comprising: 2. The semiconductor device according to claim 1, further comprising a protective film that covers each of the semiconductor elements, and a connection electrode that is connected to the pad portion from above the protective film through an opening provided in the protective film. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the support substrate has a rectangular or rectangular shape, and the connection electrodes are arranged along a peripheral portion of the support substrate. 4. The semiconductor device according to claim 1, wherein the opening of the insulating film forming the substrate contact hole is larger than the opening of the buried oxide film. 5. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are provided on a plurality of element regions formed by a surface silicon layer of the SOI substrate, with a gate oxide film interposed between the gate electrode and both sides thereof. A semiconductor device which is a single-drain type field effect transistor in which a drain layer and a source layer are formed in the gate electrode, and a metal electrode extending on the protective film is provided on the gate electrode, the drain layer, and the source layer, respectively. 6. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are provided on a plurality of element regions formed by a surface silicon layer of the SOI substrate, and a gate electrode and both sides thereof are provided via a gate oxide film. A drain layer and a source layer are formed on the gate electrode, the gate electrode has a sidewall, and a low-concentration drain layer is formed under the sidewall, and the gate electrode, the drain layer, and the source layer are on the protective film, respectively. A semiconductor device which is a field-effect transistor provided with a metal electrode extending in a direction. 7. The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are provided on a plurality of element regions formed by a surface silicon layer of the SOI substrate, with a gate electrode and both sides thereof via a gate oxide film. A drain layer and a source layer are formed, an offset region is provided between the gate electrode and the drain layer, and metal electrodes extending on the protective film are provided on the gate electrode, the drain layer, and the source layer, respectively. A semiconductor device which is a field effect transistor. 8. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer, Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to expand the impurity atoms in each of the low-concentration P-type or N-type regions. A step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and a conductive type on both sides of the gate electrode of each of the low-concentration P-type or N-type regions. Forming a drain layer and a source layer by selectively ion-implanting impurity atoms opposite to the region; and selectively etching the embedded oxide film and the field oxide film to form a drain layer and a source layer on the support substrate. Forming a substrate contact hole; forming a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as the supporting substrate into a portion of the supporting substrate exposed in the substrate contact hole; After forming an insulating film on the entire surface of the substrate, a photo-etching process is performed so that the gate electrode, the drain layer, and the source layer of the element regions are individually positioned. A step of forming contact holes for the respective elements and forming contact holes also at positions corresponding to the substrate contact holes, and after forming metal electrode layers on the entire surface of the insulating film and all the contact holes, Independent metal electrodes are formed for each contact hole by performing a photo-etching process. At that time, a metal electrode is also formed on the metal electrode formed in the substrate contact hole to form a pad portion extending on the insulating film. A method of manufacturing a semiconductor device, comprising: 9. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer. Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to expand the impurity atoms in each of the low-concentration P-type or N-type regions. A step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and a conductive type on both sides of the gate electrode of each of the low-concentration P-type or N-type regions. A step of selectively ion-implanting impurity atoms opposite to the region to form a low-concentration drain layer; a step of forming sidewalls made of a silicon oxide film on both side surfaces of each of the gate electrodes; Forming a drain layer and a source layer by selectively ion-implanting an impurity atom having the same conductivity type as that of the low-concentration drain layer into a region outside the sidewall on both sides of the gate electrode in the n-type or N-type region. Forming a substrate contact hole on the support substrate by selectively etching the buried oxide film and the field oxide film; and the substrate contact of the support substrate. Forming a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate into a portion exposed in the through hole; and performing a photoetching process after forming an insulating film on the entire surface of the supporting substrate. By doing so, a device contact hole is formed at a position corresponding to each gate electrode, a drain layer, and a source layer of each device region, and a contact hole is also formed at a position corresponding to the substrate contact hole. And a step of forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, and then performing a photoetching process to form an independent metal electrode for each contact hole, in which case, A metal electrode forming process for forming a pad portion extending on the insulating film on the metal electrode formed in the substrate contact hole. The method of manufacturing a semiconductor device having, when. 10. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer. Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to remove impurity atoms in each of the low-concentration P-type or N-type regions. A step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and a conductive type on one side of the gate electrode of each of the low-concentration P-type or N-type regions. Selectively ion-implants impurity atoms opposite to the region to form an offset region, heat-treating to diffuse the impurity atoms in the offset region, and each of the low-concentration P-type or N-type impurities. Forming a drain layer and a source layer by selectively ion-implanting impurity atoms whose conductivity type is the same as that of the offset region into regions on both sides of the gate electrode of the type region except for the offset region; Forming a substrate contact hole on the supporting substrate by selectively etching the film and the field oxide film; and the substrate contact hole of the supporting substrate. A step of ion-implanting an impurity atom of the same conductivity type as that of the supporting substrate to form a high-concentration diffusion layer in a portion exposed inside the support substrate, and a photoetching treatment after forming an insulating film on the entire surface of the supporting substrate. By doing so, a device contact hole is formed at a position corresponding to each gate electrode, a drain layer, and a source layer of each device region, and a contact hole is also formed at a position corresponding to the substrate contact hole. And a step of forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, and then performing a photoetching process to form an independent metal electrode for each contact hole, in which case, A metal electrode forming step of forming a pad portion extending on the insulating film on the metal electrode formed in the substrate contact hole; And a method for manufacturing a semiconductor device having the same. 11. The method of manufacturing a semiconductor device according to claim 10, wherein a step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and each of the low-concentration P-type or N-type regions. Reverse the order of the step of selectively implanting an impurity atom having a conductivity type opposite to that of the type region to form an offset region and performing a heat treatment to diffuse the impurity atom of the offset region. Then, a step of selectively ion-implanting an impurity atom having a conductivity type opposite to that of the low-concentration P-type or N-type region to form an offset region and heat treatment are performed, so that the impurity atom of the offset region is And a step of forming a gate electrode on each of the low-concentration P-type or N-type regions with a gate oxide film interposed therebetween after the step of diffusing. 12. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer. Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to remove impurity atoms in each of the low-concentration P-type or N-type regions. And a step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and by selectively etching the buried oxide film and the field oxide film, A step of forming a substrate contact hole on the supporting substrate; and a step of selectively ion-implanting an impurity atom having a conductivity type opposite to that of the gate electrode in each of the low-concentration P-type or N-type regions into a drain. A layer and a source layer, and forming a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate into a portion of the supporting substrate exposed in the substrate contact hole. After forming an insulating film on the entire surface of the supporting substrate, a photo-etching process is performed so that the gate electrode, the drain layer, and the source layer in the device regions are individually addressed. And forming a contact hole for each element on the substrate, and also forming a contact hole at a position corresponding to the substrate contact hole, and after forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes. A metal electrode is formed by performing a photoetching process for each contact hole, and a metal electrode formed in the substrate contact hole is also formed with a pad portion extending over the insulating film. A method of manufacturing a semiconductor device, comprising: a forming step. 13. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer. Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to remove impurity atoms in each of the low-concentration P-type or N-type regions. A step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film, and a conductive type on both sides of the gate electrode of each of the low-concentration P-type or N-type regions. Selectively implanting impurity atoms opposite to the region to form a low concentration drain layer, forming sidewalls of a silicon oxide film on both side surfaces of each gate electrode, Forming a substrate contact hole on the supporting substrate by selectively etching the film and the field oxide film, and outside the sidewalls on both sides of the gate electrode in each of the low concentration P-type or N-type regions. In the region, the impurity layer having the same conductivity type as that of the low-concentration drain layer is selectively ion-implanted to form a drain layer and a source layer, and at that time, the substrate contact of the supporting substrate is formed. A step of ion-implanting a high-concentration diffusion layer by ion-implanting impurity atoms of the same conductivity type as that of the supporting substrate into a portion exposed in the contact hole, and a photoetching treatment after forming an insulating film on the entire surface of the supporting substrate. By doing so, the device contact holes are formed at the positions corresponding to the respective gate electrodes, drain layers, and source layers of the device regions, and contact holes are also formed at the positions corresponding to the substrate contact holes. Forming step, and after forming a metal electrode layer on the entire surface of the insulating film and in all the contact holes, a photoetching process is performed to form an independent metal electrode for each contact hole. A metal electrode type in which a pad portion extending on the insulating film is also formed in the metal electrode formed in the substrate contact hole. The method of manufacturing a semiconductor device having a step. 14. An SOI substrate in which a surface silicon layer is formed on a silicon supporting substrate via an embedded oxide film is prepared, and a pad oxide film and a silicon nitride film are formed on the surface of the surface silicon layer. Patterning so that the silicon nitride film and the pad oxide film remain on the device region by performing a photoetching process; forming a field oxide film on the device isolation region of the SOI substrate; A step of forming a plurality of independent device regions, and a step of removing the silicon nitride film and the pad oxide film, and selectively adding impurity atoms of P type or N type conductivity to the plurality of device regions. Ion implantation is performed to form a plurality of low-concentration P-type or N-type regions, and heat treatment is performed to remove impurity atoms in each of the low-concentration P-type or N-type regions. A step of causing dispersion, each lightly doped P
Forming a gate electrode on the p-type or n-type region via a gate oxide film, and selectively ion-implanting each of the low-concentration p-type or n-type regions with impurity atoms having a conductivity type opposite to that of the region. A step of forming an offset region, a step of diffusing the impurity atoms of the offset region by performing a heat treatment, and a step of selectively etching the buried oxide film and the field oxide film to form a film on the support substrate. A step of forming a substrate contact hole, and selectively ion-implanting impurity atoms having the same conductivity type as the offset region into regions of the low-concentration P-type or N-type region on both sides of the gate electrode except the offset region. To form a drain layer and a source layer, and at that time, an impurity source of the same conductivity type as that of the supporting substrate is also formed in a portion exposed in the substrate contact hole of the supporting substrate. And a step of forming a high-concentration diffusion layer by ion-implanting a child, after forming an insulating film on the entire surface of the support substrate, by performing a photoetching process, each gate electrode of each element region, the drain layer, And a step of forming element contact holes at positions corresponding individually to the source layer, and forming contact holes at positions corresponding to the substrate contact holes, and the entire surface of the insulating film and all the contact holes. After forming a metal electrode layer inside, a photoetching process is performed to form an independent metal electrode for each contact hole. At that time, the metal electrode formed in the substrate contact hole is formed on the insulating film. And a metal electrode forming step of forming a pad portion extending to the semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 14, wherein a step of forming a gate electrode on each of the low-concentration P-type or N-type regions via a gate oxide film, and each of the low-concentration P-type or N-type regions. Reverse the order of the step of selectively implanting an impurity atom having a conductivity type opposite to that of the type region to form an offset region and performing a heat treatment to diffuse the impurity atom of the offset region. Then, a step of selectively ion-implanting an impurity atom having a conductivity type opposite to that of the low-concentration P-type or N-type region to form an offset region and heat treatment are performed, so that the impurity atom of the offset region is And a step of forming a gate electrode on each of the low-concentration P-type or N-type regions through a gate oxide film after the step of diffusing the semiconductor. 16. The method of manufacturing a semiconductor device according to claim 8, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 17. The method of manufacturing a semiconductor device according to claim 9, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 18. The method of manufacturing a semiconductor device according to claim 10, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 19. The method of manufacturing a semiconductor device according to claim 11, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 20. The method of manufacturing a semiconductor device according to claim 12, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 21. The method of manufacturing a semiconductor device according to claim 13, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 22. The method of manufacturing a semiconductor device according to claim 14, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 23. The method of manufacturing a semiconductor device according to claim 15, wherein after the metal electrode forming step, a protective film is formed on the entire surface of the insulating film and each of the metal electrodes, and the pad portion of the protective film is formed. A method of manufacturing a semiconductor device, comprising: forming an opening at a position corresponding to the step; and forming a connection electrode connected to the pad section through the opening from above the protective film. 24. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 25. The method of manufacturing a semiconductor device according to claim 9, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 26. The method of manufacturing a semiconductor device according to claim 10, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 27. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 28. The method of manufacturing a semiconductor device according to claim 12, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 29. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 30. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device. 31. The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming a contact hole in the insulating film, a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole. Of manufacturing a semiconductor device.