JP2003282734A - Semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A semiconductor memory device having a trench capacitor for reducing the resistance of a buried strap portion and a method of manufacturing the same are provided. SOLUTION: A trench capacitor 3, 4, 5, 6, 7 provided in a trench 2 in a semiconductor substrate 1, and a data transfer transistor 11, 1 provided on the semiconductor substrate.
A source connection electrode 8 is provided for connection between 2, 3, 14, and 16, and data of the trench capacitor is transmitted through a data transfer transistor. Since the connection surface of the source connection electrode 8 with the source 13 of the data transfer transistor is provided with irregularities, the semiconductor memory device has an enlarged contact area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a fine semiconductor memory device having a trench type capacitor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been highly integrated, and in particular, DRAMs are required to have a high integration density at a gigabit level. With the increase in the integration density of such semiconductor integrated circuits, miniaturization of the trench capacitor and the element isolation region around it has become an essential technology.

The structure of a conventional semiconductor memory device will be described with reference to FIGS. A cross-sectional structure of a conventional semiconductor memory device will be described with reference to FIG. 4, which is a cross-sectional view showing a schematic structure on the “CD” line in FIG. In the semiconductor substrate 1,
The trench groove 2 is formed. An N-type diffusion layer 3 for a capacitor electrode is provided in the semiconductor substrate 1 around the lower part of the trench groove 2. A silicon oxide film is provided in contact with the N-type diffusion layer 3 for the capacitor electrode on the side wall in the lower portion of the trench groove 2. Further, a silicon nitride film is formed inside the silicon oxide film and also functions as the capacitor insulating film 4.

Further, a lower capacitor electrode 5 filled with amorphous silicon is formed in the capacitor insulating film 4 in the lower portion of the trench groove 2. An upper capacitor sidewall insulating film 6 is provided on the sidewall of the trench groove 2 on the lower capacitor electrode 5.

Further, the trench groove 2 in the upper capacitor side wall insulating film 6 is filled with amorphous silicon to provide an upper capacitor electrode 7, which is connected to the lower capacitor electrode 5. A source connection electrode 8 made of polysilicon is formed on the upper capacitor electrode 7. The source connection electrode 8 is formed up to the upper capacitor sidewall insulating film 6. Thus, a trench capacitor including the N-type diffusion layer 3 for capacitor electrode, the capacitor insulating film 4, the lower capacitor electrode 5, the upper capacitor sidewall insulating film 6, the upper capacitor electrode 7, the source connecting electrode 8 and the upper insulating film 9 is formed. There is.

An upper insulating film 9 is formed on the source connecting electrode 8.
Is formed, and the gate insulating film 1 is formed on the upper insulating film 9.
For example, a polycrystalline silicon gate electrode layer 11 and a WSi gate electrode layer 12 are formed via the 0. The polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 1
A source 13 connected to the source connection electrode 8 is formed near the upper surface of the semiconductor substrate 1 below the semiconductor substrate 1. The semiconductor substrate 1 below the polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 12 is formed in the region where the source 13 is formed.
The drain 14 is formed near the upper surface of the. The source 13 and the drain 14 are provided in the active region 15 near the upper surface of the semiconductor substrate 1. A gate sidewall insulating film 16 is provided on the side surfaces of the polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 12.

Further, on the active region 15, a plurality of polycrystalline silicon gate electrode layers 11, WSi gate electrode layers 12 and gate side wall insulating films 16 are continuously provided. The trench capacitors are formed in the semiconductor substrate 1 at regular intervals, and in the active region 15 between a pair of adjacent trench capacitors,
An element isolation region 18 is provided. A polycrystalline silicon gate electrode layer 11 and a WSi layer are formed on each trench capacitor.
The gate electrode layer 12 and the gate sidewall insulating film 16 are provided one by one. An element isolation region 18 is formed in the active region 15 between a pair of trench capacitors formed adjacent to each other. 2 further apart
Two data transfer transistors composed of a polycrystalline silicon gate electrode layer 11, a WSi gate electrode layer 12, a gate sidewall insulating film 16, a source 13 and a drain 14 are formed between two trench capacitors.

As can be seen from the top view of FIG. 22, in the conventional technique, the active region 15 is provided between the trench grooves 2 which are spaced apart and surrounded by the element isolation region 18. The active region 15 has a rectangular shape with a semi-elliptical end portion, and an element isolation region 18 is formed in the trench groove 2 except for the active region 15. Since the trench groove 2 of the trench type capacitor is formed in an elliptical shape close to a rectangle, the structure of the junction surface 50 with the source region seen from above is a part of the ellipse as shown in the top view.
A substantially straight line or a smooth arc close to a straight line is drawn, and the bonding resistance depends on the length of this portion and the area multiplied by the depth direction. Here, in FIG. 22, the data transfer transistor is not shown.

Next, a conventional method for manufacturing a semiconductor memory device will be described with reference to FIGS. 4, 6, 22, 23 and 24. First, as shown in a sectional view in FIG. 6A, a rectangular glass mask pattern is transferred onto a semiconductor substrate by lithography in a memory cell area of the semiconductor substrate, and a trench type capacitor opening is formed by dry etching. A capacitor portion made of, for example, an ON film is formed on the lower sidewall of the trench, and an inner portion of the opening is formed as
^An electrode is formed by filling with ⁺ -added amorphous silicon, and the capacitor part and the source part of the active region near the semiconductor substrate surface are separated from the semiconductor substrate surface by a silicon oxide film, for example. An insulating film is formed, and the inside thereof is further filled with another amorphous silicon to which As ⁺ is added. When forming this portion, etching and thermal diffusion of impurities are appropriately performed. The shape of the top surface in this state is as shown in FIG.
The trench groove 2 is formed therein, the upper capacitor side wall insulating film 6 is formed on the side surface thereof, and the upper capacitor electrode is formed therein.

Next, as shown in the sectional view of FIG. 23A, for example, after stacking polycrystalline silicon, the polycrystalline silicon is etched to the surface position of the semiconductor substrate by chemical dry etching or the like, and source connection is performed. The electrode 8 is formed. A top view of this trench groove is as shown in FIG. 23B, which is a top view in the previous step.
Same as (B). In addition, "K" in FIG.
The cross-section along the line -L "is the cross-sectional view of FIG.

Next, as shown in FIG. 24, a shallow groove (element isolation groove 35) for element isolation is processed in the semiconductor substrate 1 by using the lithography technique, and the active region 1 is formed.
5 is formed.

Thereafter, as shown in FIGS. 4 and 22, after an insulator such as an oxide film is laminated in the element isolation trench 35,
The upper surface of the semiconductor substrate 1 is etched to form an element isolation region 18, and the gate of the data transfer transistor is processed and the source 13 and drain 14 of the transistor are processed.
Are formed by impurity implantation and thermal diffusion. Thus
The upper electrode 7 of the trench type capacitor and the source 13 of the data transfer transistor are connected. At this connection surface 50, a junction resistance will be generated.

[0013]

The conventional semiconductor memory device and the manufacturing method thereof as described above have the following problems. As miniaturization progresses, both the diameter of the trench capacitor and the size of the source region of the transistor decrease, so the junction with the source region has a nearly straight line or a smooth arc structure close to a straight line. Becomes shorter and, as a result, the junction resistance also rises. The time constant is determined by the product of the capacitor capacitance C of the memory cell and the junction resistance R. When the junction resistance increases, the time constant increases and the write / read characteristics of the memory cell deteriorate.
Further, if the active region is formed deviating from the trench capacitor at the time of lithography for forming the active region by element isolation, the junction area becomes small and the junction resistance further increases. That is, the active region is displaced in the longitudinal direction with respect to the trench region, so that the overlapping portion of the connection region between the active region and the trench region becomes small and the junction resistance increases.

An object of the present invention is to solve the above problems of the prior art. In particular, it is an object of the present invention to provide a semiconductor memory device having a trench capacitor that reduces the resistance of a buried strap portion and a method for manufacturing the same.

[0015]

To achieve the above object, the present invention is characterized by a semiconductor substrate, an element isolation region provided in the upper surface of the semiconductor substrate, and an element isolation in the semiconductor substrate. A source provided in the upper surface other than the area,
A data transfer transistor having a drain, a gate electrode provided on the semiconductor substrate, a trench groove provided in the upper surface of the semiconductor substrate other than the element isolation region, and a semiconductor substrate around the trench groove. A capacitor electrode diffusion layer provided therein, a capacitor insulating film provided on the lower side surface of the trench groove in contact with the capacitor electrode diffusion layer, and a capacitor insulating film provided below the trench groove in the capacitor insulating film. A lower electrode, an upper capacitor sidewall insulating film provided on an upper side surface in the trench groove, an upper capacitor electrode provided in the trench groove in the upper capacitor sidewall insulating film on the lower electrode, and an upper portion thereof. Provided on a capacitor electrode and the upper capacitor sidewall insulating film, and connected to the source of the data transfer transistor, There is a concave portion and a convex portion on the connection surface with the source, and the convex portion protrudes from the upper capacitor sidewall insulating film in the outer side direction of the trench groove, and has a thickness on the upper capacitor sidewall insulating film more than other portions. Also has a large source connection electrode.

Another feature of the present invention is that a trench type capacitor provided in a semiconductor substrate for holding charges, a data transfer transistor for supplying a charge holding voltage to the trench type capacitor, and this data transfer transistor. And a trench strap connected between the source and the trench type capacitor, and a buried strap provided with a projecting portion projecting toward the source side and a non-projecting portion not projecting.

Another feature of the present invention is that a trench groove is formed in a semiconductor substrate, a capacitor insulating film is formed on a lower side surface in the trench groove, and a trench lower portion is formed in the trench groove inside the capacitor insulating film. Forming an electrode, forming a trench upper capacitor sidewall insulating film on an upper side surface in the trench groove, and forming an upper capacitor electrode in the trench groove inside the trench upper capacitor sidewall insulating film; Forming a diffusion layer for a capacitor electrode around the capacitor insulating film, and forming a photoresist having an opening extending over the semiconductor substrate outside the trench groove from above the upper capacitor electrode above the semiconductor substrate, Using the photoresist, the opening of the photoresist is etched and the semiconductor layer is removed. Forming a projecting opening in the substrate, the upper capacitor electrode, and the trench upper capacitor sidewall insulating film; removing the photoresist; and forming a conductive layer on the projecting opening and the upper capacitor electrode. A step of forming a source connection electrode; a step of forming a device isolation region forming groove by etching the vicinity of the surface of the semiconductor substrate other than the device formation planned region; and a step of filling an insulating film in the device isolation region forming groove. Forming a gate electrode on the semiconductor substrate on the device formation planned region, forming a source and a drain in the semiconductor substrate, connecting the source to the source connection electrode, and forming a data transfer transistor. And a method for manufacturing a semiconductor memory device.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) The structure of a semiconductor memory device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a memory cell area showing the characteristics of the semiconductor memory device according to the present embodiment. For example, in a semiconductor substrate 1 made of silicon, trench grooves (holes for trench type capacitors, holes for trench type capacitors) are formed. 2) is formed. An N-type diffusion layer 3 for a capacitor electrode is provided in the semiconductor substrate 1 around the lower part of the trench groove 2. A silicon nitride film, for example, is provided on the side wall in the lower portion of the trench groove 2 so as to be in contact with the N-type diffusion layer 3 for a capacitor electrode. Further, a silicon oxide film is formed inside the silicon nitride film and also functions as a capacitor insulating film 4.

Further, a lower capacitor electrode 5 filled with, for example, As ⁺ -doped amorphous silicon is formed in the capacitor insulating film 4 in the lower portion of the trench groove 2. On the side wall of the trench groove 2 on the lower capacitor electrode 5,
An upper capacitor sidewall insulating film 6 is provided.

Further, the trench groove 2 in the upper capacitor side wall insulating film 6 is filled with amorphous silicon to which As ⁺ is added, and the upper capacitor electrode 7 is provided.
It is connected to the lower capacitor electrode 5. A source connection electrode (embedded strap) 8 made of polysilicon is formed on the upper capacitor electrode 7. The source connection electrode 8 is formed so as to protrude from the upper capacitor side wall insulating film 6 to a part of the upper portion of the semiconductor substrate 1 corresponding to the outside of the trench groove 2. Here, the source connection electrode 8 is formed to the deepest position on the upper capacitor side wall insulating film 6 and is formed to have a slightly thin thickness in the periphery thereof. Further, the source connection electrode 8 on the upper capacitor electrode, which is separated from the peripheral portion of the upper capacitor side wall insulating film 6, is
The thickness is further reduced. Thus, a trench capacitor including the N-type diffusion layer 3 for capacitor electrode, the capacitor insulating film 4, the lower capacitor electrode 5, the upper capacitor sidewall insulating film 6, the upper capacitor electrode 7, the source connecting electrode 8 and the upper insulating film 9 is formed. There is.

An upper insulating film 9 is formed on the source connecting electrode 8.
Is formed, and the gate insulating film 1 is formed on the upper insulating film 9.
For example, a polycrystalline silicon gate electrode layer 11 and a WSi gate electrode layer 12 are formed via the 0. The polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 1
A source 13 connected to the source connection electrode 8 is formed near the upper surface of the semiconductor substrate 1 below the semiconductor substrate 1. The semiconductor substrate 1 below the polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 12 is formed in the region where the source 13 is formed.
The drain 14 is formed near the upper surface of the. The source 13 and the drain 14 are provided in the active region 15 near the upper surface of the semiconductor substrate 1. A gate sidewall insulating film 16 made of SiN or the like is provided on the side surfaces of the polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 12.

Further, on the active region 15, a plurality of polycrystalline silicon gate electrode layers 11, WSi gate electrode layers 12 and a gate sidewall insulating film 16 are continuously provided. The trench capacitors are formed in the semiconductor substrate 1 at regular intervals, and in the active region 15 between a pair of adjacent trench capacitors,
An element isolation region 18 is provided. A polycrystalline silicon gate electrode layer 11 and a WSi layer are formed on each trench capacitor.
The gate electrode layer 12 and the gate sidewall insulating film 16 are provided one by one. An element isolation region 18 is formed in the active region 15 between a pair of trench capacitors formed adjacent to each other. 2 further apart
Two data transfer transistors composed of a polycrystalline silicon gate electrode layer 11, a WSi gate electrode layer 12, a gate sidewall insulating film 16, a source 13 and a drain 14 are formed between two trench capacitors. The polycrystalline silicon gate electrode layer 11 and the WSi gate electrode layer 12 function as word lines.

One drain 14 of the two data transfer transistors provided between the two trench capacitors spaced apart is provided in common. In addition, a pair of adjacent trench capacitors is a capacitor electrode N
The mold diffusion layers 3 are connected to each other. Further, data transfer transistors of other trench capacitors not shown in FIG. 1 are provided on the respective trench capacitors.

Here, FIG. 1 is a top view of FIG.
2 is a cross-sectional view taken along the line -B ", and the data transfer transistor is not shown in FIG. 2. In the top view shown in FIG. An active region 15 is provided surrounded by an isolation region 18. The active region 15 has a rectangular shape with a semi-elliptical end portion, and the element isolation region 18 other than the active region 15 is also formed in the trench groove 2. The width of the active region 15 is, for example, about 0.175.
It can be μm. The length of the protrusion 20 is smaller than the width of the active region 15. As shown in the top view, another active region is formed in rows above and below the same line in one active region, being shifted in the longitudinal direction.

Here, one trench groove 2 facing the active region 15 is provided with three projecting portions 20. Except for the portion facing the active region 15, the shape is oval, that is, the combined shape of the curved portion and the straight portion.

FIG. 3 is a top view showing the data transfer gate omitted in FIG. As shown in FIG.
A plurality of WSi gate electrode layers 12, which is the uppermost layer of the data transfer transistor, are linearly formed in parallel with each other at regular intervals.

Next, FIG. 4 shows a cross section taken along the line "CD" in FIG. Here, the point different from the cross section shown in FIG. 1 is that the source connection electrode 8 of the trench capacitor and the connection surface of the upper insulating film 9 with the source 13 are not uneven. That is, the source connection electrode 8 and the upper insulating film 9 are in contact with the source 13 on the same side surface as the lower capacitor side wall insulating film 6 side surface.

Next, an enlarged view of the M portion in FIG. 1 is shown in FIG.
Shown in. Here, the source connection electrode 8 and the protruding portion 20 of the upper insulating film 9 protrude toward the source 13 side with respect to the upper capacitor sidewall insulating film 6, and the depth thereof is deeper than the source connecting electrode 8 other than the protruding portion 20. It has a side protrusion 21. Further, the protruding portion 20 of the source connecting electrode 8 has a depth on the trench groove 2 side other than the protruding portion 20.
It has a trench-side protrusion 22 that is deeper than the above. Also,
The projecting portion 20 of the source connection electrode 8 is formed on the upper capacitor side wall insulating film 6 so as to have the deepest depth than the other regions. As described above, in the cross section of FIG. 1, the source connection electrode 8 which is a junction with the active region of the trench type capacitor is provided with uneven steps at the bottom in the depth direction.

The data transfer transistor adjacent to the trench capacitor inputs / outputs the stored contents of the trench capacitor and transmits the potential to the word line. The gate electrode of the data transfer transistor in the active region provided in the uppermost row shown in FIG. 2 corresponds to the word line formed on the trench capacitor shown in FIG. A bit line contact (not shown) is connected to the shared drain between the gates of the data transfer transistors adjacent to each other, and a bit line (not shown) provided on the word line is connected.
It is connected to the. Further, an interlayer insulating film (not shown) is formed on the semiconductor substrate to cover the gate electrode, the bit line and the like.

Here, since the source connection electrode 8 on the upper portion of the trench capacitor, which functions as an embedded strap for connecting the trench capacitor and the source of the data transfer transistor, can have its resistance value lowered by setting its impurity concentration high, When combined with the structure of this embodiment, the contact resistance can be further reduced.

As described above, according to the semiconductor memory device of the present embodiment, it is possible to reduce the resistance of the embedded strap portion formed between the trench type capacitor and the data transfer transistor.

That is, in the case of the structure shown in FIG. 2 which is the present embodiment, assuming that the width of the active region 15 is X0, the diameter of the embedded strap portion is ⅓ (= 3).
/ 10 × X0) are provided, and the protrusions are embedded in each other, and the intervals are 1/5 (= 1) of the strap portion.
/ 5 × X0) each, the total length X of the buried strap portion in contact with the active region and the trench capacitor is represented by the following equation, where π = 3.14. In the formula below, the first term indicates that there are two intervals between the three holes, and the second term indicates that there is one semicircle,
The third term indicates that there are two quarter circles.

[0033]

[Equation 1] As shown in this formula, the length is 30% more than X0 corresponding to the length when the embedded strap is formed linearly.
The joint length can be increased in the vicinity.

Further, according to the structure of the present embodiment, there is no effect even if the contact distance is shortened in the range of up to 1.3 times as long as the contact distance is reduced.

Further, according to the structure of the present embodiment, the contact distance is 1.3 times, so that the contact resistance is 1 / 1.3.
That is, it can be reduced to about 74.5%. In the present embodiment, the junction resistance between the trench capacitor, which is a memory cell constituent element, and the source region of the data transfer transistor is reduced.

Next, a method of manufacturing the semiconductor memory device according to this embodiment will be described with reference to FIGS. First, as shown in FIG. 6A, a glass mask (not shown) is placed in a rectangular island shape on the semiconductor substrate 1 corresponding to the active region, and the trench capacitor formation planned region of the semiconductor substrate outside the mask is placed. A plurality of trench grooves 2 are formed in. The trench groove 2 maintains a shape close to an ellipse in which four corners are rounded when a quadrangle of a glass mask is transferred by a lithography technique when viewed from the top surface.

Next, the side surface under the trench groove 2 is oxidized to form a silicon oxide film on the surface. At this time, a silicon nitride film is formed on the exposed surface of the semiconductor substrate. Next, oxidation is performed to form a silicon oxide film. Furthermore, on the silicon oxide film under the trench. Thus, the capacitor insulating film 4 is formed.

Next, an amorphous silicon layer is buried inside the trench groove 2 and left only in the lower portion of the trench groove 2, so that the amorphous silicon layer is formed in the upper portion of the trench groove 2 until the semiconductor substrate 1 is exposed. Remove and remove the lower capacitor electrode 5
To form.

Next, a silicon oxide film is deposited on the upper portion of the trench groove 2 by the CVD method, and the silicon oxide film in the upper portion of the trench groove 2 is removed so that only the upper side surface of the trench groove 2 remains. The capacitor sidewall insulating film 6 is formed.

Next, amorphous silicon is deposited on the trench groove 2 to form the upper capacitor electrode 7.

A top view in this state corresponds to FIG. 6B, the upper capacitor side wall insulating film 6 is formed on the side surface inside each trench groove 2, and the inner surface of the upper capacitor side wall insulating film 6 is formed. The upper capacitor electrode 7 is formed.
The cross section taken along the line "EF" in FIG. 6B is shown in FIG.
It corresponds to (A).

Next, a glass mask having a hole pattern opening 30 for forming three openings on the side surface of each trench groove 2 is prepared. Since the glass mask is transferred every several chips, a pattern for several chips is formed.

Next, as shown in the cross section of FIG. 7A, a rectangular glass mask pattern is transferred as a photoresist 31 onto the semiconductor substrate by lithography in the memory cell area of the semiconductor substrate 1. As described above, the hole pattern opening 30 is provided in the photoresist 31. In the hole pattern opening 30, the upper surface of the end of the trench upper capacitor electrode 7, the upper surface of the upper capacitor insulating film 6, and the upper surface of the semiconductor substrate 1 in contact with the trench groove 2 are exposed. . The upper surface in the state shown in FIG. 7 (A) is shown in FIG. 7 (B). Figure 7
In (B), three hole pattern openings 30 are provided at positions corresponding to the ends of each trench groove 2. The cross section taken along the line "GH" in FIG. 7B is shown in FIG.
It corresponds to (A).

Next, as shown in the cross section of FIG. 8, using a photoresist 31 by, for example, dry etching,
The protrusion opening 33 is formed on the end of the trench groove 2.

Next, as shown in the cross section of FIG. 9A, the photoresist 31 is removed by ashing (ashing treatment). Next, the source connection electrode 8 is formed by depositing, for example, As ⁺ -doped amorphous silicon in the protrusion opening 33 and on the trench upper capacitor electrode 7. When forming this portion, etching and thermal diffusion of impurities are appropriately performed. The state of this cross section viewed from above is shown in FIG. As shown in FIG. 9B, three protruding portions 20 are provided on each of the facing surfaces of the trench grooves 2 that are separated from each other. Further, the surfaces of the trench grooves 2 facing each other in a pair adjacent to each other are linear. 9A is a cross-sectional view of the cross section taken along the line "I-J" in FIG. 9B.

Next, element isolation regions (Shallow Trench Isolation, hereinafter referred to as STI) are formed by lithography.
A photoresist (not shown) for forming the STI is formed in the planned formation region.

Next, as shown in FIG. 10, using this photoresist as a mask, the upper insulating film 9, the source connection electrode 8 and the upper capacitor electrode 7 in the STI formation planned region are formed.
Then, the upper capacitor sidewall insulating film 6 is removed by etching to form an island pattern of the element isolation trench 35 for STI formation.

Next, as shown in FIG. 1, an insulating film is buried in the element isolation trench 35 for forming each STI to form an element isolation region 18, and adjacent trench capacitors are isolated near the upper surface. At this time, the upper insulating film 9 is formed on the source connection electrode 8 which is the exposed surface of the trench groove 2.

Next, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are deposited on the active region 15 surrounded by the element isolation region 18 and on the trench capacitor, and processed into a gate shape. To do. Next, a gate side wall insulating film 16 is formed around the gate, and the gate side wall insulating film 16, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are used as masks in the active region 15. The source 13 and the drain 14 are formed. Thus, the semiconductor memory device of this embodiment is obtained.

Further, according to the manufacturing method of the present embodiment,
Even if the trench capacitor is misaligned when the element isolation trench is transferred, it is possible to suppress a decrease in the contact portion and suppress an increase in resistance as compared with the case where there is no unevenness.

Furthermore, according to the manufacturing method of the present embodiment, since the contact portion between the trench capacitor and the data transfer transistor becomes long, even if the displacement between the trench capacitor and the active region is increased, for example, 1.3. One-third
Even if the contact distance is reduced in the range up to twice, it has no effect.

(Second Embodiment) A semiconductor memory device according to the present embodiment will be described with reference to FIGS. 1, 3, 4, and 11. FIG. 11 is a top view showing the semiconductor memory device of the present embodiment with the data transfer transistor omitted.
In, the active area for one row is shown. Here, the cross section on the "AB" line without omitting the data transfer transistor is as shown in FIG. 1, and the cross section on the "CD" line without omitting the data transfer transistor is shown. The cross section is as shown in FIG. Further, the top view including the data transfer transistor is as shown in FIG.

In FIG. 11, an active region 15 is provided between the trench grooves 2 arranged apart from each other and surrounded by an element isolation region 18. The active area 15 is
The end portion is a rectangle with a semi-elliptical shape, and the element isolation region 18 is formed in the trench groove 2 except for the active region 15.
Are formed. The width of the active region 15 can be set to about 0.175 μm, for example. The length of the protrusion 20 is smaller than the width of the active region 15. As shown in the top view, another active region is formed in rows above and below the same line in one active region, being shifted in the longitudinal direction.

Here, the trench groove 2 facing the active region 15 is provided with two projecting portions 20. Except for the portion facing the active region 15, the shape is oval, that is, the combined shape of the curved portion and the straight portion.

The number and size of the protrusions provided for each trench capacitor are not limited to those shown in FIG. 11, and protrusions having other numbers and sizes may be used. . As described above, the structure other than the structure shown in FIG. 11 is the same as the structure of the first embodiment, and the description thereof will be omitted. In the semiconductor memory device of this embodiment, the same effect as that of the first embodiment can be obtained.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIGS. 6 (A), 6 (B) and 7
This will be described with reference to (A), FIG. 8, FIG. 9 (A), FIG. 9 (B), and FIGS. First, FIG. 6A and FIG.
The structure shown in (B) is formed similarly to the first embodiment.

Next, a glass mask having a hole pattern opening 30 for forming two openings on the side surface of each trench groove 2 is prepared. Since the glass mask is transferred every several chips, a pattern for several chips is formed.

Next, as shown in the cross section of FIG. 7A, a rectangular glass mask pattern is transferred as a photoresist 31 onto the semiconductor substrate by lithography in the memory cell area of the semiconductor substrate 1. As described above, the hole pattern opening 30 is provided in the photoresist 31. In the hole pattern opening 30, the upper surface of the end of the trench upper capacitor electrode 7, the upper surface of the upper capacitor insulating film 6, and the upper surface of the semiconductor substrate 1 in contact with the trench groove 2 are exposed. . The upper surface in the state shown in FIG. 7A is shown in FIG. In FIG. 12, two hole pattern openings 30 are provided at positions corresponding to the ends of each trench groove 2. The cross section taken along the line “GH” in FIG. 12 corresponds to FIG.

Next, as shown in the cross section of FIG. 8, using a photoresist 31 by, for example, dry etching,
The protrusion opening 33 is formed on the end of the trench groove 2.

Next, as shown in the cross section of FIG. 9A, the photoresist 5 is removed by ashing (ashing treatment). Next, the source connection electrode 8 is formed by depositing, for example, As ⁺ -doped amorphous silicon in the protrusion opening 33 and on the trench upper capacitor electrode 7. When forming this portion, etching and thermal diffusion of impurities are appropriately performed.
FIG. 13 shows a state in which this cross section is viewed from above. FIG.
As shown in FIG. 2, two protruding portions 20 are provided on each of the facing surfaces of the separated trench grooves 2. Further, the surfaces of the trench grooves 2 facing each other in a pair adjacent to each other are linear. The cross section taken along the line "I-J" in FIG. 13 is a cross sectional view shown in FIG.

Next, a photoresist (not shown) for STI formation is formed in the element isolation region formation planned region by lithography.

Next, as shown in FIG. 10, using this photoresist as a mask, the upper insulating film 9, the source connection electrode 8, and the upper capacitor electrode 7 in the STI formation planned region are formed.
Then, the upper capacitor sidewall insulating film 6 is removed by etching to form an island pattern of the element isolation trench 35 for STI formation.

Next, as shown in FIG. 1, an insulating film is buried in the element isolation trench 35 for forming each STI to form an element isolation region 18, and adjacent trench capacitors are isolated near the upper surface. . At this time, the upper insulating film 9 is formed on the source connection electrode 8 which is the exposed surface of the trench groove 2.

Next, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are deposited on the active region 15 surrounded by the element isolation region 18 and on the trench capacitor, and processed into a gate shape. To do. Next, a gate sidewall insulating film 16 is formed around the gate, and the gate sidewall insulating film, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are used as a mask to form a source in the active region 15. 13 and the drain 14 are formed. Thus, the semiconductor memory device of this embodiment is obtained.

The method of manufacturing the semiconductor memory device of the present embodiment can achieve the same effects as those of the method of manufacturing the semiconductor memory device of the first embodiment. Further, in the semiconductor memory device of this embodiment, the number of openings is two, so that the distance between openings can be made larger than that in the first embodiment, and the reduction in yield due to the short distance between openings can be avoided.

(Third Embodiment) This embodiment is a semiconductor memory device having a structure similar to that of the first embodiment. A method of manufacturing the semiconductor memory device having such a structure will be described with reference to FIGS. 6 to 9 and 14 to 16. First, the structure shown in FIGS. 6A and 6B is formed similarly to the first embodiment.

Next, a glass mask having a hole pattern opening 30 having two openings on each side surface of each trench groove 2 is prepared. At this time, the distance between the two openings provided as the hole pattern openings 30 is formed smaller than the distance between the two openings provided as the hole pattern openings 30 in the second embodiment. Since the glass mask is transferred every several chips, a pattern for several chips is formed.

Next, as shown in the cross section of FIG. 7A, a rectangular glass mask pattern is transferred as a photoresist 31 onto the semiconductor substrate by lithography in the memory cell area of the semiconductor substrate 1. As described above, the hole pattern opening 30 is provided in the photoresist 31. In the hole pattern opening 30, the upper surface of the end of the trench upper capacitor electrode 7, the upper surface of the upper capacitor insulating film 6, and the upper surface of the semiconductor substrate 1 in contact with the trench groove 2 are exposed. . The upper surface in the state shown in FIG. 7A is shown in FIG. In FIG. 14, two hole pattern openings 30 are provided at positions corresponding to the ends of each trench groove 2. The cross section taken along the line “GH” in FIG. 14 corresponds to FIG.

Next, as shown in the cross section of FIG. 8, lithography is performed using a phase shift mask to form a photoresist 31, and etching is performed to form a protrusion opening 33.
Are formed on the ends of the trench groove 2. At this time, due to the sidelob effect, three openings and three projection openings 33 are provided for each trench groove 2 as shown in the upper surface of FIG. 7B. Here, the sidelob effect is that when the phase shift mask is used and the distance between the openings provided in the mask is equal to or less than a certain value, the peaks of the light intensity of the antiphase corresponding to the respective openings are adjacent to each other. This is a phenomenon in which the peaks of the light intensities at the opposite phases overlap each other and become extremely large. The opening obtained by the side lobe effect is provided with the third opening while its diameter is slightly smaller than the normal opening corresponding to the opening provided in the mask. Here, FIG. 15A is a top view showing a state of an opening in a resist when etching is performed using a normal mask.
Here, the two openings are formed at a distance Y. The light intensity according to the position of this opening is shown in FIG. Peaks P having the same phase occur at the positions of the openings 30. Two opposite-phase peaks PR1 are generated at the left and right positions of these two peaks P, respectively. Since the magnitude of the peak PR1 having the opposite phase is smaller than that of the peak P, the damage to the resist is small.

On the other hand, FIG. 16A shows a top view showing the state of openings in the photoresist when etching is performed using the phase shift mask. Here, the two openings are formed at a distance Z. This distance Z is smaller than the distance Y. Therefore, 2
Another opening is formed between one opening. The light intensity according to the position of this opening is shown in FIG. Peaks P having the same phase occur at the positions of the openings 30 at both ends. Between these two peaks P, there is a peak PR2 having the same intensity and opposite phase. This anti-phase peak PR2 causes an opening which does not exist in the original glass mask between two adjacent openings. One opposite phase peak PR1 is generated at a position opposite to the opposite side of the opposite phase PR2 forming side of the peak P. The magnitude of the intensity of the reverse phase peak PR1 is the peak P or the reverse phase peak PR.
Since it is smaller than 2, the damage to the resist is small and no opening occurs in this portion.

Next, as shown in the cross section of FIG. 9A, the photoresist 5 is removed by ashing (ashing treatment). Next, the source connection electrode 8 is formed by depositing, for example, As ⁺ -doped amorphous silicon in the protrusion opening 33 and on the trench upper capacitor electrode 7. When forming this portion, etching and thermal diffusion of impurities are appropriately performed.
The state of this cross section viewed from above is shown in FIG. As shown in FIG. 9B, three protruding portions 20 are provided on each of the facing surfaces of the trench grooves 2 that are separated from each other. Further, the surfaces of the trench grooves 2 facing each other in a pair adjacent to each other are linear. "I" in FIG. 9 (B)
FIG. 9A is a cross-sectional view showing a cross section taken along the line -J ".

Next, a photoresist (not shown) for STI formation is formed in the element isolation region formation planned region by lithography. The subsequent steps are the same as those of the method for manufacturing the semiconductor memory device according to the first embodiment, and description thereof will be omitted. When the phase shift mask is used in this way, the resolution can be improved, and finer holes can be formed than in a commonly used chrome mask. Also in this embodiment, the same effect as in the first embodiment can be obtained. Further, as described above, when the phase shift mask is used, even if the number of openings on the glass mask is reduced, the pattern is formed in the middle of the two openings on the photoresist due to the sidelob effect by bringing the two openings closer to each other. Can be formed,
By performing reactive ion etching on this as in the first embodiment, it is possible to transfer a pattern having three openings onto the semiconductor substrate.

(Fourth Embodiment) The structure of the semiconductor memory device of the present embodiment will be described with reference to FIG. FIG. 17
17A is a cross-sectional view of the memory cell area showing the characteristics of the semiconductor memory device of this embodiment, which has the top surface shape shown in FIGS. 2 and 3, and FIG. It is the figure which added the word line to the cross section on the "AB" line in FIG. The semiconductor memory device of the present embodiment is different from the semiconductor memory device of the first embodiment only in the shape of the source connection electrode 8 and has the other structure in common, and therefore the description of the common points will be omitted. .

As shown in FIG. 17B, which is an enlarged view of the N portion showing the connection portion with the source of the data transfer transistor above the trench capacitor in FIG. 17A, the source connection electrode 8 has the protruding portion 20. Has only the source-side protruding portion 21, and only in the source-side protruding portion 21, the depth is formed to be shallower than the depth of the source connection electrode 8 on the upper capacitor electrode 7. The protrusion 20 is formed to be shallower than the depth of the source 13. Source connection electrode 8 which is the processing depth of the embedded strap portion
In the first embodiment shown in FIG. 5, the source-side protruding portion 21 is deeper than the junction depth of the source 13, and a junction leak current is generated from the stepped portion toward the semiconductor substrate 1. . On the other hand, in the structure of the semiconductor memory device of the present embodiment, the stepped portion of the source connection electrode 8 is
Since it is shallower than the junction depth of the source 13 and surrounded by the source 13, a junction leak current to the semiconductor substrate 1 can be prevented. In the stepped portion of the source connection electrode 8 that has been removed by etching, the source 13 has, for example, a depth of 50 n.
In the case of about m, it is formed with a depth of 50 nm or less.

According to the semiconductor memory device of this embodiment,
In addition to obtaining the same effect as that of the first embodiment, it is possible to further prevent the generation of leak current between the source connection electrode and the semiconductor substrate.

Next, a method of manufacturing the semiconductor memory device of this embodiment will be described. Descriptions of steps common to the method for manufacturing the semiconductor memory device according to the first embodiment will be omitted.
In the method of manufacturing the semiconductor memory device of the first embodiment, the steps shown in FIGS. 6 to 7 are common.
Next, as shown in FIG. 18, the protrusion opening 40 is formed by using the photoresist 31 by dry etching, for example.
Are formed on the ends of the trench groove 2. At this time, the etching amount on the upper surface of the semiconductor substrate 1 is made shallower than a predetermined value of the diffusion depth of the source of the data transfer transistor manufactured in a later step.

Next, as shown in the cross section of FIG. 19, the photoresist 31 is removed by ashing (ashing treatment). Next, the source connection electrode 8 is formed by depositing, for example, As ⁺ -doped amorphous silicon in the protrusion opening 40 and on the trench upper capacitor electrode 7. When forming this portion, etching and thermal diffusion of impurities are appropriately performed. The state of this cross section viewed from above is shown in FIG.

Next, a photoresist (not shown) for STI formation is formed in the element isolation region formation planned region by lithography.

Next, as shown in FIG. 20, using this photoresist as a mask, the upper insulating film 9, the source connection electrode 8 and the upper capacitor electrode 7 in the STI formation planned region are formed.
Then, the upper capacitor sidewall insulating film 6 is removed by etching to form an island pattern of the element isolation trench 35 for STI formation.

Next, as shown in FIG. 17, an insulating film is buried in the element isolation trench 35 for forming each STI to form an element isolation region 18, and adjacent trench capacitors are isolated near the upper surface. .

Next, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are deposited on the active region 15 surrounded by the element isolation region 18 and on the trench capacitor, and processed into a gate shape. To do. Next, a gate side wall insulating film 16 is formed around the gate, and the gate side wall insulating film 16, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, and the WSi gate electrode layer 12 are used as masks in the active region 15. The source 13 and the drain 14 are formed. At this time, the source 13 is formed so as to be deeper than the source connection electrode 8 without fail. Thus, the semiconductor memory device of this embodiment is obtained.

As described above, according to the method of manufacturing the semiconductor memory device of the present embodiment, the junction leak current resulting from the sharply processed shape formed on the contact surface between the source connection electrode end and the semiconductor substrate is reduced. can do. Note that this embodiment can be implemented in combination with either the second embodiment or the third embodiment.

(Fifth Embodiment) The structure of the semiconductor memory device of the present embodiment will be described with reference to FIG. Figure 21
FIG. 9A is a cross-sectional view of a memory cell area showing the characteristics of the semiconductor memory device of the present embodiment, which is different from the semiconductor memory device of the first embodiment only in the shape of the source connection electrode 8. Since the structures are common, description of common points is omitted. In the cross section of FIG. 21A, the trench groove 2
The protruding portion 20 of the source connection electrode 8 is formed on the upper portion not only on the end portion on the source 13 side but also on the element isolation region 18 side. Here, FIG. 21B is a top view of FIG.
FIG. 3B is a cross-sectional view taken along the line “A-B” in FIG. 2A, and the data transfer transistor is not shown in FIG. 2. In the top view shown in FIG. 21B, the active region 15 is provided between the trench grooves 2 arranged apart from each other and surrounded by the element isolation region 18. The active area 15 has a rectangular shape with a semi-elliptical end. The width of the active region 15 is, for example, about 0.175 μ.
It can be m. The length of the protrusion 20 is smaller than the width of the active region 15. Note that, as in FIG.
In practice, other active regions are formed in rows above and below the same line in one active region, being shifted in the longitudinal direction.

Here, in the trench groove 2 facing the active region 15, a plurality of protrusions 2 are formed over the entire periphery thereof.
0 is provided, and the overall top surface shape is an ellipse with a large number of protrusions.

The sectional view taken along the line "CD" in FIG. 21B is the same as that of the first embodiment as shown in FIG.

The semiconductor memory device of the present embodiment has the same effect as that of the first embodiment. Further, by providing the unevenness on the entire surface around the trench in this way, the stress is evenly distributed, and the stress withstand voltage is increased. Will be strengthened.

In the method of manufacturing the semiconductor memory device according to the present embodiment, a glass mask having holes corresponding to the protrusions to be formed is used for transfer to the photoresist, and the process shown in FIG.
9 and 10, the semiconductor substrate 1 and the upper electrode 7 are etched to increase the number of protrusion openings shown in FIG. As shown in FIG. 21, the source connection electrode 8, the upper insulating film 9, the element isolation trench 35, the element isolation region 18, the gate insulating film 10, the polycrystalline silicon gate electrode layer 11, the WSi gate electrode layer 12, the gate sidewall insulation. Membrane 1
6 are sequentially formed. In this way, the semiconductor memory device according to the present embodiment can be manufactured by the same number of steps as the method for manufacturing the semiconductor memory device according to the first embodiment.

[0088]

According to the present invention, it is possible to provide a semiconductor memory device having a trench capacitor for reducing the resistance of a buried strap portion and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a top view showing a structure of the semiconductor memory device according to the first embodiment of the present invention, in which a data transfer gate is omitted.

FIG. 3 is a top view showing the structure of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along the line “C-D” in FIG. 2, which is a top view of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is an enlarged view of an M region in FIG. 1, which is a cross-sectional view of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6A is a cross-sectional view showing a step in the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention, and FIG. 6B is the first embodiment of the present invention. FIG. 9 is a top view of one step in the method of manufacturing the semiconductor memory device according to the first embodiment.

FIG. 7A is a sectional view of a step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and FIG. 7B is the first embodiment of the present invention. FIG. 9 is a top view of one step in the method of manufacturing the semiconductor memory device according to the first embodiment.

FIG. 8 is a sectional view of a step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9A is a sectional view of a step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and FIG. 9B is the first embodiment of the present invention. FIG. 9 is a top view of one step in the method of manufacturing the semiconductor memory device according to the first embodiment.

FIG. 10 is a sectional view of a step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a top view showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 12 is a top view of one step in the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a top view of one step in the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 14 is a top view of one step in the method of manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 15A is a top view of a photoresist in a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, and FIG. 15B is a third embodiment of the present invention. FIG. 16 is a characteristic diagram showing the light intensity of the photoresist shown in FIG. 15 (A).

FIG. 16A is a top view of a photoresist in a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, and FIG. 16B is a third embodiment of the present invention. FIG. 17 is a characteristic diagram showing the light intensity of the photoresist shown in FIG. 16 (A).

FIG. 17A is a cross-sectional view of the structure of the semiconductor memory device according to the fourth embodiment of the present invention, and FIG.
FIG. 17A is an enlarged view of an N region in FIG. 17A which is a cross-sectional view of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a step of the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a step of the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a step of the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 21A is a sectional view showing a structure of a semiconductor memory device according to a fifth embodiment of the present invention, and FIG.
FIG. 9 is a top view showing a structure of a semiconductor memory device according to a fifth embodiment of the present invention with a data transfer gate omitted.

FIG. 22 is a top view showing a structure of a conventional semiconductor memory device in which a data transfer gate is omitted.

FIG. 23A is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor memory device, and FIG. 23B is a top view showing one step of the method for manufacturing a conventional semiconductor memory device.

FIG. 24 is a cross-sectional view showing one step in a conventional method of manufacturing a semiconductor memory device.

[Explanation of symbols]

1 Semiconductor substrate 2 trench groove 3 N-type diffusion layer for capacitor electrode 4 Capacitor insulation film 5 Lower capacitor electrode 6 Upper capacitor sidewall insulation film 7 Upper capacitor electrode 8 Source connection electrode 9 Upper insulating film 10 Gate insulating film 11 Polycrystalline silicon gate electrode layer 12 WSi gate electrode layer 13 Source 14 drain 15 Active area 16 Gate sidewall insulation film 18 element isolation region 20 Projection 21 Source side protrusion 22 Drain side protrusion 30 hole pattern opening 31 Photoresist 33, 40 Projection opening 35 element isolation groove P peak PR1, PR2 reverse phase peak

Claims (8)

[Claims] 1. A semiconductor substrate, an element isolation region provided in an upper surface of the semiconductor substrate, a source and a drain provided in an upper surface other than the element isolation region in the semiconductor substrate, on the semiconductor substrate. A data transfer transistor having a gate electrode provided in the semiconductor substrate, a trench groove provided in the upper surface other than the element isolation region in the semiconductor substrate, and a capacitor electrode provided in the semiconductor substrate around the trench groove below the trench groove. Diffusion layer, a capacitor insulating film that is in contact with the capacitor electrode diffusion layer and is provided on the lower side surface of the trench groove, a lower electrode that is provided in the trench groove so as to cover the capacitor insulating film, and the trench An upper capacitor sidewall insulating film provided on an upper side surface in the trench, and the trench groove in the upper capacitor sidewall insulating film on the lower electrode There is a concave portion and a convex portion on the connection surface between the source and the provided upper capacitor electrode, and the trench groove facing the upper capacitor electrode through the upper capacitor electrode and the upper capacitor sidewall insulating film. The semiconductor memory device is characterized in that the portion has a source connection electrode projecting from the upper capacitor side wall insulating film toward the outside of the trench groove and having a thickness on the upper capacitor side wall insulating film larger than that of the other portion. 2. A trench type capacitor provided in a semiconductor substrate for holding charges, a data transfer transistor for supplying a charge holding voltage to the trench type capacitor, a source of the data transfer transistor and the trench type capacitor. And a buried strap provided with a protruding portion protruding toward the source side and a non-projecting portion not protruding from the source side. 3. The semiconductor memory device according to claim 1, wherein the depth of the convex portion of the source connection electrode is shallower than the depth of the source connected to the source connection electrode. 4. The semiconductor memory device according to claim 2, wherein the depth of the protruding portion of the embedded strap is shallower than the depth of the source to which the embedded strap is connected. 5. The semiconductor memory device according to claim 1, wherein a plurality of convex portions of the source connection electrode are provided. 6. The source connection electrode further has a convex portion projecting with respect to the element isolation region and a concave portion not projecting with respect to the element isolation region at an outer edge portion in contact with the element isolation region. 1. The semiconductor memory device according to 1. 7. A trench groove is formed in a semiconductor substrate, and a capacitor insulating film is formed on a lower side surface in the trench groove,
A trench lower electrode is formed in the trench groove inside the capacitor insulating film, a trench upper capacitor sidewall insulating film is formed on an upper side surface in the trench groove, and a trench upper electrode is formed inside the trench groove inside the trench upper capacitor sidewall insulating film. A step of forming a capacitor electrode; a step of forming a capacitor electrode diffusion layer around the capacitor insulating film in the semiconductor substrate; and an opening extending from above the upper capacitor electrode to outside the trench groove on the semiconductor substrate. Forming a photoresist above the semiconductor substrate, and using the photoresist to etch the opening of the photoresist in the semiconductor substrate, the upper capacitor electrode, and the trench upper capacitor sidewall insulating film. Forming a protrusion opening, and removing the photoresist Then, a step of forming a conductive layer on the projecting portion opening and the upper capacitor electrode to form a source connection electrode, and etching the vicinity of the surface of the semiconductor substrate other than the element formation planned region to form an element isolation region forming groove. A step of forming an insulating film in the element isolation region forming groove, forming a gate electrode on the semiconductor substrate on the element formation planned region, and forming a source and a drain in the semiconductor substrate. And connecting the source to the source connection electrode to form a data transfer transistor. 8. A step of forming the photoresist above the semiconductor substrate, wherein a plurality of openings are provided in the photoresist, and a step of forming the projection opening is performed in the step of forming the projection opening. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the number of openings is greater than the number of openings of the photoresist, and the increased openings of the protrusions are formed by a side-lob effect.