JP2003282665A - Semiconductor failure analysis tool, system, unnecessary analysis method, and semiconductor device manufacturing method - Google Patents

Abstract

(57) Abstract: An object of the present invention is to accurately and quickly grasp the location and cause of a failure analysis of a semiconductor device. At least one or more wiring design layers,
This is a failure analysis tool having a user layer for capturing and displaying the output of a semiconductor failure inspection device or a failure analysis device as data format information, or a technique using them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor failure analysis tool, system and semiconductor failure analysis method for supporting semiconductor failure analysis. The present invention also relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, shortening a failure analysis time is very important for shortening a process construction period and realizing early start-up of a process line. Diagram of process construction flow chart
It will be explained using 6. After selecting process conditions (STEP1),
The manufacturing process of TEG is set and the Si wafer is input to the manufacturing line for manufacturing (STEP2). After performing the appearance inspection of the wafer between the desired steps in this manufacturing process and after the steps (for example, foreign matter inspection after film formation, appearance inspection after etching and CMP, and SEM review after inspection) (STEP3) Tester, prober, etc. Electrical test to determine the TEG quality (S
TEP4). In addition, defect analysis is performed based on the results of visual inspection and electrical test to identify the defective position (STEP5). Based on the specified coordinates, the surface and cross section are observed by SEM and TEM and material analysis (STEP6), the failure mechanism is estimated, and a countermeasure plan is formulated (STEP7). Determine whether the initial yield target has been achieved or not, and take desired measures (process improvement,
Equipment improvement, equipment cleaning, etc.) will be performed (STEP8), and the results will be reflected in subsequent lots to confirm the effects. Since this series of flowcharts is repeated to promote defect reduction and process construction, delay in failure analysis leads to delay in process construction.

Further, in a mass production factory, it is very effective for early recovery from a sudden decrease in yield and improvement in yield at the time of product startup. For this purpose, it is indispensable to identify the defective part in the LSI chip and identify which wiring layer manufacturing process occurred in which manufacturing process was performed in which wiring layer among various manufacturing processes. As a result, it is possible to prohibit the start of the work in the corresponding device, and to take various measures such as cleaning the starter and changing the manufacturing conditions, depending on the cause of the failure, so that shortening the failure analysis time is an important issue.

However, in recent years, miniaturization and high integration of LSI have progressed.
The wiring pattern becomes huge, and the emission microscope and OBIRCH (O
It is difficult to identify the corresponding defective part from the reaction image observed by the semiconductor defect analysis device such as ptical beam induced resistance change).

As a technique for supporting the identification of this defective portion, the coordinates and scale of the reaction image are matched with the layout pattern by using the CAD design data of the LSI under test (hereinafter referred to as [DUT]), and the result is overlaid and displayed on the screen. As a result, the CAD navigation system has come to be used as a semiconductor failure analysis tool, method, and system for navigating defect locations. Japanese Patent Laid-Open No. 9-266235 is disclosed as a conventional technique of a semiconductor defect analysis tool, method, and system, and is achieved by an embodiment.

[0006]

FIG. 7 shows a flowchart of failure analysis. The failure mode (logic failure, current leak, margin failure) of the LSI under test is determined from the failure data obtained from wafer inspection, etc., and the failure analysis method / device is selected and analyzed (STEP 1). For example, in the case of a leak failure, physical failure information such as a light emission / reaction image is output by an emission microscope or OBIRCH analysis. Further, in the case of a logic failure such as a malfunction or a defective operation margin, the electron beam tester outputs the suspected logic cell information of the defective operation. This analysis output is referred to the CAD design data of the DUT, and the suspected failure cell and net (wiring) are extracted and output as a list (STEP2).

However, in the conventional CAD navigation system, the layout information and the netlist information are not compatible with each other, or the light emission / reaction image is simply displayed as superimposed coordinate information and color information on the layout screen. Therefore, the reaction area is not recognized as quantitative data such as area information or weighting information by luminance information. For this reason, the extraction of nets and cells included in the reaction region and intersecting with each other is not achieved in the embodiment described in the known example-Japanese Patent Laid-Open No. 9-266235, and the analyst himself manually performs the reaction on the monitor screen. When the location is wide, it takes a lot of time to prepare the suspected failure list.
Here, the suspected failure list is a list or a set of extracted wirings or cells that may have some kind of failure at that time.

In actual failure analysis, the reaction site by the analyzer is often not the defect occurrence site. For example, when the signal wiring is short-circuited with another wiring, an abnormal potential is input to a normal transistor to emit light. However, the abnormal potential propagates inside the electronic circuit, which may cause a light emission phenomenon. . In such a case, it is necessary to sequentially trace the reaction site and the wiring associated therewith with an electron beam tester or the like to narrow down and identify the defective site. However, this is not achieved in the embodiment described in the publicly known example-Japanese Patent Laid-Open No. 9-266235, and the net cells at the relevant portions cannot be extracted, and similarly, the analyst manually creates the list.

After creating the suspected failure list, suspected failure candidates having a high analysis priority are narrowed down (STEP 3). In order to narrow down the suspected failure candidates, it is necessary to sequentially perform a plurality of failure analyzes such as light emission analysis and OBIRCH analysis, and combine them appropriately to make a comprehensive judgment. However, there are many analysis examples in which the reaction points obtained in each analysis are different, and it is important to generate a suspected failure list for each analysis and analyze the duplication relationship. However, in the known example-the embodiment described in JP-A-9-266235, it is not possible to narrow down the failure candidates by analyzing the overlapping relationship between the failure lists and assigning weight information to the net cells in the suspect list. Much of the judgment depends on the person's analysis experience and knowledge.

The identification of the defective portion (STEP 4) is achieved by repeating the analysis flow for narrowing down the suspected failure candidate. For analysis examples that are difficult to identify, additional defect analysis will be performed depending on the case. After that, the surface and cross section of the identified defective portion are observed by SEM and TEM, and the material is analyzed (STEP5) to identify the cause of the defective portion.

When the CAD navigation system including the known example-Japanese Unexamined Patent Publication No. 9-266235 is considered in the above failure analysis flow chart, the current system has many problems such as insufficient support function. ing. In order to solve the above problems, the analysis output by various failure analysis devices is coordinated on the CAD navigation system,
It is necessary to quantitatively recognize it as area information, and recognize it as the layout data of the DUT on the CAD navigation system and handle it.

An object of the present invention is to accurately grasp the location and cause of failure analysis of a semiconductor device in a short time.

It is another object of the present invention to improve the manufacturing efficiency of semiconductor devices and the yield.

[0014]

[Means for Solving the Problems] In order to achieve the above object, typical solutions disclosed in the present application are as follows.

At least one or more wiring design layers;
It is a failure analysis tool having a user layer for capturing and displaying the output of a semiconductor failure inspection device or a failure analysis device as data format information, or a method using them. Here, the user layer indicates a user area in which the semiconductor failure analysis tool, method, and system can be recognized with the same index as the wiring design layer of the DUT.

A defect analysis system for performing defect analysis of a semiconductor device, which is a semiconductor defect inspection device or defect analysis device for performing defect inspection or inspection of a semiconductor device, a wiring design layer, and the semiconductor defect inspection device or It is a failure analysis system having a failure analysis tool having a user layer for capturing and displaying the output of the failure analysis apparatus as data format information.

Further, a wiring pattern design process for the semiconductor device, a manufacturing process for manufacturing the semiconductor device based on the design information, a testing process for testing the manufactured or a semiconductor device in the middle of the manufacturing process, A method of manufacturing a semiconductor device having an analysis / evaluation step of analyzing or evaluating a test result, wherein in the analysis / evaluation step, a wiring design layer and a user layer for capturing and displaying an output of a semiconductor failure analysis apparatus as data format information. Perform a failure analysis using a failure analysis tool that has, and if the analysis result clears a predetermined condition, the semiconductor device is produced, and if the predetermined condition cannot be cleared, the analysis result is included in the analysis result in the design process. This is a method of manufacturing a semiconductor device in which the wiring pattern is redesigned based on the above.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a CAD navigation system 101 which is an example of a failure analysis system of the present embodiment. In the present embodiment, since the analysis output by the semiconductor failure analysis device 114 is treated as the same index as the layout data of the DUT, the coordinates, the area information generation unit 113, the data conversion unit 112, as compared with the conventional CAD navigation system shown in FIG. A user layer database 111 is newly provided. The input analysis output of the semiconductor failure analysis device 114 is coordinates, coordinates in the area information generation unit 113, area area information,
Luminance information is generated. The data conversion unit 112 converts the image data and the like into polygon data based on the generated information, converts the data into defective layout data of the user layer, and then stores the same in the user layer database 111. In addition, the user layer database 111 is an external arbitrary file format 1
Various data can be entered at 15. As input examples, net (wiring) / cell information of DUT obtained from various analysis devices such as electron beam tester and IDDQ analysis device, layout pattern information with strict process margin, weighting conditions of analysis obtained from past failure analysis Input data is diverse.

The DUT design data is the layout data 10
2. Layout-to-netlist correspondence information data 103 and netlist data 104 are input to the system. Each data is passed through the data conversion unit 105 to the layout database 10
6, layout vs. netlist correspondence information database 10
7, accumulated in the netlist database 108. The databases are linked to each other, and the layout display section
They are output and displayed on the 109 and the net list display unit 110 while mutually corresponding.

FIG. 2 is a schematic diagram of an analysis screen 201 in the CAD navigation system 101 of this embodiment. On the screen, together with the design layout information for each wiring layer of the DUT, the output of the failure analysis device is output and displayed as the failure layout 204 on the user layer 205. The display color of the defective layout 204 can be arbitrarily designated, and the display color can be changed for each analysis device / method so that the analyst can visually distinguish on the screen. For example, the display method, for example, the display color or display shape, etc., may be changed according to the cause of failure or the analysis result of the cause of failure, or the display method may be changed for each result of failure analysis methods such as light emission analysis or OBIRCH analysis, or each design layer The display method may be changed and displayed for each failure analysis result.

Each defective layout 204 has area area information and luminance information, and the barycentric coordinates 20 are used based on the area area information.
7 can be calculated and displayed. This barycentric coordinate can be arbitrarily reset by the analyst on the analysis screen 201. The calculation of the barycentric coordinates is also performed on the layout cell 203 and the net 202 of the DUT, and the net 202 performs the area division based on the starting point, the ending point, and the inflection point coordinate information, and calculates the centroids for each divided element. Further, each defective layout 204 can be enlarged or reduced by the analyst by designating an arbitrary area ratio based on the barycentric coordinates 207. Moreover, the defective layout 204 can be reset and redisplayed by using the brightness information as a threshold value (brightness value = a, b, c), and a layout region showing a strong light emission reaction can be extracted.

With reference to the defective layout 204 and the layout of the DUT, nets and cells included, intersecting, and adjacent to the reaction area are extracted.

FIG. 3 is a schematic view of the inclusion, intersection, adjacent net cell extraction and list generation screens in the CAD navigation system 101 of this embodiment. Analysis condition input section 301
The function that defines the inclusion relationship when more than% of the cell area is included in the defective layout by referring to the barycentric coordinates and the area information, and the more than% of the net wiring are included in the defective layout. , It has a function of defining a cross relationship, and based on this definition, the target net cell is extracted and the suspected failure list 303 is output. This extraction and list output can be performed for each layer recognized by the CAD navigation system 101.
It is possible to output a list for a specific layer or all layers for a DUT having multiple layers such as layers and 5 layers. When extracting adjacent net cells,
It has a function of defining adjacency when the distance between the center of gravity of the cell and the center of gravity of the defective layout is less than a certain value. Based on this definition, the extraction of the adjacent net cells and the list output can be performed for each recognized layer. The output of this list 303 can be saved or input in any file format in the file input / output unit 302.

The suspicious defect candidates are narrowed down by light emission analysis and OB.
It is required to perform multiple defect analyzes such as IRCH analysis in order and combine them appropriately to make a comprehensive judgment. FIG. 4 shows a schematic diagram of failure analysis using a plurality of failure layouts. A defect layout is created for each defect analysis output, and the defect layout is input / displayed in the user layer 205 sorted by defect analysis device / analysis method. For each defective layout 204, reference is made to the design layout information of each layer of the DUT to extract the suspected failure net cell and output the list. With respect to the suspected failure list 303, the integrated arithmetic processing unit 502 analyzes the overlapping relationship such as the logical product and the logical sum, and generates the common suspected failure list 503 and the all suspected failure list 504. The list has weighting information such as duplication and failure analysis priority, and the common net cell 401 having a high degree of duplication is displayed in gray scale on the analysis screen according to the weighting information. List output of duplication analysis can be output to a specific layer or all layers, and can be saved and input in any file format.

FIG. 8 shows a schematic diagram of the related wiring and route runup analysis for a specific net cell. From the suspected failure list and the displayed net cell on the analysis screen, the run-up origin adjacent net cell 801 is designated. It is possible to specify a plurality of net cells, and input from any external file format 115. In the run-up condition input unit 805, the number of run-up stages from the starting point adjacent net cell is designated. Based on the run-up condition, the run-up net 802 / run-up cell 803 information is extracted and output as a list. The list output of the upstream analysis has layer information and can be output to a specific layer or all layers.
You can save or input in any file format.

As a result, in semiconductor failure analysis, it is possible to narrow down suspected failure candidates, improve efficiency of identification work, and shorten analysis time. In addition, through the failure analysis examples, it is possible to establish analysis conditions and methods for shortening the analysis time by accumulating threshold value information of the brightness when narrowing down the defective layout and creating a database.

FIG. 10 shows a schematic diagram of a manufacturing process flow of a semiconductor product. Defect analysis is an indispensable flow for process construction and design condition change in the design stage, and yield improvement and defect countermeasures in the mass production stage. The effects produced by the embodiment of the present embodiment are not limited to simply improving the efficiency and time of failure analysis, but are extremely wide-ranging in the semiconductor manufacturing process, the semiconductor manufacturing method, and the manufacturing process. A method of manufacturing a semiconductor device will be specifically described.

In the manufacturing process of semiconductor devices, mass production of the device is started through a design (function / theory / circuit) process, a trial manufacturing process, an evaluation process, a defect analysis process, a countermeasure process, etc. in accordance with a market research and customer's request. To be done. The mass production process includes a process of forming a circuit element on a wafer, a process of inspecting a wafer-shaped semiconductor device, a process of dicing a wafer, and a process of forming leads and bumps on a semiconductor chip.

FIG. 11 shows a flow chart of manufacturing a semiconductor device. In FIG. 11, the product wafer manufactured in the process of step S1 is subjected to initial defect selection by P inspection (Pellet inspection) in step S2. Then, the non-defective wafers selected are processed in step S3.
Or, proceed to S5. The selection as to whether to proceed to step S3 or S5 is made based on the relation of manufacturing equipment and the like.

In step S3, the product wafer is diced, and only non-defective chips are individually packaged in CSP (Chip Size Package), BGA (Ball Grid Array) or the like in step S4. Then, the process proceeds to step S7.

In step S5, a wiring pattern and a protective film are collectively formed on the wafer, and further,
Perform solder ball attachment. Subsequently, in step S6, the wafer on which the wiring pattern and the like are formed is individually divided by dicing. Then, the process proceeds to step S7.

In step S7, a semiconductor device inspection method using a semiconductor element inspection socket is performed. In other words, the product of the final shape divided into
The test socket is used for the burn-in test for final selection. Then, finally obtained non-defective products are shipped in step S8. In recent years, a wafer level chip size package has been introduced in which a semiconductor element is inspected, rewiring and external connection terminals are formed at a wafer level, and then a wafer is diced to form a semiconductor device. The manufacturing of the semiconductor device described above is performed based on the design which is the first step of the semiconductor manufacturing process. Therefore, performing unnecessary analysis based on the information obtained in the evaluation and inspection processes, understanding the cause of defects, and taking appropriate measures such as changing the wiring pattern in the design process are very important in the subsequent mass production process. It becomes important. That is, the defect analysis and the circuit design have an effect on all devices, such as improvement of the yield in the mass production stage. Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Nor.

The representative aspects disclosed in the above embodiments are as follows.

(1) A failure analysis tool characterized by having at least one or more wiring design layers and a user layer for capturing and displaying the output of a semiconductor failure inspection device as data format information.

(2) In addition, the defect analysis tool is characterized by having at least one or more wiring design layers and a user layer for capturing and displaying the output of the semiconductor defect analysis device as data format information.

(3) The defect analysis tool according to (1) or (2) above, which is characterized in that it has a plurality of user layers.

(4) The defect analysis tool according to (3) above, wherein the user layer can be displayed in association with each wiring design layer.

(5) In the defect analysis tool according to (1) or (2) above, the user layer can be displayed for each type of the semiconductor defect inspection device or each type of the semiconductor defect analysis device. It is a characteristic failure analysis tool.

(6) The defect analysis tool according to (2) above, wherein the output data of the semiconductor defect analysis device in the previous period has at least either the light emission analysis data of the wiring or the OBIRCH analysis data. It is a failure analysis tool.

(7) The defect analysis tool according to (1) or (2) above, wherein the user layer takes in information in which the output is converted into coordinate and area information data format as layout data and displays it. It is a failure analysis tool characterized by:

(8) In the failure analysis tool described in (2) above, the suspected faulty wiring or cell information of the LSI under test is extracted using the user layer and the wiring design layer, and the extracted faulted failure is extracted. It is a semiconductor failure analysis tool characterized by displaying wiring or cell information in association with information that is predetermined and specifies wiring or cells.

(9) In the failure analysis tool according to (2) above, the suspected faulty wiring or cell information of the LSI under test is extracted using the user layer and the wiring design layer, and the extracted faulted failure is extracted. The defect analysis tool is characterized by displaying wiring or cell information on a layer other than the user layer or a wiring design layer of the defect analysis tool.

(10) The defect analysis tool according to (3) above, wherein the suspected faulty wiring extracted among a plurality of user layers formed by using different semiconductor defect inspection apparatuses or semiconductor defect analysis apparatuses or It is a failure analysis tool characterized by performing duplicate analysis on cells and displaying a suspected failure frequency or analysis priority.

(11) A defect analysis system for performing defect analysis of a semiconductor device, which includes a semiconductor defect inspection device for inspecting a semiconductor device, a wiring design layer, and an output of the semiconductor defect inspection device as data format information. The defect analysis system is characterized by having a defect analysis tool having a user layer for capturing and displaying as.

(12) A defect analysis system for performing defect analysis of a semiconductor device, wherein the semiconductor defect analysis device for inspecting the defect of the semiconductor device, the wiring design layer, and the output of the semiconductor defect analysis device are data format information. It is a wiring design tool characterized by having a user layer that is captured and displayed as.

(13) A wiring pattern design process for a semiconductor device, a manufacturing process for manufacturing a semiconductor device based on the design information, and a testing process for testing a semiconductor device that has been manufactured or is in the middle of the manufacturing process. A method of manufacturing a semiconductor device having an analysis / evaluation step of analyzing or evaluating the test result, wherein the analysis / evaluation step captures and displays a wiring design layer and an output of a semiconductor failure analysis apparatus as data format information. A failure analysis is performed using a failure analysis tool having a layer, and if the analysis result clears a predetermined condition, a semiconductor device is produced, and if the predetermined condition cannot be cleared, the analysis is performed in the design process. A method of manufacturing a semiconductor device is characterized in that the wiring pattern is redesigned based on a result.

Further, in the CAD navigation system, there is provided a semiconductor failure analysis system and method characterized by having a user layer for inputting an analysis output by the semiconductor failure analysis apparatus.

Further, in the CAD navigation system, the semiconductor failure analysis system and method are characterized in that a plurality of analysis outputs from a plurality of semiconductor failure analysis devices can be input to the user layer.

Further, the present invention is a semiconductor defect analysis system and method characterized in that in a CAD navigation system, an analysis output by a semiconductor defect analysis device is converted into coordinates and area information data formats and input and recognized as layout data.

Further, in the CAD navigation system, the LSI under test is analyzed based on the analysis output by the semiconductor failure analysis apparatus.
The semiconductor failure analysis system and method are characterized by extracting the suspected failure net / cell information and outputting the list.

Further, the semiconductor failure analysis system and method are characterized in that duplication analysis is performed between the suspected failure net / cell list outputs, and the suspected failure frequency and analysis priority are extracted and output as a list.

Further, the CAD navigation system is a semiconductor defect analysis system and method characterized in that it has a plurality of user layers for inputting the analysis output of the semiconductor defect analysis device. Further, in the CAD navigation system, an arbitrary LSI under test is selected. The semiconductor failure analysis system and method are characterized in that a path is traced back to a designated net cell.

According to the embodiment described above, the analysis output from each analysis device is converted into quantitative data as coordinates, area, luminance information, etc., and is recognized and displayed as layout information of the user layer. Can be handled in the same way as the layout data of the DUT. This will make the work of narrowing down the failure candidates more efficient,
It is possible to identify the failure location of the semiconductor product, shorten the analysis time, and promptly take defect prevention and improvement measures.

TE which is indispensable for process construction
G failure analysis time can be shortened. Due to this effect, the process construction period can be shortened, and a very large effect can be brought about for early startup of the process line.

Further, in the mass production factory, by shortening the failure analysis time, it is possible to take early various countermeasures such as countermeasures against the defects of the starting apparatus and changes in the manufacturing conditions, depending on the causes of the failures. This can bring about a great effect on the early recovery from a sudden decrease in yield and the improvement in yield at the time of product startup.

[0056]

According to the present invention, the location and cause of failure analysis can be accurately grasped in a short time.

Further, it is possible to improve the manufacturing efficiency of semiconductor devices and the yield.

[Brief description of drawings]

[Figure 1] Schematic diagram of CAD navigation system

[Figure 2] Schematic view of analysis screen

FIG. 3 Inclusion in the CAD navigation system 101,
Schematic of intersection, adjacent net cell extraction and list generation screen

FIG. 4 is a schematic diagram of defect analysis using a defect layout.

FIG. 5: Failure analysis flow using multiple suspected failure lists

FIG. 6 Process construction flowchart

7] Defect analysis flowchart

[Fig. 8] Schematic diagram of route upstream analysis

[Figure 9] Schematic diagram of conventional CAD navigation system

FIG. 10 is a schematic diagram of a semiconductor manufacturing process flow 1

FIG. 11 is a schematic view of a semiconductor manufacturing process flow 2

[Explanation of symbols]

101 CAD navigation system 201 Analysis screen 202 net 203 cells 204 bad layout 205 User layer 206 Design layer 207 barycentric coordinates 301 Analysis condition input section 302 File input / output section 303 Suspected Failure List 801 Run-up origin cell 802 Combined (one-stage) net 803 Run-up (1 stage) cell 804 Combined (2-stage) net

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Muraoka             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory F term (reference) 2G132 AA00 AB02 AC10 AE11 AE14                       AE16 AE18 AH07 AL09                 4M106 AA01 DA20                 5F064 AA04 EE23 FF12 FF48 HH06                       HH10 HH11 HH13 HH14

Claims (13)

[Claims] 1. At least one or more wiring design layers,
A failure analysis tool having a user layer for capturing and displaying the output of a semiconductor failure inspection device as data format information. 2. At least one wiring design layer,
A failure analysis tool having a user layer for capturing and displaying the output of a semiconductor failure analysis device as data format information. 3. The failure analysis tool according to claim 1, wherein the failure analysis tool has a plurality of user layers. 4. The failure analysis tool according to claim 3, wherein the user layer can be displayed corresponding to each of the wiring design layers. 5. The defect analysis tool according to claim 1 or 2, wherein the user layer can be displayed for each type of the semiconductor defect inspection device or each type of the semiconductor defect analysis device. Analysis tool. 6. The failure analysis tool according to claim 2, wherein the output data of the semiconductor failure analysis device in the first half includes at least either light emission analysis data of the wiring or OBIRCH analysis data. tool. 7. The defect analysis tool according to claim 1 or 2, wherein the user layer fetches and displays, as layout data, information in which the output is converted into a coordinate and area information data format. Defect analysis tool to do. 8. The defect analysis tool according to claim 2, wherein the suspected faulty wiring or cell information of the LSI under test is extracted using the user layer and the wiring design layer, and the extracted faulty wiring or A failure analysis tool, which displays cell information in association with information that is predetermined and identifies wiring or cells. 9. The failure analysis tool according to claim 2, wherein the suspected faulty wiring or cell information of the LSI under test is extracted using the user layer and the wiring design layer, and the extracted faulty wiring or A failure analysis tool for displaying cell information in a layer other than the wiring design layer of the user layer or the failure analysis tool. 10. The failure analysis tool according to claim 3, further comprising: a suspected failure wiring or cell extracted between a plurality of user layers formed by using different semiconductor failure inspection apparatuses or semiconductor failure analysis apparatuses. A failure analysis tool that performs duplicate analysis and extracts and displays the suspected failure frequency or analysis priority. 11. A defect analysis system for performing a defect analysis of a semiconductor device, comprising: a semiconductor defect inspection device for performing a defect inspection of a semiconductor device; a wiring design layer; and an output of the semiconductor defect inspection device as data format information. A failure analysis system having a failure analysis tool having a user layer for capturing and displaying. 12. A failure analysis system for performing failure analysis of a semiconductor device, comprising: a semiconductor failure analysis device for inspecting a failure of the semiconductor device; a wiring design layer; and an output of the semiconductor failure analysis device as data format information. A failure analysis system having a user layer for capturing and displaying. 13. A process for designing a wiring pattern of a semiconductor device, a manufacturing process for manufacturing a semiconductor device based on the design information, a testing process for testing a semiconductor device that has been manufactured or is in the process of manufacturing, and A method of manufacturing a semiconductor device having an analysis / evaluation step of analyzing or evaluating a test result, wherein in the analysis / evaluation step, a wiring design layer and a user layer for displaying an output of a semiconductor failure analysis apparatus as data format information are displayed. If the analysis result clears a predetermined condition, the semiconductor device is manufactured. If the predetermined condition cannot be cleared, the analysis result is obtained in the design process. A method of manufacturing a semiconductor device, characterized in that the wiring pattern is redesigned based on the above.