JP2003273942A - Serial communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a loss of synchronization by inserting a synchronization trigger and realize communication at an optimum transfer rate according to the accuracy of a clock oscillation frequency to avoid a decrease in the transfer rate. It is an object of the present invention to realize a one-wire serial communication system capable of performing the above. SOLUTION: In a serial communication system in which a master 1 and a slave 2 are connected by a serial interface 3 having only one line and data is sequentially transmitted one bit at a time, a synchronization trigger for synchronization is transmitted. A predetermined number of n (> 1) bits of data are transmitted between the trigger and the next synchronization trigger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication system, and more particularly to a serial communication system in which synchronization accuracy and communication speed are adjusted.

[0002]

2. Description of the Related Art In a one-wire serial communication system in which a master and a slave are connected by only one wire and data is sequentially transmitted bit by bit, communication is properly synchronized in order to properly transmit and receive communication. Need to be.
If the clocks of either the master or the slave or both of them are inaccurate due to the CR oscillation method, etc., it is only possible to guarantee the coincidence of the timings for a short time after the synchronization, so it has been the conventional practice. For example, synchronization is maintained by a method of attaching a synchronization trigger for each bit. FIG. 3 shows a waveform of data when a synchronization trigger is attached to each bit. However,
If such a method is adopted, the transfer rate is reduced by the amount of the synchronization trigger, which causes a problem that it is not suitable for high-speed data transfer.

As a character-based data transmission method that has been used conventionally, start-stop synchronization is performed in which a start bit and a stop bit are added to each character before and after the character data to indicate character delimiters. There is a formula transmission method. In this case, 11-12 including the character data and the parity bit between the start bit and the stop bit.
Bits are sent. With this method, the transfer rate can be made higher than in the case where a synchronous trigger is added for each bit, but it cannot be said to be the optimum one that matches the clock oscillation accuracy.

[0004]

In the conventional one-wire serial communication system, when the accuracy of the oscillation frequency of the clock is bad on the transmitting side, the receiving side, or both, a synchronization shift occurs and a synchronization error occurs. There is a problem, and there has been a method of inserting a synchronization trigger for each bit in order to avoid this, but if this happens, the transfer rate will be reduced by the amount of the synchronization trigger, and there is a problem that it is not suitable for high-speed data transfer. The present invention solves this problem in a relatively simple way, inserting a sync trigger to prevent sync loss,
It is an object to realize a 1-wire serial communication system capable of avoiding a decrease in transfer rate by realizing communication at an optimum transfer rate according to the accuracy of the clock oscillation frequency.

[0005]

In order to achieve the above object, the present invention provides a serial communication system in which transmission and reception are connected by only one line and data is sequentially transmitted bit by bit.
A synchronization trigger is transmitted to synchronize transmission and reception, and a predetermined number n (> 1) is set between this synchronization trigger and the next synchronization trigger.
It is characterized by transmitting bit data. As a result, it is relatively easy to realize the communication at the optimum transfer rate that matches the accuracy of the clock oscillation frequency while preventing the synchronization deviation, and to avoid the decrease of the transfer rate. A serial communication system can be realized.

[0006]

DETAILED DESCRIPTION OF THE INVENTION The serial communication system of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a master / slave system in which the serial communication system of the present invention is implemented. In FIG. 1, reference numeral 1 is a master, reference numeral 2 is a slave, and reference numeral 3 is a serial interface (communication line). Communication data is sent from the master 1 to the slave 2 via the one-wire serial interface 3.

The waveform of the transmission data of the present invention is shown in FIG.
FIG. 2 shows an example in which 4-bit data is sent between one synchronization trigger and the next synchronization trigger. If one of the master 1 or slave 2 has a stable clock frequency and the other clock frequency has a large error, the number of bits sent between one synchronization trigger and the next synchronization trigger is n, and the clock oscillation is generated. Assuming that the period is t and the oscillation period on the side with many errors fluctuates within the range of t ± Δt, the conditions for correctly transmitting and receiving without bit shift are as follows.

[0009]       t> nΔt (1)

If there are many errors in the clock frequencies of both master 1 and slave 2, the number of bits sent between one synchronization trigger and the next synchronization trigger is n, and the clock oscillation period is t. Side oscillation cycle is t ± Δ
If the oscillation cycle of the other side fluctuates within the range of t1 within the range of t1 and t ± Δt2, the conditions for correct transmission / reception without bit shift are as follows.

[0011]       t> n (Δt1 + Δt2) (2)

From equation (1) or equation (2), the number of bits n of data inserted and sent between the synchronization triggers is determined. From a different point of view, the sync trigger is the data n
It should be inserted bit by bit. As described above, communication can be realized at an optimum transfer rate that matches the accuracy of the oscillation frequency of the clock while preventing the synchronization deviation, and a decrease in the transfer rate can be avoided.

[0013]

As described above, according to the invention of claim 1 of the present invention, the transmission and reception are synchronized in the serial communication system in which the transmission and reception are connected by only one line and data is sequentially transmitted bit by bit. Is transmitted, and data of a predetermined number n (> 1) bits is transmitted between this synchronization trigger and the next synchronization trigger. As a result, it is possible to realize a one-wire serial communication system that can prevent a decrease in transfer rate while inserting a synchronization trigger to prevent synchronization deviation.

According to the second aspect of the present invention, the number n of bits of data inserted between one synchronization trigger and the next synchronization trigger is determined by the error of the clock cycle. As a result, it is possible to realize communication at an optimum transfer rate that matches the accuracy of the clock oscillation frequency, and to realize a one-wire serial communication method that can avoid a decrease in transfer rate.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a master / slave system in which a serial communication system of the present invention is implemented.

FIG. 2 is a waveform diagram of transmission data according to the present invention.

FIG. 3 is a waveform diagram of conventional transmission data.

[Explanation of symbols]

1 master 2 slaves 3 Serial interface (communication line)

Claims (2)

[Claims] 1. In a serial communication system in which transmission and reception are connected by only one line and data is sequentially transmitted bit by bit, a synchronization trigger for synchronizing the transmission and reception is transmitted, and this synchronization trigger and the next synchronization trigger are transmitted. A predetermined number n (> 1) between
A serial communication method characterized by transmitting bit data. 2. The serial communication system according to claim 1, wherein the predetermined number n is determined by an error of a clock cycle.