JP2003273249A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: An SRAM memory cell having a coupling capacitance is manufactured by using a damascene gate process.
Provide technology that can improve the performance and reliability of SOLUTION: After forming a gate groove 18 on a semiconductor substrate 1, an SRAM memory cell is formed by embedding a gate insulating film made of a high dielectric constant material 19 and a gate electrode made of a metal film 20 inside the gate groove 18. Load MISF
ETQp ₂ is formed, and a high-dielectric-constant material 19 is used to form a capacitive insulating film of the coupling capacitance C ₁ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and in particular, an M in which a gate insulating film is made of a high dielectric constant material and a gate electrode is made of a low resistance metal
ISFET (metal insulator semiconductor field ef)
SRAM (static random a) with fect transistor
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a ccess memory).

[0002]

2. Description of the Related Art IEDM98 (High Performance Metal
Gate MOSFETs Fabricated by CMP for 0.1 μm Regime) discloses an example of a damascene gate process using a chemical mechanical polishing (CMP) technique.

In the damascene gate process described in the above document, first, a dummy gate insulating film and a dummy gate electrode are formed on a semiconductor substrate, then a diffusion layer (source, drain) is formed on the semiconductor substrate, and a gate is formed. An interlayer insulating film is formed on the electrodes. Next, after selectively removing the dummy gate electrode, a gate insulating film made of a tantalum oxide film is deposited, and subsequently, a laminated film of TiN and W deposited on the semiconductor substrate is polished by a CMP method. A gate electrode made of a laminated film of TiN and W is formed inside the groove formed by removing the dummy gate electrode.

In the above process, since the gate insulating film is formed after forming the diffusion layers (source and drain),
The heat load in the process after forming the gate insulating film and the gate electrode can be reduced, and the gate insulating film and the gate electrode can be formed of a material having low heat resistance.

[0005]

The following is a damascene gate process studied by the present inventor, the outline of which is as follows.

First, a dummy gate insulating film and a dummy gate are formed on a substrate, and then, a source / drain is formed on the substrates on both sides of the dummy gate, and then an interlayer insulating film is formed on the substrate. Then, for example, CMP (chemical mec
The interlayer insulating film is polished until the upper surface of the dummy gate is exposed by using the hanical polishing method, and the dummy gate and the dummy gate insulating film are selectively removed. Then, the gate insulating film and the gate electrode are formed inside the gate trench. Buried and MISFET is formed. The gate insulating film can be made of, for example, a tantalum oxide film, and the gate electrode can be made of, for example, a tungsten film.

As described above, in the damascene gate process, since the gate insulating film and the gate electrode are formed after forming the source / drain, a high dielectric constant material having low heat resistance can be used for the gate insulating film, and the gate insulating film can be used. A low resistance metal film having low heat resistance, such as aluminum, copper or titanium, can be used for the electrodes.

In particular, by using a high dielectric constant material for the gate insulating film, the capacitance of the gate insulating film can be increased even if the film thickness is relatively large, and the carrier density accumulated in the gate insulating film is increased. It is possible to improve the driving capability of the MISFET and reduce the tunnel leak current of the gate insulating film due to the increase in the physical film thickness.

Regarding the MISFET formed by using the damascene gate process, for example, International Electron Device Meetin
gs. "High Performance Metal Gate MOSFETs Fabricated
by CMP for 0.1 μm Regime "1998).

By the way, at present, a coupling capacitor is installed on a substrate as a measure against a SRAM soft error. Furthermore, as the element becomes finer, a large coupling capacitance is required in a small area, so we are considering thinning the capacitance insulating film that constitutes the coupling capacitance and applying materials with a relatively high dielectric constant. Has been done. The capacitive insulating film may be formed, for example, by thermal CVD (chemical vapor deposition).
The silicon nitride film formed by the method is used, and the silicon nitride film has advantages that the relative permittivity is larger than that of the silicon oxide film and the leak current is smaller than that formed by the plasma CVD method. have.

However, in the conventional SRAM manufacturing process, the coupling capacitance portion is formed after the MISFET is formed on the substrate. Therefore, the MI of SRAM
When the damascene gate process is used for manufacturing an SFET, a capacitive insulating film forming a coupling capacitor is formed after forming a high-dielectric constant material having low heat resistance and a low-resistance metal film. Heat C with a large heat load on the film
A silicon nitride film formed by the VD method cannot be used.

It is an object of the present invention to provide a technique capable of manufacturing an SRAM memory cell having a coupling capacitance by using a damascene gate process and improving the performance and reliability of the SRAM.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, after the gate groove is formed on the substrate, a gate insulating film made of a high dielectric constant material and a gate electrode made of a metal film are embedded in the gate groove to form the SRA.
The MISFET forming the M memory cell is formed, and the capacitive insulating film having the coupling capacitance is formed by using the material of the same layer as the high dielectric constant material.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a flip-flop circuit, which is an embodiment of the present invention, and a transfer MISFE.
SRAM composed of T and coupling capacitance
It is an equivalent circuit diagram showing a memory cell.

The memory cell comprises two n-channel MISFs.
ET (driving MISFETs Qd ₁ and Qd ₂ ) and two p-channel MISFETs (load MISFETs Qp ₁ and Qd)
p ₂ ) and a pair of CMOS (Complementary Metal)
Oxide Semiconductor) includes inverters INV ₁ and INV ₂ and includes a flip-flop circuit that stores 1-bit information.

One of the input / output terminals (storage node) of this flip-flop circuit is connected to the source of the transfer MISFET Qt ₁ , and the other input / output terminal (storage node) is connected to the source of the transfer MISFET Qt ₂ and is mutually connected. Coupling capacitors C ₁ and C ₂ are coupled between the input and output terminals. Further, the drains of the transfer MISFETs Qt ₁ and Qt ₂ are connected to the data lines DL ₁ and DL ₂ , respectively.

Further, one end (the source of each of the load MISFETs Qp ₁ and Qp ₂ ) of the flip-flop circuit is connected to the power supply voltage Vcc, and the other end (driving MISFET Q).
The sources of d ₁ and Qd ₂ ) are connected to the reference voltage Vss. Power supply voltage Vcc is, for example, 1.2V, and reference voltage Vss is, for example, 0V (GND potential).
Is.

FIG. 2 shows an SR according to an embodiment of the present invention.
It is a principal part top view of the semiconductor substrate which shows the specific structure of about one AM memory cell.

Six MISFETs constituting a memory cell
Is formed in an active region L provided on the main surface of the semiconductor substrate, and the active region L is surrounded by an element isolation portion made of an insulating film. Driving MISFETs Qd ₁ and Qd ₂ and n-channel type transfer MIS
The FETs Qt ₁ and Qt ₂ are formed in the active region of the p-well, and the p-channel type load MISFETs Qp ₁ and Qp ₂ are formed in the active region of the n-well.

The transfer MISFETs Qt ₁ and Qt ₂ are gate electrodes F made of a metal film, for example, a tungsten film.
G ₁ and FG ₂ , respectively, and gate electrodes FG ₁ and
FG ₂ is formed on a gate insulating film made of a high dielectric constant material such as a tantalum oxide film. Also, transfer MI
The sources and drains of the SFETs Qt ₁ and Qt ₂ are composed of n-type semiconductor regions formed in the active region L of the p well.

CMOS inverter INV₁Drive that composes
Dynamic MISFET Qd₁And load MISFET Qp₁When
Is a common gate electrode FG₃With CMOS Inverter
INV ₂MISFET Qd for driving₂And for load
MISFETQp₂And the common gate electrode FG_FourHave
And these gate electrodes FG₃, FG_FourThe above gate
Electrode FG₁, FG₂It has a high dielectric constant because it is composed of a metal film like
It is formed on the gate insulating film made of a material. For drive
MISFET Qd₁, Qd₂Source and drain are p-way
Of the n-type semiconductor region formed in the active region L of the
MISFET for load Qp₁, Qp₂Source Dray
Is a p-type semiconductor region formed in the active region L of the n-well
Composed of. The gate electrode FG₁~ FG_FourThe gate of
The length Lg is, for example, about 80 nm, and the gate width W is
For example, it is about 200 nm.

Further, the gate electrode FG ₃ is provided with the CMOS inverter I through the conductive film embedded in the connection hole CONT ₁ and the local wiring L ₂ provided thereunder.
It is connected to the input / output terminal of NV ₂ (the drain of the load MISFET Qp ₂ , the drain of the driving MISFET Qd ₂ and the source of the transfer MISFET Qt ₂ ). Similarly, the gate electrode FG ₄ is formed of the conductive film embedded in the connection hole CONT ₁ and the local wiring L provided therebelow.
₁ through the input / output terminal of the CMOS inverter INV ₁ (the drain of the load MISFET Qp ₁ , the driving MIS
Drain of FET Qd ₁ and transfer MISFET Qt ₁
Source).

The local wirings L ₁ and L ₂ are MISFETs for load.
Sources of Qp ₁ and Qp ₂ and driving MISFETs Qd ₁ and Q
It is composed of the same layer (indicated by hatching in the figure) as the metal film embedded in the connection hole CONT ₂ on the source of d ₂ and the drains of the transfer MISFETs Qt ₁ and Qt ₂ .

In the coupling capacitors C ₁ and C ₂ , a part of the metal film forming the local wirings L ₁ and L ₂ is used as a lower layer electrode, and an upper layer made of a metal film sandwiching the lower layer electrode and the capacitor insulating film. And electrodes. The capacitance insulating film is MI
It is formed of the same layer as the high dielectric constant material that forms the gate insulating film of the SFET, and the upper layer electrode is formed of the same layer as the metal film that forms the gate electrodes FG _{1 to} FG ₄ of the MISFET.
The upper layer electrode covers predetermined portions of the local wirings L ₁ and L ₂ and the gate electrodes FG ₃ and FG ₄ , and the upper layer electrode of the coupling capacitance C ₁ is the gate electrode FG ₃ of the CMOS inverter INV _{1 and} the coupling. The upper electrode of the capacitor C ₂ is CMOS
It is connected to the gate electrode FG ₄ of the inverter INV ₂ .

Next, SRA which is an embodiment of the present invention
A method of manufacturing a part of the M memory cell will be described in the order of steps with reference to FIGS. FIG. 2A shows the line AA ′ in FIG.
2 is a cross-sectional view of a main part corresponding to a line cross section, and FIG.
Is a sectional view of a main part corresponding to the section taken along line BB ′ of FIG.
A method of manufacturing the local wirings L ₁ and L ₂ , the coupling capacitance C ₁ and the load MISFET Qp ₂ will be exemplified.

First, as shown in FIG. 3, the specific resistance is 10Ω.
A semiconductor substrate (thin plate having a substantially circular shape in plan view called a semiconductor wafer) 1 made of a p-type silicon single crystal having a size of about 1 cm is prepared, and a groove-type separation portion 2 is formed on the main surface thereof. That is, after forming an isolation groove having a depth of, for example, about 250 nm at a predetermined position of the semiconductor substrate 1, an insulating film made of, for example, a silicon oxide film is deposited on the semiconductor substrate 1, and the insulating film is formed only in the isolation groove. The isolation portion 2 is formed by polishing the insulating film by a CMP method so as to remain.

Subsequently, after forming a silicon oxide film on the surface of the semiconductor substrate 1, a predetermined impurity is selectively introduced into a predetermined portion of the semiconductor substrate 1 at a predetermined energy by an ion implantation method, whereby the n well 3 is formed. And p-well 4 is formed.

Next, after cleaning the surface of the semiconductor substrate 1,
A dummy gate insulating film 5 having a thickness of, for example, about 3 nm is formed on the main surface of the semiconductor substrate 1 surrounded by the isolation portion 2, and a dummy gate 6 is further formed thereon. Dummy gate 6
Can be formed, for example, by depositing a silicon polycrystal film on the semiconductor substrate 1 by the CVD method and then processing the silicon polycrystal film using a dry etching technique using a photoresist pattern as a mask. The thickness of the silicon polycrystalline film is about 200 nm, for example.

Then, using the dummy gate 6 as a mask,
By introducing a p-type impurity, such as boron fluoride, into the n-well 3 by an ion implantation method, the MISF for load is loaded.
A pair of extension regions 7 forming a part of the source / drain of ETQp ₁ and Qp ₂ are formed. The junction depth of the extension region 7 is, for example, about 30 nm. Similarly, the dummy gate 6 as a mask, n-type impurities into the p-well 4, for example by introducing arsenic by ion implantation, although not shown in the driving MISFET Qd _1, Qd ₂ and transfer MISFET Qt _1, Qt ₂ A pair of extension regions forming part of each source / drain are formed.

Next, after depositing an insulating film, for example, a silicon oxide film having a thickness of about 60 nm on the semiconductor substrate 1, this insulating film is anisotropically etched, for example, RIE (reactive).
Then, the spacers 8 are formed on the sidewalls of the dummy gates 6 by the ion etching method.

Subsequently, the dummy gate 6 and the spacer 8
Is used as a mask to introduce a p-type impurity, such as boron fluoride, into the n-well 3 by an ion implantation method to form a pair of diffusion regions 9p forming another part of the source / drain of the load MISFETs Qp ₁ and Qp _2. To form. The junction depth of the diffusion region 9p is, for example, about 100 nm. Similarly, by using the dummy gate 6 and the spacer 8 as a mask, an n-type impurity, such as arsenic, is introduced into the p-well 4 by an ion implantation method.
ISFETs Qd ₁ and Qd ₂ and transfer MISFET Qt
A pair of diffusion regions 9n forming another part of the source / drain of ₁ and Qt ₂ are formed. Then RTA
(Rapid Thermal Annealing) method, for example, 10
The impurities introduced by the above ion implantation are activated by applying heat treatment at 00 ° C. for 1 second.

Then, a cobalt film and a titanium nitride film are sequentially deposited on the semiconductor substrate 1 by the sputtering method. The cobalt film has a thickness of, for example, about 10 nm, and the titanium nitride film has a thickness of, for example, about 10 nm. Further, a heat treatment at about 500 to 600 ° C. is applied to the semiconductor substrate 1 for about 60 seconds to make the surface of the dummy gate 6 and the diffusion region 9
A silicide layer 10 having a thickness of about 30 nm is selectively formed on the surfaces of p and 9n. After that, the unreacted cobalt film on the insulating film is selectively removed, and the semiconductor substrate 1 is further subjected to 700-
Heat treatment at about 800 ° C. is performed for about 90 seconds to reduce the resistance of the silicide layer 10.

Next, as shown in FIG. 4, a silicon nitride film 11 and a silicon oxide film 12 are formed on the semiconductor substrate 1 by CV.
Deposition is sequentially performed by the D method. The silicon nitride film 11 has a thickness of, for example, about 30 nm, and the silicon oxide film 12 has a thickness of, for example, about 300 to 400 nm. The silicon oxide film 12 is formed of, for example, TEOS (Tetra Ethyl Ortho
Silicate: made of Si (OC ₂ H ₅₎₎ and the TEOS oxide film and ozone formed by the plasma CVD method using a source gas. Then, the silicon oxide film 12 and the silicon nitride film 11 are polished by the CMP method to form the interlayer insulating film 13 whose surface is flattened and expose the surface of the dummy gate 6.

Next, as shown in FIG. 5, the silicon oxide film 12 is etched by using the resist pattern as a mask.
To process. At this time, the silicon nitride film 11 functions as an etching stopper layer. Then, the exposed silicon nitride film 11 is removed, so that the connection hole CONT ₂ and the groove 14 for the local wiring are formed in a self-aligned manner with respect to the isolation portion 2 and the spacer 8.

Next, the connection hole CONT₂And in the groove 14
A metal film, such as a tongue, on the entire surface of the semiconductor substrate 1 including the parts.
A stainless film or the like is formed. Then the connection hole CONT₂And
And the metal film in the region other than the groove 14 is removed by the CMP method.
Connection hole CONT₂Form the plug 15 inside the
Local wiring L inside 14₁, L₂To form. Local wiring L
₁, L₂A part of the metal film forming the
₁, C₂A lower layer electrode.

Next, as shown in FIG. 6, the local wiring L ₁ ,
L ₂ , dummy gate 6, spacer 8, silicon nitride film 1
1 and the silicon oxide film 12 are processed to form a groove 17 for the coupling capacitor C ₁ having a predetermined depth. Although not shown, similarly, a groove for the coupling capacitor C ₂ having a predetermined depth is formed. Next, as shown in FIG. 7, after removing the resist pattern 16, the dummy gate 6 and the dummy gate insulating film 5 are selectively removed to form a gate groove 18.

Next, as shown in FIG. 8, a high dielectric constant material 19 is deposited on the entire surface of the semiconductor substrate 1 including the inside of the groove 17 and the gate groove 18. The high dielectric constant material 19 is made of, for example, a tantalum oxide film, an alumina film, a hafnium oxide film, a zirconium oxide film, a titanium oxide film, a zirconium silicon oxide film or a hafnium silicon oxide film, and is deposited on the semiconductor substrate 1. The thickness of the dielectric constant material 19 is
For example, the SiO ₂ equivalent film thickness considering the relative permittivity is 1.5
It is set to be about 2 nm.

Then, a metal film 20, for example, a titanium nitride film or a tungsten film is deposited on the entire surface of the semiconductor substrate 1 including the inside of the groove 17 and the gate groove 18 by the CVD method.

Next, as shown in FIG. 9, the metal film 20 and the high-dielectric-constant material 19 in the regions other than the groove 17 and the gate groove 18 are removed by the CMP method, and the load MISFET Qp is placed inside the gate groove 18. _The high dielectric constant material 19 forming the gate insulating film ₂ and the metal film 20 forming the gate electrode FG ₄ are formed, and the high dielectric constant material forming the capacitive insulating film of the coupling capacitance C ₁ is formed inside the groove 17. 19 and the metal film 20 forming the upper electrode is formed. Although not shown, similarly, the gate insulating film and the gate electrodes FG _{1 to} FG _{3 of} another MISFET are formed, and the coupling capacitance C
_{The second} capacitive insulating film and the upper electrode are formed.

Next, as shown in FIG. 10, the semiconductor substrate 1
After the interlayer insulating film 21 is formed thereon, the interlayer insulating film 21 is dry-etched using the resist pattern as a mask.
Contact holes CONT ₁ and CONT ₃ are formed in the. Connection hole CO
NT ₁ is formed in a region connecting the gate electrode FG ₃ common to the CMOS inverter INV ₁ and the input / output terminal of the CMOS inverter INV ₂ , and the connection hole CONT ₃ is formed on the connection hole CONT ₂ . Although not shown, the connection hole CONT ₁ is further formed in a region connecting the gate electrode FG ₄ common to the CMOS inverter INV ₂ and the input / output terminal of the CMOS inverter INV ₁ .

Subsequently, a metal film, for example, a tungsten film is deposited on the entire surface of the semiconductor substrate 1 including the insides of the connection holes CONT ₁ and CONT ₃ by the CVD method, and thereafter, a region other than the connection holes CONT ₁ and CONT ₃ is formed. The metal film is removed by the CMP method to form the plug 22 inside the connection holes CONT ₁ and CONT ₃ .

After that, a wiring layer is formed and the entire surface of the semiconductor substrate 1 is covered with a passivation film, whereby the SRAM memory cell of the first embodiment is substantially completed.

In the first embodiment, the MISFET is
Although the gate electrodes FG _{1 to} FG ₄ are formed of the metal film 20 such as a titanium nitride film or a tungsten film, they may be formed of a metal film having low heat resistance such as an aluminum film, a copper film or a titanium film.

As described above, according to the first embodiment, S
Since the gate insulating film of the MISFET and the capacitive insulating films of the coupling capacitors C ₁ and C ₂ that form the RAM memory cell can be formed in the same layer, the gate insulating film made of a high dielectric constant material is used by using the dummy gate process. It is possible to form an SRAM memory cell composed of a gate electrode composed of a film and a metal film, and by forming the capacitive insulating film of a high dielectric constant material, a coupling capacitance C ₁ having a large capacitance even in a relatively small area. , C ₂ can be formed, so that the performance and reliability of the SRAM can be improved. Furthermore, since the gate insulating film of the MISFET and the capacitive insulating film of the coupling capacitors C ₁ and C ₂ can be simultaneously formed, it is possible to prevent an increase in the number of manufacturing steps.

(Embodiment 2) FIG. 11 is a plan view of a main portion of a semiconductor substrate showing a specific structure of one SRAM memory cell according to another embodiment of the present invention.

Similar to the memory cell of the first embodiment,
It is composed of 6 MISFETs and 2 coupling capacitors. The transfer MISFETs Qt ₁ and Qt ₂ have a common gate electrode FG ₅ made of a metal film such as a tungsten film, and the gate electrode FG ₅ is formed on a gate insulating film made of a high dielectric constant material such as a tantalum oxide film. Has been formed.

CMOS inverter INV₁Drive that composes
Dynamic MISFET Qd₁And load MISFET Qp₁When
Is a common gate electrode FG₆With CMOS Inverter
INV ₂MISFET Qd for driving₂And for load
MISFETQp₂And the common gate electrode FG₇Have
And these gate electrodes FG₆, FG₇The above gate
Electrode FG_FiveIs composed of a metal film like
Is formed on the gate insulating film.

Further, the gate electrode FG ₇ has a connection hole CO
The local wiring L ₃ is connected to a local wiring L ₃ (indicated by hatching in the figure) via a conductive film embedded in NT ₅ , and the local wiring L ₃ is an input / output terminal of the CMOS inverter INV ₁ (load MISFET Qp ₁ Drain, drive MISFET
It is connected to the drain of Qd ₁ and the source of the transfer MISFET Qt ₁ .

A part of the metal film forming the local wiring L ₃ forms the lower electrodes of the coupling capacitors C ₁ and C ₂ . For example, the coupling capacitance C ₁ is the load MISF.
The local wiring L ₃ on the drain of ETQp ₁ is used as a lower layer electrode,
The coupling capacitance C ₂ uses the local wiring L ₃ on the drain of the driving MISFET Qd ₁ and the source of the transfer MISFET Qt ₁ as a lower layer electrode. Coupling capacitors C ₁ and C ₂ are formed by the lower electrode and the upper electrode made of a metal film with the capacitor insulating film interposed therebetween. The capacitance insulating film is M
It is formed of the same layer as the high dielectric constant material that forms the gate insulating film of the ISFET, and the upper layer electrode is formed of the same layer as the metal film that forms the gate electrodes FG _{5 to} FG ₇ of the MISFET.

(Third Embodiment) FIG. 12 is a cross-sectional view of a main part of a semiconductor substrate showing an SRAM memory cell according to another embodiment of the present invention. FIG. 1A shows the first embodiment.
2 is a sectional view of a main part corresponding to the section taken along the line AA ′ of FIG. 2, and FIG. 7B is a sectional view of the main part corresponding to the section taken along the line BB ′ of FIG. 2 of the first embodiment. There is.

The aspect ratio of the gate groove 23 of the memory cell is set to be larger than the aspect ratio of the groove 17 in which the upper electrodes of the coupling capacitors C ₁ and C ₂ are buried, for example, 2.5 or more, and the gate groove 23 The high dielectric constant material 24 which is embedded inside and constitutes the gate insulating film is formed under the condition that the step coverage is relatively bad.

As described above, according to the third embodiment, the thickness of the capacitance insulating film for the coupling capacitors C ₁ and C ₂ can be made larger than that of the gate insulating film. The leak current of the insulating film can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, MISF is used.
The case of application to the method of manufacturing the coupling capacitance of the SRAM memory cell formed by connecting to the gate electrode of ET has been described, but it can also be applied to the method of manufacturing a capacitive element that is not connected to the gate electrode of MISFET. For example, as shown in FIG. 13, by using the manufacturing method described in the first embodiment and further connecting and wiring by an upper wiring layer, an analog circuit including a lower layer electrode 25, a capacitance insulating film 26 and an upper layer electrode 27 is formed. Capacitive element C can be formed.

[0058]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

A damascene gate process can be used to form an SRAM memory cell having a coupling capacitance, and a coupling capacitance having a large capacitance can be formed even in a relatively small area. High reliability can be achieved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing an SRAM memory cell composed of a flip-flop circuit, a transfer MISFET, and a coupling capacitor according to an embodiment of the present invention.

FIG. 2 is a main-portion plan view of a semiconductor substrate showing a specific configuration of approximately one SRAM memory cell according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM memory cell according to an embodiment of the present invention.

FIG. 11 is a plan view of a main portion of a semiconductor substrate showing a specific configuration of approximately one SRAM memory cell according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view of essential parts of a semiconductor substrate showing an SRAM memory cell according to another embodiment of the present invention.

FIG. 13 is an SRA that is an application example of an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main portion of a semiconductor substrate showing an M memory cell.

[Explanation of symbols]

1 semiconductor substrate 2 isolation part 3 n well 4 p well 5 dummy gate insulating film 6 dummy gate 7 extension region 8 spacer 9p diffusion region 9n diffusion region 10 silicide layer 11 silicon nitride film 12 silicon oxide film 13 interlayer insulating film 14 trench 15 plug 16 Resist Pattern 17 Groove 18 Gate Groove 19 High Dielectric Material 20 Metal Film 21 Interlayer Insulating Film 22 Plug 23 Gate Groove 24 High Dielectric Material 25 Lower Layer Electrode 26 Capacitance Insulating Film 27 Upper Layer Electrode Qd ₁ Driving MISFET Qd ₂ Driving MISFET Qp ₁ load MISFET Qp ₂ load MISFET Qt ₁ transfer MISFET Qt ₂ transfer MISFET C ₁ coupling capacitance C ₂ coupling capacitance C analog circuit capacitance element INV ₁ CMOS inverter INV ₂ CMOS inverter DL ₁ data line DL ₂ Data line Vcc Source voltage Vss reference voltage L active region FG ₁ gate electrode FG ₂ gate electrode FG ₃ gate electrode FG ₄ gate electrode FG ₅ gate electrode FG ₆ gate electrode FG ₇ gate electrode Lg gate length W the gate width CONT ₁ connection hole CONT ₂ connecting hole CONT ₃ connection hole CONT ₄ connection hole CONT ₅ connection hole CONT connection hole L ₁ local wiring L ₂ local wiring L ₃ local wiring

Claims (5)

[Claims] 1. A gate insulating film and a metal film of a MISFET made of the high dielectric constant material, comprising: forming a gate groove in an insulating film on a substrate; and burying a high dielectric constant material and a metal film inside the gate groove. The MISFET comprising
A gate electrode is formed, and a capacitive insulating film of a capacitive element formed on the substrate is formed of a material in the same layer as the high dielectric constant material, and a method for manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device, comprising forming a MISFET and a capacitive element on the same substrate, comprising: (a) forming a dummy gate insulating film and a dummy gate on the substrate, and then forming the dummy gate Forming a source / drain on the substrates on both sides; (b) forming an interlayer insulating film on the substrate and then polishing the interlayer insulating film to expose the surface of the dummy gate; ) A step of forming a first groove in a predetermined portion of the interlayer insulating film, and then burying a conductive film in the first groove to form a lower electrode of the capacitor, and (d) at least the capacitor Forming a second groove having a predetermined depth in a predetermined portion of the lower electrode, further forming a third groove by removing the dummy gate and the dummy gate insulating film, and (e) the second groove. And the third Inside embedded high dielectric constant material, the capacitor insulating film and the MIS of the capacitive element
Forming a gate insulating film of the FET, further burying a metal film in the second and third trenches, and forming an upper layer electrode of the capacitance element and a gate electrode of the MISFET. Manufacturing method of semiconductor integrated circuit device. 3. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a MISFET and a capacitive element on the same substrate, comprising: (a) forming a dummy gate insulating film and a dummy gate on the substrate, and then forming the dummy gate Forming a source / drain on the substrates on both sides; (b) forming an interlayer insulating film on the substrate and then polishing the interlayer insulating film to expose the surface of the dummy gate; ) A step of forming a first groove in a predetermined portion of the interlayer insulating film, and then burying a conductive film in the first groove to form a lower electrode of the capacitor, and (d) at least the capacitor Forming a second groove having a predetermined depth in a predetermined portion of the lower electrode, further forming a third groove by removing the dummy gate and the dummy gate insulating film, and (e) the second groove. And the third Inside embedded high dielectric constant material, the capacitor insulating film and the MIS of the capacitive element
Forming a gate insulating film of the FET, further burying a metal film inside the second and third trenches, and forming an upper layer electrode of the capacitive element and a gate electrode of the MISFET. The aspect ratio of the groove is larger than the aspect ratio of the second groove, and the thickness of the capacitive insulating film of the capacitive element is formed to be thicker than the thickness of the gate insulating film of the MISFET. Manufacturing method of semiconductor integrated circuit device. 4. A transfer MISFET and a load MI.
A pair of CMO consisting of SFET and driving MISFET
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a memory cell having a flip-flop circuit composed of an S inverter and a coupling capacitor connected to an input / output terminal of the flip-flop circuit on the same substrate. a) forming a dummy gate insulating film and a dummy gate on the substrate and then forming source / drain on the substrate on both sides of the dummy gate; and (b) forming an interlayer insulating film on the substrate, Polishing the interlayer insulating film to expose the surface of the dummy gate; and (c) forming a first groove in a predetermined portion of the interlayer insulating film, and then forming a conductive film inside the first groove. Burying, forming a local wiring including the lower electrode of the coupling capacitor, and (d) at least a dummy gate common to the local wiring and the CMOS inverter. Forming a second groove having a predetermined depth in a predetermined portion of the gate, and further removing the dummy gate and the dummy gate insulating film to form a third groove; and (e) the second and the second A high dielectric constant material is embedded in the groove 3 to form a capacitance insulating film of the coupling capacitance and a gate insulating film of the MISFET, and a metal film is embedded in the second and third grooves, And a step of forming an upper layer electrode of a coupling capacitor and a gate electrode of the MISFET, the method for manufacturing a semiconductor integrated circuit device. 5. A method of manufacturing a semiconductor integrated circuit device, comprising forming a MISFET and a capacitance element for an analog circuit on the same substrate, comprising: (a) forming a dummy gate insulating film and a dummy gate on the substrate, Forming a source / drain on the substrate on both sides of the dummy gate; and (b) forming an interlayer insulating film on the substrate and then polishing the interlayer insulating film to expose the surface of the dummy gate. (C) a step of forming a first groove in a predetermined portion of the interlayer insulating film, and then burying a conductive film inside the first groove to form a lower layer electrode of the analog circuit capacitor. d) A second groove having a predetermined depth is formed at least in a predetermined portion of the lower layer electrode of the analog circuit capacitor, and the dummy gate and the dummy gate insulating film are removed to form a third groove. And (e) a high dielectric constant material is embedded in the second and third grooves to form a capacitance insulating film of the analog circuit capacitive element and a gate insulating film of the MISFET, and further, A metal film is embedded in the second and third grooves, and the upper layer electrode of the analog circuit capacitor and the MIS are formed.
And a step of forming a gate electrode of the FET.