JP2003258130A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A bird's beak generated in an interlayer film interposed between a floating gate and a control gate of a memory cell is suppressed, and a decrease in a writing speed of a flash memory is suppressed. SOLUTION: An interlayer film 4 interposed between a conductor film 3 for a floating gate and a conductor film 5 for a control gate is formed by a silicon nitride film 4a having a silicon nitride film 4a disposed at the lowermost layer, a silicon oxide film 4b, It is composed of a four-layered stacked film composed of a silicon nitride film 4c and a silicon oxide film 4d. Accordingly, bead bark of the silicon oxide film constituting a part of the interlayer film 4 can be suppressed, so that a decrease in the capacity of the interlayer film 4 can be suppressed and a decrease in the writing speed can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to an electrical collective erase type EEPROM (el
The present invention relates to a technique effectively applied to a semiconductor device having an ectric erasable programmable read only memory (hereinafter referred to as a flash memory).

[0002]

2. Description of the Related Art A nonvolatile memory capable of electrically writing and erasing data requires a memory because it can be rewritten while being incorporated in a wiring board and is easy to use. Widely used in various products.

In particular, the flash memory has a function of collectively electrically erasing data in a certain range of the memory array (all memory cells of the memory array or a predetermined memory cell group). Furthermore, the flash memory is 1
Due to the transistor stacked gate structure, miniaturization of cells is advanced, and there are great expectations for high integration.

In the one-transistor stacked gate structure, one memory cell is basically one double-layer gate MISFET.
(Metal insulator semiconductor field effect trans
istor). The two-layer gate MISFE
The T is formed by providing a floating gate on a semiconductor substrate via a tunnel insulating film and further stacking a control gate on the floating gate via an interlayer film. Data is stored by injecting electrons into the floating gate or extracting electrons from the floating gate.

For example, Japanese Unexamined Patent Publication No. 8-279566 discloses a parallel type flash memory in which memory cells of each column of a flash memory array are connected in parallel as one type of a nonvolatile semiconductor memory device of this type. Has been done.

[0006]

FIG. 11 is a cross-sectional view of essential parts showing a memory cell having a two-layer gate structure of a parallel flash memory studied by the present inventor.

The memory cell has a pair of semiconductor regions 22S and 22S formed on the semiconductor substrate 21 with the channel region interposed therebetween.
D, and a conductor film 24 for a floating gate formed on the main surface (active region) of the semiconductor substrate 21 via a gate insulating film 23.
And a conductor film 26 for a control gate formed on the interlayer film 25. Further, although not shown, an insulating film is formed so as to cover the conductor film 26 for the control gate, and a predetermined wiring electrically connects to the semiconductor region 22D forming a drain through a connection hole formed in the insulating film. It is connected.

By the way, the interlayer film 25, which is located between the floating gate and the control gate and has a function of insulating the two, is
A silicon oxide film 25c is stacked on the silicon oxide film 25a via a silicon nitride film 25b to form a laminated structure effective for leak characteristics.

However, as a result of the study by the present inventor, the silicon oxide films constituting the upper and lower layers of the interlayer film 25 are formed by the heat treatment applied to the semiconductor substrate 21 after patterning the gates (floating gates and control gates) of the memory cells. It was revealed that bird's beaks were generated in 25a and 25c. For example, in the silicon oxide films 25a and 25c having a thickness of about 5 nm, bird's beaks having a thickness of about 10 nm are formed.

As memory cells are miniaturized, the effect of the bird's beak on the device performance increases,
For example, the capacity of the interlayer film 25 is reduced, and the rewriting speed is reduced.

An object of the present invention is to provide a technique capable of suppressing a bird's beak generated in an interlayer film interposed between a floating gate and a control gate of a memory cell and suppressing a decrease in writing speed of a flash memory. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, the interlayer film interposed between the floating gate and the control gate is a laminated structure composed of a silicon nitride film, a silicon oxide film, a silicon nitride film and a silicon oxide film in which a silicon nitride film is arranged at the lowermost layer. Or a laminated film having a laminated structure composed of a silicon nitride film, a silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film in which a silicon nitride film is arranged in the lowermost layer and the uppermost layer.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a schematic diagram of a partial equivalent circuit of a memory array included in a parallel flash memory which is an embodiment of the present invention. In addition, in FIG. 1, a memory cell for 4 bits is provided with two word lines and two word lines.
Although an array configuration is shown using a plurality of bit lines, the number of memory cells and the number of word lines and bit lines are not limited to this.

The memory array MARY comprises memory cells MC
₁₁ , the control gates of MC ₁₂ are connected to the word line W ₀ ,
Each control gate of the memory cells MC ₂₁ and MC ₂₂ has a word line W
₁ , the drains D of the memory cells MC ₁₁ and MC ₂₁ are connected to the sub-bit line SB ₀ , and the memory cells M
The drains D of C ₁₂ and MC ₂₂ are connected to the sub bit line SB ₁ . Furthermore, memory cells MC ₁₁ , MC ₁₂ , MC
Each source S of ₂₁ and MC ₂₂ is connected to a local source line SS. Although not shown, the sub bit line SB
₀ and SB ₁ are electrically connected to the main bit line, and the local source line SS is electrically connected to the common source line.

A method of manufacturing a flash memory according to an embodiment of the present invention will be described in the order of steps with reference to FIGS. In these figures, a cross-sectional view of a main part of a memory array is shown, in which a channel region of a memory cell is cut along a direction intersecting a word line.

First, on the main surface of a semiconductor substrate (a semiconductor thin plate having a substantially circular shape in plan view called a semiconductor wafer at this stage),
For example, a groove-type isolation portion and an active region arranged so as to be surrounded by the isolation portion are formed. That is, after forming a separation groove in a predetermined portion of the semiconductor substrate, an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate,
Further, the insulating film is polished by a CMP (Chemical Mechanical Polishing) method or the like so that the insulating film is left only in the separation groove to form a separation portion.

Subsequently, as shown in FIG. 2, the semiconductor substrate 1
N well NWm and p well PWm are formed by selectively introducing a predetermined impurity with a predetermined energy into a predetermined portion of the substrate by ion implantation.

Next, as shown in FIG. 3, a gate insulating film 2 having a thickness of, for example, about 9 to 11 nm is formed on the semiconductor substrate 1 by a thermal oxidation method, and then, having a thickness of, for example, 40 nm on the semiconductor substrate 1. A conductive film 3 made of silicon polycrystal having a degree of n-type conductivity is formed by CVD (Chemical Vapor Deposit).
ion) method. Then, the interlayer film 4 is formed on the semiconductor substrate 1. The interlayer film 4 is, for example, a silicon nitride film 4a, a silicon oxide film 4b, a silicon nitride film 4
c is a laminated film obtained by sequentially depositing c and the silicon oxide film 4d by a CVD method from the lower layer. The silicon nitride film 4a has a deposited film thickness of, for example, about 1 to 2 nm, and the silicon oxide film 4b has a deposited film thickness of For example, about 5 nm,
The deposited film thickness of the silicon nitride film 4c is, for example, about 10 nm, and the deposited film thickness of the silicon oxide film 4d is, for example, 5 nm.
It is a degree. Therefore, S considering the relative dielectric constant of the interlayer film 4
The iO ₂ converted film thickness is about 15 nm.

Thereafter, although not shown, the conductor film 3 is patterned by a photolithography technique and a dry etching technique to process the conductor film 3 so as to separate the floating gates adjacent to each other in the extending direction of the word lines. .

Next, a conductor film 5 made of, for example, a silicon polycrystalline film having n-type conductivity and having a thickness of about 150 nm is deposited on the semiconductor substrate 1 by the CVD method, and then the cap insulating film 6 is formed on the semiconductor substrate 1. To form.

Next, as shown in FIG. 4, the cap insulating film 6, the conductor film 5, the interlayer film 4 and the conductor film 3 are sequentially patterned by a dry etching method using the resist pattern as a mask. As a result, a control gate made of the conductor film 5 and a floating gate made of the conductor film 3 are formed.
That is, the two-layer gate structure of the memory cell is completed in which the control gate made of the conductor film 5 is stacked on the floating gate made of the conductor film 3 with the interlayer film 4 interposed therebetween.

Then, using the gates (control gate and floating gate) as masks, n-type impurities are added to the p-well PWm.
For example, arsenic is introduced by the ion implantation method to form the extended semiconductor regions 7S and 7D forming a part of the source / drain of the memory cell. In addition, after forming the gate having the two-layer structure, an in-place film may be formed on the semiconductor substrate 1 by a thermal oxidation method, a CVD method, or the like.
This in-plus film is provided to reduce the damage that is likely to occur at the end of the floating gate conductor film 3 and the end of the gate insulating film 2 during the ion implantation, and its thickness is, for example, 20. It is about 30 nm.

Next, as shown in FIG. 5, an insulating film made of, for example, a silicon nitride film is deposited on the semiconductor substrate 1 by the CVD method and then etched back by the anisotropic dry etching method. , Spacers 8 are formed on the side surfaces of the gates (control gate and floating gate).

Then, using the gates (control gates and floating gates) and spacers 8 as a mask, the p well PW is formed.
By introducing an n-type impurity such as arsenic into m by an ion implantation method, diffusion semiconductor regions 9S and 9D forming another part of the source / drain of the memory cell are formed.

Next, as shown in FIG. 6, the semiconductor substrate 1
Is washed with, for example, a hydrofluoric acid solution, and then a cobalt film having a thickness of, for example, about 10 to 20 nm is deposited on the semiconductor substrate 1 by a sputtering method. Subsequently, a heat treatment at about 500 to 600 ° C. is applied to the semiconductor substrate 1 to selectively form a thickness of 3 on the surfaces of the source / drain diffusion semiconductor regions 9S and 9D.
A silicide film 10 having a thickness of about 0 nm is formed. After that, unreacted cobalt is removed, and then heat treatment at about 700 to 800 ° C. is applied to the semiconductor substrate 1 to reduce the resistance of the silicide film 10.

Next, as shown in FIG. 7, an insulating film 11 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1 by CV.
After being deposited by the D method, the insulating film 11 is provided with a silicide film 10 formed on the drain diffusion semiconductor region 9D.
The connection hole 12 that exposes a part of is exposed by photolithography and dry etching.

Subsequently, a metal film such as tungsten is deposited on the semiconductor substrate 1 and the surface of the metal film is flattened by the CMP method, so that the metal film is embedded in the connection hole 12 and the plug is formed. 13 is formed. afterwards,
A metal film such as tungsten is deposited on the semiconductor substrate 1 by a sputtering method, and is patterned by a photolithography technique and a dry etching technique to form the wiring 14 of the first layer. The wiring 14 is electrically connected to the diffusion semiconductor region 9D of the drain of the memory cell through the plug 13.

Thereafter, on the semiconductor substrate 1, a wiring in an upper layer than the wiring 14 is formed, and then a surface protective film is further formed. Then, an opening is formed so that a part of the uppermost wiring is exposed. A memory cell of a flash memory is manufactured by forming and forming a bonding pad.

FIG. 8 shows the relationship between the coupling of the memory cell of the first embodiment and the memory cell studied by the present inventor and the gate length of the control gate, and FIG. 9 shows the first embodiment.
The relationship between the inter-layer capacitance of the memory cell and the memory cell studied by the present inventor and the gate length of the control gate is shown. The memory cell of the first embodiment has an interlayer formed of a stacked film of the silicon nitride film 4a, the silicon oxide film 4b, the silicon nitride film 4c and the silicon oxide film 4d described in FIG. 7 between the floating gate and the control gate. The memory cell having the film 4 and examined by the present inventor has a structure in which the silicon oxide film 25a, the silicon nitride film 25b, and the silicon oxide film 25c shown in FIG. 11 are stacked between the floating gate and the control gate. It has an interlayer film 25 made of a film. The SiO ₂ converted film thickness of the interlayer films 4 and 25 is about 15 nm.

As shown in FIG. 8, in the memory cell studied by the present inventor, the coupling decreases sharply as the gate length of the control gate decreases from about 0.18 μm. In the memory cell, the coupling length of the control gate is almost constant up to about 0.13 μm, and the coupling decreases rapidly from about 0.13 μm as the gate length becomes shorter.

Further, as shown in FIG. 9, the interlayer capacitance of the memory cell of the first embodiment is larger than the interlayer capacitance of the memory cell examined by the present inventor, and the control gate of the memory cell examined by the present inventor is The interlayer capacitance when the gate length is 0.18 μm and the interlayer capacitance when the gate length of the control gate in the memory cell of the first embodiment is 0.13 μm are almost the same.

Thus, the silicon nitride film 4a having a thickness of about 1 to 2 nm is formed on the floating gate, and the silicon oxide film 4b, the silicon nitride film 4c and the silicon oxide film 4d are formed on the floating gate to form the interlayer film 4. By doing so, the coupling and the interlayer capacitance can be improved. It is considered that this is because the bird's beak of the silicon oxide film 4b was suppressed by using the silicon nitride film 4a as an underlay.

Although the silicon nitride film 4a forming the lowermost layer of the interlayer film 4 is formed by the CVD method in the first embodiment, the surface layer of the floating gate conductor film 3 is formed of NO _x.
The silicon nitride film 4a may be replaced with the silicon nitride film by a nitrogen treatment using gas.

As described above, according to the first embodiment, by laying the silicon nitride film 4a on the lowermost layer of the interlayer film 4 of the laminated structure interposed between the floating gate and the control gate,
Since the bird's beak of the silicon oxide film 4b on the silicon nitride film 4a is suppressed, the capacity decrease of the interlayer film 4 is suppressed, and the decrease of the writing speed can be suppressed.

(Embodiment 2) FIG. 10 is a sectional view showing the principal part of a semiconductor substrate showing a flash memory according to another embodiment of the present invention.

The interlayer film 15 located between the floating gate and the control gate in the second embodiment is, for example, a silicon nitride film 15a, a silicon oxide film 15b, or a silicon nitride film 15.
c, silicon oxide film 15d and silicon nitride film 15e
Is a laminated film obtained by sequentially depositing by the CVD method from the lower layer, and the deposited film thickness of the silicon nitride film 15a is
For example, the thickness of the silicon oxide film 15b is about 4 nm, the thickness of the silicon nitride film 15c is about 6 to 7 nm, and the thickness of the silicon oxide film 15d is about 3 to 4 nm. The thickness of the deposited silicon nitride film 15e is, for example, about 4 to 5 nm. Therefore, the SiO ₂ converted film thickness of the interlayer film 15 is 15
It becomes about nm.

As described above, according to the second embodiment, by laying the silicon nitride film 15a on the lowermost layer of the interlayer film 15 of the laminated structure interposed between the floating gate and the control gate, the silicon nitride film 15a is formed. The bird's beak of the upper silicon oxide film 15b is suppressed, and the bird's beak of the silicon oxide film 15d below the silicon nitride film 15e is suppressed by placing the silicon nitride film 15e on the uppermost layer of the interlayer film 15. It is possible to suppress a decrease in capacity and a decrease in writing speed.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, the interlayer film interposed between the floating gate and the control gate has a four-layer structure or a five-layer structure in which a silicon nitride film and a silicon oxide film are alternately stacked. The number of layers to be stacked is not limited to this.

Further, in the above-mentioned embodiment, the case where the invention is applied to the interlayer film of the two-layer gate which constitutes the memory cell of the parallel type flash memory has been described, but any flash memory having the two-layer gate with the interlayer film interposed is described. The same effect can be obtained by being applicable to a memory cell.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

An interlayer film formed by stacking a plurality of layers of a silicon nitride film and a silicon oxide film, which is interposed between a floating gate and a control gate forming a two-layer gate of a memory cell, is a bottom layer or a bottom layer and a top layer. By adopting the structure in which the silicon nitride film is arranged in the above, the bird's beak of the silicon oxide film forming a part of the interlayer film can be suppressed. As a result, a decrease in capacity of the interlayer film is suppressed, and a decrease in writing speed can be suppressed.

[Brief description of drawings]

FIG. 1 is a partial equivalent circuit diagram of a memory array included in a flash memory according to an embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view of the semiconductor substrate, showing the method of manufacturing the memory array of the flash memory according to the embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor substrate, showing a method of manufacturing a memory array of a flash memory according to an embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing a method of manufacturing a memory array of a flash memory according to an embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view of the essential part of the semiconductor substrate, showing the method of manufacturing the memory array of the flash memory according to the embodiment of the present invention in the order of steps.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the memory array of the flash memory according to the embodiment of the present invention in the order of steps.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the memory array of the flash memory according to the embodiment of the present invention in the order of steps.

FIG. 8 is a graph showing coupling of memory cells in the flash memory according to the embodiment of the present invention.

FIG. 9 is a graph showing an interlayer capacitance of a memory cell of a flash memory which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a memory array of a flash memory according to another embodiment of the present invention.

FIG. 11 is a cross-sectional view of essential parts of a semiconductor substrate showing a memory array of a flash memory examined by the present inventor.

[Explanation of symbols]

1 semiconductor substrate 2 gate insulating film 3 conductor film 4 interlayer film 4a silicon nitride film 4b silicon oxide film 4c silicon nitride film 4d silicon oxide film 5 conductor film 6 cap insulating film 7S extended semiconductor region 7D extended semiconductor region 8 spacer 9S diffusion semiconductor region 9D Diffusion semiconductor region 10 Silicide film 11 Insulating film 12 Connection hole 13 Plug 14 Wiring 15 Interlayer film 15a Silicon nitride film 15b Silicon oxide film 15c Silicon nitride film 15d Silicon oxide film 15e Silicon nitride film 21 Semiconductor substrate 22S Semiconductor region 22D Semiconductor region 23 The gate insulating film 24 conductive film 25 interlayer film 25a silicon oxide film 25b silicon nitride film 25c silicon oxide film 26 conductive film MARY memory array MC ₁₁ memory cells MC ₁₂ memory cells MC ₂₁ memory cells MC ₂₂ memory cell W ₀ word line W ₁ word SB ₀ sub-bit line SB ₁ sub-bit line S source D drain SS local source line NWm n-well PWm p-well

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tetsuo Adachi             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Takashi Takeuchi             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 5F083 EP02 EP23 EP53 EP56 EP63                       EP68 EP77 ER22 GA01 JA04                       JA35 JA39 JA53 KA06 MA06                       MA19 NA01 PR40                 5F101 BA29 BA36 BB05 BD07 BD35                       BD36 BE07 BH05

Claims (4)

[Claims] 1. A process of forming a separation portion on a main surface of a semiconductor substrate; a process of forming a gate insulating film on a surface of the semiconductor substrate; and a process of forming a gate insulating film on the semiconductor substrate. 1
And (d) a silicon nitride film and a silicon oxide film are alternately stacked on the semiconductor substrate to form an interlayer film having a laminated structure. And (e) depositing a second conductor film on the semiconductor substrate, and (f) sequentially processing the second conductor film, the interlayer film and the first conductor film, A first gate composed of a first conductor film and the second gate;
And a step of forming a laminated gate having a second gate formed of the conductor film. 2. A step of: (a) forming a separation portion on the main surface of the semiconductor substrate; (b) a step of forming a gate insulating film on the surface of the semiconductor substrate; and (c) a first step on the semiconductor substrate. 1
And (d) forming a plurality of layers of a silicon nitride film and a silicon oxide film alternately on the semiconductor substrate with the lowermost layer and the uppermost layer being a silicon nitride film, A step of forming a film, (e) a step of depositing a second conductor film on the semiconductor substrate, and (f) a step of sequentially processing the second conductor film, the interlayer film and the first conductor film. And a step of forming a laminated gate including a first gate made of the first conductor film and a second gate made of the second conductor film. . 3. A semiconductor substrate having a plurality of non-volatile memory cells arranged in a matrix, the sources and drains of the plurality of non-volatile memory cells being connected to each other in parallel in each column, and a part of each row is partially formed in each row. A method of manufacturing a semiconductor device in which word lines forming control gates of the plurality of nonvolatile memory cells extend, comprising: (a) forming an isolation portion on a main surface of the semiconductor substrate; Forming a gate insulating film on the surface of the semiconductor substrate; and (c) depositing a first conductor film on the semiconductor substrate and processing the first conductor film in the gate width direction. d) a step of sequentially depositing a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film from the lower layer on the semiconductor substrate to form an interlayer film having a laminated structure,
(E) depositing a second conductor film on the semiconductor substrate, and (f) sequentially processing the second conductor film, the interlayer film, and the first conductor film along the gate length direction, A method of manufacturing a semiconductor device, comprising: forming a stacked gate having a floating gate made of the first conductor film and a control gate made of the second conductor film. 4. A semiconductor substrate having a plurality of non-volatile memory cells arranged in a matrix, the sources and drains of the plurality of non-volatile memory cells being connected in parallel to each other in each column, and a part of each row is partially formed in each row. A method of manufacturing a semiconductor device in which word lines forming control gates of the plurality of nonvolatile memory cells extend, comprising: (a) forming an isolation portion on a main surface of the semiconductor substrate; Forming a gate insulating film on the surface of the semiconductor substrate; and (c) depositing a first conductor film on the semiconductor substrate and processing the first conductor film in the gate width direction. d) A first silicon nitride film, a first silicon oxide film, a second silicon nitride film, a second silicon oxide film and a third silicon nitride film are sequentially deposited from the lower layer on the semiconductor substrate to form an interlayer film having a laminated structure. Forming process, (E) depositing a second conductor film on the semiconductor substrate, and (f) sequentially processing the second conductor film, the interlayer film, and the first conductor film along the gate length direction, A method of manufacturing a semiconductor device, comprising: forming a stacked gate having a floating gate made of the first conductor film and a control gate made of the second conductor film.