JP2003249570A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To mount MOS transistors having low-breakdown voltage characteristics and MOS transistors having high-breakdown voltage characteristics in a single chip without increasing the number of manufacturing processes. <P>SOLUTION: In a P-type semiconductor substrate (1), an N-type low- breakdown voltage MOS transistor forming region (2), a P-type low-breakdown voltage MOS transistor forming region (3), an N-type high-breakdown voltage MOS transistor forming region (4), and a P-type high-breakdown voltage MOS transistor forming region (5) are formed. When forming a P-type impurity layer (19) and an N-type impurity layer (11) in the N-type low-breakdown voltage MOS transistor forming region (2) and the P-type low-breakdown voltage MOS transistor forming region (3) respectively, a first N-type lightly-doped region (13) and a first P-type lightly-doped region (12) are formed simultaneously in the N-type high-breakdown voltage MOS transistor forming region (4) and the P-type high-breakdown voltage MOS transistor forming region (5) respectively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (LSI) in which a plurality of MOS transistors having different breakdown voltages are mixed.
And a manufacturing method thereof.

[0002]

2. Description of the Related Art FIGS. 6 to 8 are sectional views showing a conventional method of manufacturing a semiconductor device in which MOS transistors having different breakdown voltages are mounted in the same chip. As a conventional semiconductor device, for example, one in which four types of MOS transistors are mounted will be introduced. First, N-type low withstand voltage MO for low withstand voltage
S transistor formation region (102), P type low breakdown voltage MOS
A transistor formation region (103), a high breakdown voltage N-type high breakdown voltage MOS transistor formation region (104), and a P-type high breakdown voltage MOS transistor formation region (105) are arranged.

First step (see FIG. 6): Phosphorus P + and boron B + are ion-implanted at a predetermined position on a P-type semiconductor substrate (101), and a subsequent heat treatment is performed to form an N-type or P-type well region. It is formed. In the N-type low breakdown voltage MOS transistor formation region (102), the P-type well region (10
6) is formed. On the other hand, in the P-type low breakdown voltage MOS transistor formation region (103) and the P-type high breakdown voltage MOS transistor formation region (105), the N-type well region (10
7) are formed respectively.

Second step (see FIG. 7): After the first step, by selectively oxidizing a predetermined region of the semiconductor substrate (101), a LOCO for element isolation is provided between the above four regions.
An S oxide film (108) is formed. Then, LOCOS in the N-type high breakdown voltage MOS transistor formation region (104)
Boron B + is ion-implanted from above the oxide film (108) to form a P-type impurity region (109). This P
The type impurity region (109) is a LOCOS oxide film (10) inside the N-type high breakdown voltage MOS transistor formation region (104).
It is formed so as to be adjacent to the deepest part of 8) and functions as a channel stopper.

Next, boron B is introduced from above the P-type well region (106) and its surrounding LOCOS oxide film (108).
+ Is ion-implanted to form a P-type impurity layer (110). After that, similarly, phosphorus P is formed from above the N-type well region (107) and the LOCOS oxide film (108) around it.
Is ion-implanted to form an N-type impurity layer (111).

Third step (see FIG. 8): After the second step, 4
N-type low breakdown voltage MOS transistor formation region (102), P-type low breakdown voltage MOS transistor formation region (103), N-type high breakdown voltage MOS transistor formation region (104), and P-type high breakdown voltage MOS transistor formation region (105). 2), a gate electrode 112 is formed at a predetermined position on each substrate surface via a gate oxide film (not shown). At this time, there are two types of gate oxide films,
The film thickness is about 7 nm for low breakdown voltage and about 23 nm for high breakdown voltage. Then, using the gate electrode (112) as a mask in a self-aligned manner, a photoresist mask (not shown) is used to ion-implant phosphorus P + and boron difluoride BF ₂ +, respectively, to form an N-type low concentration region (113). And P-type low concentration regions (114) are formed respectively. The N-type low concentration region (113) is formed so as to have a predetermined depth in each of the N-type low breakdown voltage MOS transistor formation region (102) and the N-type high breakdown voltage MOS transistor formation region (104). Similarly, the P type low concentration region (114) is also P
Type low breakdown voltage MOS transistor formation region (103) and P
The high withstand voltage MOS transistor formation region (105) is formed to have a predetermined depth.

Then, using the sidewall spacer film (not shown) formed on the side wall of the gate electrode (112) and the gate electrode (112) as a mask, the N-type high-concentration region (113A) and the P-type high-concentration region are ionized. It is formed by injection. The sidewall spacer film (not shown) formed on the sidewall of the gate electrode (112) and the gate electrode (11)
2) Then, arsenic As + and boron difluoride BF ₂ + are ion-implanted using a photoresist mask (not shown) to form an N-type high-concentration region (115) and a P-type high-concentration region (116). At this time, the N-type high concentration region (1
The region 15) is formed deeper than the N-type low concentration region 113, and the P-type high concentration region 116 is formed deeper than the P-type low concentration region 114.

After the third step, a semiconductor device having MOS transistors having different withstand voltages is completed through a certain process up to resin molding.

In the conventional semiconductor device of the present application, the N-type low withstand voltage MOS transistor forming region (102) having a low withstand voltage and the P-type low withstand voltage MOS transistor forming region (103) have a withstand voltage of about 6V. A MOS transistor having the same is formed. In addition, the N-type high breakdown voltage MOS transistor formation region (104) having a high breakdown voltage and the P-type high breakdown voltage MOS transistor formation region (105) have about 1
A MOS transistor having a withstand voltage of about 1 V is formed.

[0010]

Among the various needs of LSI technology in recent years, a MOS transistor having a low withstand voltage characteristic (mainly 6 V or less) and a high withstand voltage characteristic (mainly 10 V or more) are required. There is one in which a MOS transistor is integrated in one chip. Under such circumstances, there is a natural need to integrate the above-mentioned MOS transistor having the low withstand voltage characteristic and the MOS transistor having the higher withstand voltage characteristic (mainly 15 V or more) into one chip. Is. However, the conventional example shown in FIG. 8 has a limit of about 11V even though it has a high breakdown voltage characteristic, and does not fully satisfy the need to mount a MOS transistor having a high breakdown voltage characteristic. As a method of satisfying these needs, it is possible to improve the high breakdown voltage characteristics by reducing the concentration difference between the source / drain and the semiconductor substrate (101) or each well region. However, it was an unavoidable fact that the manufacturing process had to be changed in order to reduce the density difference between the two, and in addition, the number of masks increased with the change. As a result, the cost of the manufacturing process increases, so that in the MOS transistor of the manufacturing process of the conventional example, a MOS transistor having a low withstand voltage characteristic (mainly 6 V or less) and a further high withstand voltage characteristic (mainly 15 V or more) is mounted together. However, there was a limit.

The present invention has been made in view of the above-mentioned drawbacks. A MOS transistor having a low withstand voltage characteristic (mainly 6 V or less) and a high withstand voltage characteristic (mainly 15 V or more) are provided without increasing the number of steps as compared with the prior art. And a MOS transistor having the same are mounted together in one chip.

[0012]

The present invention provides a first MOS
In a method of manufacturing a semiconductor device including a transistor and a second MOS transistor having a higher breakdown voltage than that of the first MOS transistor, at least the step of forming a source / drain region of the second MOS transistor includes A method of manufacturing a semiconductor device, which uses an ion implantation process other than an ion implantation process for forming a source / drain region of a first MOS transistor, and a semiconductor device obtained as a result. is there.

[0013]

1 to 3 are sectional views showing in chronological order the invention showing the manufacturing method according to the first embodiment of the present application. In all the drawings, (1) is a semiconductor substrate of one conductivity type, for example, P type, (2) is an opposite conductivity type, for example, N type low breakdown voltage MOS transistor formation region, (3) is P type low breakdown voltage MOS transistor formation region , (4) are N type high voltage MO
S transistor formation region, (5) P type high breakdown voltage MOS transistor formation region, (6) P type well region, (7)
Is an N-type well region, (8) is a LOCOS oxide film, (9)
Is a P-type impurity region as an inversion prevention layer in the N-type high breakdown voltage MOS transistor formation region, and (10) is the P-type impurity region.
A P-type impurity layer formed in the well region (6), (1
1) is an N-type impurity layer formed in the N-type well region (7) of the P-type low breakdown voltage MOS transistor formation region (3), and (12) is N of the P-type high breakdown voltage MOS transistor formation region (5). A first P-type low-concentration region formed in the well region (7), (13) a first N-type low-concentration region formed in the N-type high breakdown voltage MOS transistor forming region (4), (14) Is a photoresist mask, (15) is a gate electrode, (16) is a second N-type low-concentration region formed in the P-type impurity layer (10) and the N-type high breakdown voltage MOS transistor formation region (4), (17) is an N-type impurity layer (1
1) and P-type high breakdown voltage MOS transistor formation region (5)
A second P-type low-concentration region formed inside (18), a P-type impurity layer (10) and an N-type high-concentration region formed inside the N-type high breakdown voltage MOS transistor forming region (4), (19) )
Represents the P-type high concentration region formed in the N-type impurity layer (11) and the P-type high breakdown voltage MOS transistor formation region (5), respectively. Further, in all the drawings, the same components are designated by the same reference numerals. First step (see FIG. 1): P type with a concentration of 1.0 × 10
N type low breakdown voltage MOS transistor formation regions (2) and P are formed at predetermined positions of the semiconductor substrate (1) of ¹⁵ (cm ⁻³ ), respectively.
Type low breakdown voltage MOS transistor formation region (3), N type high breakdown voltage MOS transistor formation region (4), P type high breakdown voltage MO
A region for forming a MOS transistor, which is an S transistor formation region (5), is provided.

Then, a photoresist mask (not shown) having an opening is provided at a predetermined position on those surfaces,
Phosphorus P + and boron B + are ion-implanted to form an N-type or P-type well region. First, boron B + is ion-implanted into the N-type low breakdown voltage MOS transistor formation region (2), and phosphorus P + is implanted into the P-type low breakdown voltage MOS transistor formation region (3) and P-type high breakdown voltage MOS transistor formation region (5). Ion implantation. At this time, the condition for ion implantation of boron B + is that the implantation speed is 120 (Ke).
V) and the dose amount is 7.5 × 10 ¹² (pieces / cm ² ).
The phosphorus P + ion implantation condition is an implantation speed of 60.
(KeV) and the dose amount is 8.5 × 10 ¹² (pieces / cm ² ). Then, the ion-implanted boron and phosphorus ions are thermally diffused (1100 ° C., 6 hours) to form the P-type well region (6) and the N-type well region (7), respectively. At this time, the concentration of the P-type well region (6) becomes 2.0 × 10 ¹⁶ (cm ⁻³ ) and the concentration of the N-type well region (7) becomes 3.0 × 10 ¹⁶ (cm ⁻³ ).

In the present application, the order of ion implantation steps of phosphorus P + and boron B + may be reversed. Further, although the P type is used for the semiconductor substrate (1) in the present application, there is no problem even if the N type semiconductor substrate is used. In this case, the conductivity type opposite to that described above is adopted if necessary. Second step (see FIG. 2): After the first step, a LOCOS oxide film (8) is formed between the four regions by the LOCOS oxidation method.
And is used as a field oxide film for separating each region. At this time, the film thickness of the LOCOS oxide film is 450 to 550 nm. In the present application, an example of a LOCOS oxide film is given for element isolation, but another method (for example, forming a trench groove and filling the trench with an oxide film is referred to as STI) as long as it is a method for forming element isolation.
(Shallow trench isolation) method).

Thereafter, an N-type high breakdown voltage MOS transistor forming region (4) is formed by using a photoresist mask (not shown).
Immediately below the LOCOS oxide film (8), boron B + is implanted to form a P-type impurity region (9). The conditions of ion implantation are preferably such that the implantation speed is about 165 (KeV) and the dose amount is 4.0 × 10 ¹² (pieces / cm ² ).
The P-type impurity region (9) is formed so as to be adjacent to the deepest part of the LOCOS oxide film (8) inside the N-type high breakdown voltage MOS transistor formation region (4) and provided to function as a channel stopper. Is.

The feature of the present application is that ion implantation is performed in the N-type low breakdown voltage MOS transistor formation region (2) to form the P-type impurity layer (10), and at the same time, in the P-type high breakdown voltage MOS transistor formation region (5). In the first P-type low concentration region (1
2) is to be formed. Similarly, P-type low withstand voltage MOS
Ions are implanted into the transistor formation region (3) to form an N-type impurity layer (11), and at the same time, an N-type high breakdown voltage MO is formed.
A first N-type low concentration region (13) is formed in the S transistor formation region (4). Here, since the P-type impurity layer (10) and the first P-type low-concentration region (12) are formed at the same time, both have the same depth. Similarly, the N-type impurity layer (11) and the first N-type low concentration region (1
Since 3) is also formed at the same time, both have the same depth. The impurity concentration distribution (profile) will be described later with reference to FIG.

In FIG. 2, for example, after the P-type impurity layer (10) and the first P-type low concentration region (12) are simultaneously formed,
Forming a photoresist mask (14) on the substrate surface,
An opening is formed in the photoresist mask (14) at a desired position. Then, an N-type impurity is ion-implanted through the opening to form the N-type impurity layer (11) and the first N-type impurity layer.
The state where the mold low concentration region (13) is formed is shown.

In the present embodiment, the P-type impurity layer (1
0) and the first P-type low-concentration region (12) and the N-type impurity layer (11) and the first N-type low-concentration region (13) are simultaneously formed, they are continuously formed by using the same resist mask. Three-stage ion implantation is performed. Hereinafter, those conditions (order of ion implantation, implantation speed, dose amount) will be described in detail.

I) When the P-type impurity layer (10) and the first P-type low concentration region (12) are simultaneously formed.

Using a photoresist mask (not shown) as a mask, under the LOCOS oxide film (8) around the N-type low breakdown voltage MOS transistor formation region (2) and around the P-type high breakdown voltage MOS transistor formation region (5). In a predetermined region (formation region of the first P-type low concentration region (12)) of boron B + with an implantation speed of 140 (KeV) and a dose amount of 3.0 × 10 ¹² (cells / cm ² ). inject. The ion implantation process is for forming a channel stopper layer for preventing inversion just below the LOCOS oxide film (8) in the N-type low breakdown voltage MOS transistor formation region (2).

Thereafter, for the purpose of preventing punch-through of the N-type low breakdown voltage MOS transistor, the implantation speed of boron B + is 90 (KeV) and the dose amount is 9.
Ions are implanted under the condition of 0 × 10 ¹² (pieces / cm ² ).

Thereafter, for the purpose of adjusting the Vt (threshold value) of the substrate surface of the N-type low withstand voltage MOS transistor, boron fluoride BF ₂ is implanted at a speed of 35 (Ke).
V) and the dose amount is 3.8 × 10 ¹² (pieces / cm ² ).

II) When the N-type impurity layer (11) and the first N-type low concentration region (13) are formed simultaneously.

Using the photoresist mask (14) as a mask, under the LOCOS oxide film (8) in the P-type low breakdown voltage MOS transistor formation region (3) and its periphery, and the N-type high breakdown voltage M.
P-type low withstand voltage M in the OS transistor formation region (4)
For the purpose of adjusting the Vt (threshold value) of the substrate surface of the OS transistor, the implantation speed of arsenic As is 40 (K
eV) and the dose amount is 6.0 × 10 ¹² (pieces / cm ² ).

After that, phosphorus P + is used for the purpose of preventing punch-through of the P-type low withstand voltage MOS transistor.
The implantation speed is 140 (KeV) and the dose is 3.0
Ion implantation is performed under the condition of × 10 ¹² (pieces / cm ² ).

Thereafter, divalent phosphorus P + is used for the purpose of a channel stopper for forming the P-type low withstand voltage MOS transistor.
The implantation speed of + is 260 (KeV), and the dose amount is 5.
Ions are implanted under the condition of 0 × 10 ¹² (pieces / cm ² ) (double charge method).

By the above ion implantation step I), the concentration of the P-type impurity layer (10) and the first P-type low concentration region (12) becomes 3.0 × 10 ¹⁷ . Also, the ion implantation step I
From I), the concentration of the N-type impurity layer (11) and the first N-type low concentration region (13) is 2.0 × 10 ¹⁷ (cm ⁻³ ). The present application does not particularly limit the order of the ion implantations I) and II). Further, although the present application discloses that three ion implantation steps for threshold adjustment, punch-through prevention, and channel stopper formation are sequentially performed, only one or two of these ion implantation steps are performed. But there is no problem. For example, it is a case where only the ion implantation step for adjusting the threshold value is performed, or a case where the ion implantation steps for punch-through prevention and channel stopper formation are performed. Third step (see FIG. 3): After forming a gate oxide film (not shown) on the surface of the substrate, a gate electrode (15) is formed at a predetermined position on the gate oxide film. At this time, there are two types of gate oxide films, with a film thickness of about 7 nm for low breakdown voltage and about 23 nm for high breakdown voltage. The gate electrode (1
Using 5) as a mask, the N-type low breakdown voltage MOS transistor formation region (2), the P-type low breakdown voltage MOS transistor formation region (3), the N-type high breakdown voltage MOS transistor formation region (4), and the P-type high breakdown voltage MOS transistor formation region (5)
The second N-type low concentration region (16) and the second P
The low mold concentration regions (17) are formed respectively. At this time,
Phosphorus P + is ion-implanted under the conditions of a implantation speed of 30 (KeV) and a dose amount of 3.0 × 10 ¹³ (pieces / cm ² ),
The implantation speed of boron difluoride BF ₂ + is 25 (Ke
V) and the dose amount is 1.6 × 10 ¹³ (pieces / cm ² ). The concentration of the second N-type low concentration region (16) is 1.0 × 10 ¹⁸ (cm ⁻³ ), and the concentration of the second P-type low concentration region (17) is 1.0 × 10 ¹⁸ (cm ^{−). 3} ) The second N-type low-concentration region (16) and the second P-type low-concentration region (17) become a low-concentration N-type source / drain region and a P-type source / drain region.

After that, an oxide film (not shown) is formed so as to cover the gate electrode (15), the oxide film is anisotropically etched, and sidewall spacer films are formed on both sides of the gate electrode (15). Form. Then, using a photoresist mask (not shown) and using the sidewall spacer film and the gate electrode (15) as a mask, arsenic A
s + and boron difluoride BF ₂ + are respectively ion-implanted to form an N-type high concentration region (18) and a P-type high concentration region (19).
Are formed to have a predetermined depth. At this time, arsenic As + is implanted at a rate of 40 (KeV) and the dose is 4.4 × 10 ¹⁵ (pieces / cm ² ), and boron difluoride BF ₂ + is implanted at a rate of 35.
(KeV), the dose amount is 2.2 × 10 ¹⁵ (pieces / cm ² ).
Ion implantation is performed under the conditions of. The concentration of the N-type high concentration region (18) is 1.0 × 10 ²⁰ (cm ⁻³ ), and the concentration of the P-type high concentration region (19) is 1.0 × 10 ²⁰ (cm ⁻³ ).

As a result of the above, the formed N-type high concentration region (18) and P-type high concentration region (19) are the second N-type low concentration region (16) and the second P-type low concentration region (17). 2) is formed so that the deepest part thereof becomes shallower than the above), and becomes a high-concentration N-type source / drain region and a P-type source / drain region.

In this embodiment, in the N-type high breakdown voltage MOS transistor formation region (4), the second N-type low concentration region (16) is formed only on one of the source and drain sides. That is, when the side on which the first N-type low concentration region (13) is formed is the drain side, the second N-type low concentration region (16) is formed only on the source side. Therefore, the first N-type low concentration region (13) and the second N-type low concentration region (16) do not overlap. Similarly, in the P-type high breakdown voltage MOS transistor formation region (5), the second P-type low concentration region (17) is formed only on one of the source and drain sides. That is, when the side on which the first P-type low concentration region (12) is formed is the drain side, the second P-type low concentration region (17) is formed only on the source side. Therefore, the first P-type low concentration region (12) and the second P-type low concentration region (17) do not overlap.

In this embodiment, the high-concentration N-type high-concentration region (18) is completely buried in the low-concentration first N-type low-concentration region (13), and the low-concentration first P-type region (18) is formed. Low concentration area (1
A high-concentration P-type high-concentration region (19) is completely embedded in 2). In this embodiment, the second N-type low concentration region (16) and the second P-type low concentration region (13) and the first P low-concentration region (12) are formed on the substrate surface. You may form a low concentration area | region (17).

From the above, the concentration of each diffusion region will be described. The first N type low concentration region (13) and the first P low concentration region (12) have the lowest concentration, and the N type high concentration region ( 1
8) and the P-type high concentration region (19) have the highest concentration. The concentration of the second N-type low concentration region (16) and the second P-type low concentration region (17) on the substrate surface is between these two.

After the third step, a semiconductor device having MOS transistors having different withstand voltages is completed through a certain process up to resin molding. FIG. 4 is a sectional view showing the invention showing the manufacturing method according to the second embodiment of the present application. Moreover, FIG. 4 shows the first embodiment (FIG. 3).
FIG. 3 is an enlarged view of a range including an N-type high breakdown voltage MOS transistor formation region (4) and a P-type high breakdown voltage MOS transistor formation region (5). The difference between this embodiment and the first embodiment of the present application is that the first P-type low concentration region (12) and the first N-type low concentration region (13) formed in the second step are For example, not only the drain side) but also the other side (for example, the source side) is formed. This is based on the assumption that a high breakdown voltage is required not only on the drain side but also on both sides of the source / drain.

As shown in FIG. 4, the first N-type low-concentration region (13) and the first P-type low-concentration region (12) are predetermined by non-self-alignment as in the first embodiment. After being formed at the position, the gate electrode (15) is formed through the gate oxide film.
Is formed at a predetermined position. Then, after forming a sidewall spacer film on both side walls of the gate electrode (15),
Using the spacer film and the gate electrode (15) as a mask,
The N-type high-concentration region (18) and the P-type high-concentration region (19) are used as the first N-type low-concentration region (13) and the first P-type low-concentration region (12), respectively, by using self-alignment. It is formed so as to be completely buried. Incidentally, also in the second embodiment of the present application, the second N-type low concentration region (16) and the second P-type low concentration region (17) of the source / drain are formed as in the first embodiment of the present application. It also includes the case where ions are implanted on both sides or only one of them.

FIG. 5 is a view showing the impurity concentration distribution (profile) in the cross section of the channel region in the N-type low breakdown voltage MOS transistor formation region (2) and the P-type low breakdown voltage MOS transistor formation region (3) of the present application. is there. The vertical axis represents the impurity concentration, and the horizontal axis represents the depth from the substrate surface. Figure 5
As shown in FIG. 3, three-step peak values are formed, and the reference values are A, B, and C, respectively, from the side closer to the substrate surface. Since the range of the peak value indicated by the symbol A is formed mainly near the substrate surface, the purpose is mainly to adjust the Vt (threshold value) on the substrate surface. Of the three stages of ion implantation in the above-mentioned second process, the following applies. The range of the peak value indicated by the symbol B is mainly intended to prevent punch through. Of the three stages of ion implantation in the above-mentioned second process, the following applies. The range of the peak value indicated by the symbol C is mainly intended to function as a channel stopper. Of the three stages of ion implantation in the above-mentioned second process, the following applies.

In the semiconductor chip mounting the MOS transistor manufactured through the above process, according to the results of experiments conducted by the inventor of the present application, N-type and P-type high breakdown voltage MO
It was confirmed that the breakdown voltage characteristics in the S transistor formation regions (4) and (5) were improved to about 17V.

[0038]

As described above, in the present application, low withstand voltage characteristics (mainly 6V or less) and high withstand voltage characteristics (mainly 10V) can be obtained by simply changing the shape of the photoresist mask without increasing the number of steps as compared with the prior art. It is possible to separately manufacture MOS transistors each having a higher withstand voltage characteristic (mainly 15 V or more), and even if all or some MOS transistors are required to be combined in a single chip. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the invention.

FIG. 2 is a cross-sectional view showing the manufacturing method of FIG.

FIG. 3 is a cross-sectional view showing the manufacturing method of FIG.

FIG. 4 is an enlarged cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the invention.

FIG. 5 is an impurity concentration distribution according to the semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.

7 is a cross-sectional view showing the manufacturing method of FIG.

FIG. 8 is a cross-sectional view showing the manufacturing method of FIG.

Claims (14)

[Claims] 1. A first MOS transistor and the first MOS transistor.
Second MO having a higher breakdown voltage than the MOS transistor of
In the method of manufacturing a semiconductor device including an S transistor, the step of forming the source / drain region of the second MOS transistor is an ion implantation step for forming at least the source / drain region of the first MOS transistor. A method for manufacturing a semiconductor device, wherein the ion implantation process other than the above is diverted. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the source / drain regions of the second MOS transistor is a step of forming low-concentration source / drain regions. . 3. The step of forming a source / drain region of the second MOS transistor is a step of forming only a low-concentration drain region.
A method for manufacturing a semiconductor device as described above. 4. The ion implantation process other than the ion implantation process for forming the source / drain region of the first MOS transistor is performed at least for threshold adjustment, punch-through prevention, and channel stopper of the first MOS transistor. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising one of the ion implantation steps for forming. 5. A method of manufacturing a semiconductor device having a reverse conductivity type transistor formation region for low breakdown voltage and a conductivity type transistor formation region for high breakdown voltage, and a reverse conductivity type transistor formation region for high breakdown voltage on a conductivity type semiconductor substrate, Forming one conductivity type well region in the low withstand voltage reverse conductivity type transistor forming region and forming a reverse conductivity type well region in the low breakdown voltage one conductivity type transistor forming region; Reverse conductivity type impurities are ion-implanted into the well region and the surface layer of the high breakdown voltage reverse conductivity type transistor formation region to form a reverse conductivity type impurity layer in the reverse conductivity type well region, Forming a low-concentration reverse-conductivity-type drain region in a predetermined region of the reverse-conductivity-type transistor forming region, and forming a gate electrode after forming a gate insulating film on the substrate. Forming a low concentration one conductivity type source / drain region by ion-implanting one conductivity type impurity into the surface layer of the opposite conductivity type impurity layer using the gate electrode as a mask. And a step of forming a low concentration reverse conductivity type source / drain region by ion-implanting a reverse conductivity type impurity into a surface layer of the high breakdown voltage reverse conductivity type transistor formation region, and a sidewall on both side wall portions of the gate electrode. After forming the spacer film, using the gate electrode and the sidewall spacer film as a mask, one conductivity type impurity is ion-implanted into a predetermined region of the surface layer of the opposite conductivity type impurity layer to form a high concentration one conductivity type source / drain. A step of forming a region, and an impurity of a reverse conductivity type is ion-implanted into the surface layer of the one conductivity type impurity layer and the reverse breakdown type transistor forming region for high breakdown voltage to form a high concentration reverse conductivity type. And a step of forming a conductive type source / drain region. 6. A step of forming a low-concentration reverse-conductivity type source / drain region by ion-implanting a reverse-conductivity type impurity into the surface layer of the one-conductivity-type impurity layer and the reverse breakdown type transistor forming region for high breakdown voltage. 6. The semiconductor device according to claim 5, further comprising a step of forming a source region and a drain region in the one conductivity type impurity layer, and forming only a source region side in the opposite conductivity type transistor formation region. Production method. 7. A method of manufacturing a semiconductor device having a reverse-conductivity-type transistor formation region for low breakdown voltage and a conductivity-type transistor formation region for high breakdown voltage, and a conduction-type transistor formation region for high breakdown voltage on a conductivity-type semiconductor substrate, One conductivity type well region is formed in the low withstand voltage reverse conductivity type transistor forming region, and first and second conductive regions are formed in the low withstand voltage one conductivity type transistor forming region and the high withstand voltage one conductivity type transistor forming region. A second opposite conductivity type well region,
And a step of forming an impurity of one conductivity type in the surface layer of the one conductivity type well region and the one conductivity type transistor formation region for high breakdown voltage, and one conductivity type impurity in the one conductivity type well region. Forming a layer and forming a low-concentration one-conductivity type drain region in a predetermined region of the one-conductivity-type transistor forming region for high breakdown voltage; and forming a gate electrode after forming a gate insulating film on the substrate. Forming a low-concentration reverse-conductivity type source / drain region by ion-implanting a reverse-conductivity-type impurity into the surface layer of the one-conductivity-type impurity layer using the gate electrode as a mask; Forming a low-concentration one-conductivity type source / drain region by ion-implanting one-conductivity type impurity into the surface layer of the impurity layer and the one-conductivity type transistor forming region for high breakdown voltage; After forming a sidewall spacer film on both side wall portions of the electrode, an impurity of opposite conductivity type is ion-implanted into a predetermined region of the surface layer of the one conductivity type impurity layer using the gate electrode and the sidewall spacer film as a mask. Forming a high-concentration reverse-conductivity type source / drain region; and ion-implanting a single-conductivity-type impurity into the surface layer of the reverse-conductivity-type impurity layer and the second reverse-conductivity-type well region. And a step of forming a source / drain region. 8. The step of forming a low-concentration one-conductivity type source / drain region by ion-implanting one-conductivity type impurities into the surface layers of the first and second reverse-conductivity type well regions is performed. 8. The method of manufacturing a semiconductor device according to claim 7, which is a step of forming only the source region side in the conductivity type well region. 9. A one-conductivity-type semiconductor substrate has a low-breakdown-voltage reverse-conductivity-type transistor formation region and a one-conductivity-type transistor formation region, and a high-breakdown-voltage reverse-conductivity-type transistor formation region and one-conductivity-type transistor formation region. In the method for manufacturing a semiconductor device, a one-conductivity type well region is formed in the low-breakdown-voltage reverse-conductivity-type transistor forming region, and the low-breakdown-voltage one-conductivity-type transistor forming region and the high-breakdown-voltage one-conductivity-type transistor are formed. First and second opposite conductivity type well regions in the formation region,
In the first reverse-conductivity-type well region by ion-implanting a reverse-conductivity-type impurity into a surface layer of the first reverse-conductivity-type well region and the high breakdown voltage reverse-conductivity-type transistor forming region. Forming a reverse conductivity type impurity layer and forming a low concentration reverse conductivity type drain region in a predetermined region of the high breakdown voltage reverse conductivity type transistor formation region; An impurity of one conductivity type is ion-implanted into the surface layer of the second well region of the opposite conductivity type to form an impurity layer of one conductivity type in the well region of the one conductivity type, and a transistor of one conductivity type for high breakdown voltage is formed. Forming a low-concentration one-conductivity-type drain region in a predetermined region of the region; forming a gate electrode after forming a gate insulating film on the substrate; and using the gate electrode as a mask to form the one-conductivity region. -Type impurity layer and a step of forming a low-concentration reverse-conductivity type source / drain region by ion-implanting a reverse-conductivity-type impurity into a surface layer of the high-voltage reverse-conductivity-type transistor formation region, and the reverse conductivity-type impurity layer and Forming a low concentration one conductivity type source / drain region by ion-implanting one conductivity type impurity into the surface layer of the second opposite conductivity type well region; and forming a sidewall spacer film on both side walls of the gate electrode. After the formation, using the gate electrode and the sidewall spacer film as a mask, the opposite conductivity type impurities are ion-implanted into the surface layer of the one conductivity type impurity layer and the reverse conductivity type transistor forming region for the high breakdown voltage so as to have a high concentration. Forming a reverse-conductivity type source / drain region, and ion-implanting a single-conductivity-type impurity into the surface layer of the reverse-conductivity type impurity layer and the second reverse-conductivity type well region. Method of manufacturing a semiconductor device characterized by being a step of forming a one conductivity type source and drain regions of concentration. 10. The step of forming the first reverse-conductivity-type low-concentration region and the first one-conductivity-type low-concentration region includes the source side and the drain side in the high-voltage reverse-conductivity-type transistor forming region. And a step of forming the first reverse conductivity type low concentration region on both sides, and the first one conductivity type low concentration on both the source side and the drain side in the high breakdown voltage one conductivity type transistor formation region. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming a region. 11. A semiconductor substrate of one conductivity type, a reverse conductivity type low withstand voltage MOS transistor forming region, a one conductivity type low withstand voltage MOS transistor forming region, and a reverse conductivity type high withstand voltage MOS transistor forming region formed on the semiconductor substrate. A gate electrode formed at a desired position on the semiconductor substrate, a well region of one conductivity type in the reverse conductivity type low breakdown voltage MOS transistor formation region, and a reverse conductivity type well in the one conductivity type low breakdown voltage MOS transistor formation region A region, one conductivity type impurity layer in the one conductivity type well region, and a reverse conductivity type impurity layer in the reverse conductivity type well region; and a reverse conductivity type of the reverse conductivity type in the one conductivity type impurity layer. Semiconductor device having one-conductivity-type impurity layer and reverse-conductivity-type low-concentration region and high-concentration region in the reverse-conductivity-type high-voltage MOS transistor formation region on their surface layers In the reverse conductivity type high breakdown voltage MOS transistor formation region,
A semiconductor device having a reverse-conductivity-type low-concentration region having the same concentration and the same depth as the reverse-conductivity-type impurity layer. 12. A one-conductivity-type semiconductor substrate, a reverse-conductivity-type low-breakdown-voltage MOS transistor forming region formed on the semiconductor substrate, a one-conductivity-type low-breakdown-voltage MOS transistor forming region, and a one-conductivity-type high-breakdown-voltage MOS transistor forming region. A gate electrode formed at a desired position on the semiconductor substrate, a well region of one conductivity type in the reverse conductivity type low withstand voltage MOS transistor forming region, and a first reverse electrode in the one conductivity type low withstand voltage MOS transistor forming region. Conductive type well region and the one conductive type high breakdown voltage MOS
A second opposite conductivity type well region in the transistor formation region; a first conductivity type impurity layer in the first conductivity type well region; a second conductivity type impurity layer in the first opposite conductivity type well region; The one conductivity type impurity layer has an opposite conductivity type, the opposite conductivity type impurity layer has one conductivity type, and the second opposite conductivity type well region has one conductivity type low concentration region and high concentration region. In a semiconductor device provided on a surface layer, a semiconductor of one conductivity type low concentration region having the same concentration and the same depth as the one conductivity type impurity layer is formed in a second opposite conductivity type well region. apparatus. 13. A semiconductor substrate of one conductivity type, a reverse conductivity type low breakdown voltage MOS transistor formation region formed on the semiconductor substrate, a one conductivity type low breakdown voltage MOS transistor formation region, a reverse conductivity type high breakdown voltage MOS transistor formation region, A one-conductivity-type high-breakdown-voltage MOS transistor forming region; a gate electrode formed at a desired position on the semiconductor substrate; one-conductivity-type well region in the reverse-conductivity-type low-breakdown-voltage MOS transistor forming region; A first reverse conductivity type well region in a MOS transistor formation region, and the one conductivity type high breakdown voltage MOS
A second opposite conductivity type well region in the transistor formation region; a first conductivity type impurity layer in the first conductivity type well region; a second conductivity type impurity layer in the first opposite conductivity type well region; The conductivity type impurity layer has an opposite conductivity type, the opposite conductivity type impurity layer has one conductivity type, the opposite conductivity type high withstand voltage MOS transistor formation region has an opposite conductivity type, and the second opposite conductivity type well region has an opposite conductivity type. A semiconductor device of one conductivity type having a low-concentration region and a high-concentration region on respective surface layers thereof, wherein:
An opposite conductivity type low concentration region having the same concentration and the same depth as the opposite conductivity type impurity layer is formed, and has the same concentration and the same depth as the one conductivity type impurity layer in the second opposite conductivity type well region. A semiconductor device comprising a low-concentration region of one conductivity type. 14. The first reverse conductivity type low concentration region is formed on both the source side and the drain side in the high breakdown voltage reverse conductivity type transistor formation region, and the high breakdown voltage single conductivity type transistor is formed. 14. The semiconductor device according to claim 13, wherein the first one conductivity type low concentration region is formed on both the source side and the drain side in the region.