JP2003249568A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which does not bring about performance deterioration of any of high- and low-voltage transistors formed on a single substrate. <P>SOLUTION: The method comprises steps of: forming a first and second conductor patterns on first and second element forming regions of a first conductivity semiconductor substrate, respectively; introducing first conductivity ions into the first element forming regions through a mask layer formed over the second element forming regions and the first conductor pattern used as a mask; forming sidewalls on the first and second conductor patterns; introducing the second conductivity ions and second conductivity ions having diffusion coefficient higher than those into the first element forming regions through the conductor patterns and the sidewalls used as masks; and thermally diffusing the introduced ions. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element operating at a predetermined operating voltage and a semiconductor element operating at an operating voltage lower than the operating voltage of the semiconductor element, which are simultaneously formed on the same semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device, which is capable of sufficiently exhibiting the performance of both the semiconductor elements.

[0002]

2. Description of the Related Art A semiconductor device such as an IC, which is an assembly of semiconductor elements such as MOSFET, generally incorporates two types of semiconductor elements having different operating voltages. For example, in Japanese Patent Laid-Open No. 11-330267,
A technique for incorporating a low-voltage field effect transistor, that is, a low-voltage transistor, and a high-voltage field effect transistor, that is, a high-voltage transistor, into a single substrate is disclosed. In the prior art, in order to solve the problem caused by applying the impurity regions of the same impurity concentration for the source and drain of each of the low voltage transistor and the high voltage transistor, the impurity region of the low voltage transistor is It has been proposed to form an impurity region having a low concentration or an intermediate concentration thereof as an extension region.

[0003]

However, according to the above-mentioned conventional technique, the pair of impurity regions of the low-voltage transistor and the high-voltage transistor have impurities of a conductivity type opposite to that of the semiconductor substrate. A first impurity region exhibiting a predetermined impurity concentration, and a first impurity region extending from the first impurity region toward the respective gates, exhibiting the same conductivity type as the first impurity region, and having a concentration of the first impurity region. A second impurity region exhibiting a lower impurity concentration, and the setting of the second impurity region is set to be suitable for electric field relaxation of the high voltage transistor, this setting allows The effective gate length of the low voltage transistor is shortened, and the low voltage transistor causes a short channel effect. On the other hand, if the second impurity region is set so that the low-voltage transistor does not cause the short channel effect, with this setting, the high-voltage transistor cannot obtain a sufficient electric field relaxation effect, Therefore, a hot carrier effect is brought about in the high voltage transistor.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which can be efficiently manufactured without causing a deterioration in performance of both the high voltage transistor and the low voltage transistor formed on a single substrate. To provide.

[0005]

The present invention adopts the following constitution in order to solve the above points. A method of manufacturing a semiconductor device according to the present invention includes a first element formation region and a second element formation region of a first conductivity type semiconductor substrate having a first element formation region and a second element formation region. Forming a first conductor pattern and a second conductor pattern respectively on the regions, and forming a mask layer on the second element forming region, the mask layer and the first conductor pattern A step of introducing ions of the first conductivity type into the first element formation region using the mask as a mask;
And forming a sidewall on the second conductor pattern, and using the first and second conductor patterns and the sidewall as a mask, the first and second
A first ion of the second conductivity type and a second ion of the second conductivity type and having a diffusion coefficient larger than that of the first ion into the element formation region of And a step of thermally diffusing the second ion and the second ion.

The first element formation region and the second element formation region can be electrically separated from each other by an insulating film.

Furthermore, ions of the second conductivity type can be introduced into the first element formation region by using the mask layer and the first conductive pair pattern as a mask.

The first conductor pattern is used for a gate electrode of a first transistor, the second conductor pattern is used for a gate electrode of a second transistor, and the gate of the first transistor is used. The length can be shorter than the gate length of the second transistor.

The ions of the first conductivity type can be introduced under the conductor pattern by introducing them with a predetermined inclination with respect to the surface of the semiconductor substrate.

Further, using the mask layer formed on the second element region and the first conductor pattern as a mask, ions of the second conductivity type are formed in the vicinity of the surface of the semiconductor substrate in the first element formation region. Can be introduced.

The embodiments of the present invention will be described below with reference to specific examples. <Specific Example 1> FIGS. 1A to 1F show a manufacturing process of a semiconductor device 10 according to the present invention. 1A to 1
In (f), an n-type channel MOSFET, that is, a low-voltage transistor 12 provided on a semiconductor substrate 11 having a first conductivity type, for example, a p-type conductivity type, and operating at a predetermined voltage, and the semiconductor substrate 11 above. , A process for efficiently manufacturing a semiconductor device including a high voltage transistor 13 which is provided in the high voltage transistor 13 and which operates at a voltage higher than the operating voltage of the transistor 12 is shown.

As shown in FIG. 1A, a gate length of, for example, about 0.25 μm for the low voltage transistor 12, which is the first transistor, is formed on a semiconductor substrate 11 made of a p-type silicon crystal substrate. And a gate 14 for the second transistor, the high-voltage transistor 13, having a gate length of, for example, about 0.35 μm.
And are simultaneously formed using, for example, well-known photolithography and etching techniques. As is well known in the art, each gate 14 has a semiconductor substrate 1
1, a gate insulating film 15 formed on the active region and a gate electrode 16 formed on the insulating film 15.
The active region is partitioned by an insulating film such as a field oxide film formed by the LOCOS method.
And a second element formation region. A well-known multilayer structure can be adopted for each gate electrode 16, that is, each of the first and second conductor patterns.

Gate 1 of both transistors 12 and 13
After the formation of No. 4, the active region of the high-voltage transistor 13, that is, the second element formation region, including its gate 14, is covered with a mask not shown. As shown in FIG. 1B, in the active region for the low-voltage transistor 12 exposed from the mask, that is, in the first element formation region, the gate 14 for the transistor 12 is used as a mask, and For example, boron 17 having the same p-type conductivity type as that of the semiconductor substrate 11 is implanted at a predetermined depth position in a direction substantially perpendicular to the semiconductor substrate 11 by an ion implantation method. As an example of implantation conditions, the boron is about 2.0 × 10 ¹³ / c at an acceleration voltage of 20 keV.
It was injected at a concentration of m ² .

As shown in FIG. 1C, after the boron 17 is introduced into the active region of the transistor 12 of the semiconductor substrate 11, the drain current between the source and drain of the low voltage transistor 12 is reduced. Arsenic 18 for increasing the flow rate is implanted into the active region of the transistor 12 by ion implantation while leaving the mask covering the active region of the high voltage transistor 13 left. The arsenic 18 is shallower than the boron 17 and is implanted without extending from the boron 17 in the gate direction. As an example of implantation conditions, the arsenic 18 is 10 ke
It was injected at a accelerating voltage of V and a concentration of about 1.0 × 10 ¹⁵ cells / cm ² . When introduced into the semiconductor substrate 11, the arsenic 18 acts as an n-type impurity of the second conductivity type.

After the arsenic 18 is introduced into the active area of the transistor 12, the mask covering the active area of the high voltage transistor 13 is removed.

After removal of the mask, gate 1 of the low voltage transistor 12 is shown in FIG. 1 (d).
4 and the gate 14 of the high-voltage transistor 13, a pair of sidewalls 19 made of an insulating material sandwiching each gate from both sides thereof is formed by a well-known method.

After the formation of the side wall 19, FIG.
As shown in (e), each transistor 12
Using the gate 14 and the sidewalls 19 for 13 and 13 as a mask, phosphorus 20 is simultaneously implanted on both sides thereof by an ion implantation method. The phosphorus 20 is introduced shallower than the introduction region of the boron 17 introduced for the low voltage transistor 12 and without being extended in the gate direction beyond the boron 17. As a result, the introduction regions of the phosphorus 20 for the low-voltage transistor 12 are such that the introduction regions are spaced apart from each other, and the side surfaces facing each other and the bottom surface extending continuously to the side surfaces have the conductivity type of the previously introduced phosphorus. The boron 17 is to be covered with the introduction region of the boron 17 having a different conductivity type. As an example of the phosphorus injection condition, the phosphorus 20 is about 5.0 × 10 at an acceleration voltage of 30 keV.
The concentration was ¹³ / cm ² .

After implanting the phosphorus 20 into each of the transistors 12 and 13, arsenic 21 for source / drain is formed.
(Refer to FIG. 6F) shows the transistor 12 as a first ion using the gate 14 and the sidewall 19 for the transistors 12 and 13 as a mask.
And 13 are simultaneously implanted by the ion implantation method. As an example of implantation conditions, the arsenic 21 (see FIG. 1 (f)
Is about 5.0 × 10 ¹⁵ at an acceleration voltage of 50 keV.
It was injected at a concentration of pcs / cm ² .

Then, in order to activate each impurity introduced into the active region of the semiconductor substrate 11, each impurity introduced region of the semiconductor substrate 11 is subjected to a collective heat treatment. Due to this heat treatment, the impurities 17, 18, 20 and 21 introduced into the transistors 12 and 13 are introduced.
Therefore, as shown in FIG. 1F, the impurity 21 forms the first impurity region 21 and has a diffusion coefficient larger than that of the impurity 21. The impurity 20 implanted as the second ion forms a second impurity area 22, the impurity 17 forms a third impurity area 23, and the impurity 18 forms the first impurity area 21.
The extended portion 24 is formed.

Arsenic 21 of each transistor 12 and 13
The pair of first impurity regions 21 formed by the above functions as a well-known source and drain. In relation to the source / drain of the low voltage transistor 12, the pair of extension portions 24 formed by the arsenic 18 are
This serves to increase the flow rate of the drain current.

Since the pair of second impurity regions 22 formed by the phosphorus 20 of the high voltage transistor 13 are sufficiently extended in the directions close to each other due to the thermal diffusion of the phosphorus 20 in the heat treatment described above, By the impurity region 22 of 2,
The electric field between the source and drain is relaxed, and the hot carrier effect can be suppressed.

On the other hand, the pair of second impurity regions 22 formed by the phosphorus 20 of the low voltage transistor 12 have the conductivity type opposite to that of the introduction region of the phosphorus 20 defining the regions as described above. Surrounded by boron 17. Therefore, the side surfaces facing each other of the introduction region of the phosphorus 20 are regulated by the boron 17 covering the side surfaces so that the heat diffusion in the directions approaching each other at the time of the heat treatment is performed. as a result,
In the low-voltage transistor 12, the execution channel length is prevented from being shortened, and thus the short channel effect is prevented, so that the threshold value of the gate voltage is prevented from lowering due to the short channel effect. Further, in the low voltage transistor 12, the pair of second impurity regions 2 formed by the phosphorus 20 is formed.
Since the boron 2 is restricted from extending in the direction toward each other by the boron 17, the effect of increasing the flow rate of the drain current by the extending portion 24 is not impaired by the impurity region 22.

In the low-voltage transistor 12, the third impurity region 23 covers the lower surfaces of the pair of second impurity regions 22 extending continuously from the facing side surfaces of the second impurity region 22. Are prevented from being formed in a deep portion of the semiconductor substrate 11, and
More effectively suppress the short channel effect.

Therefore, according to the above-described manufacturing method of the present invention, it is possible to increase the flow rate of the drain current of the low-voltage transistor 12 and suppress the occurrence of the short channel effect thereof, and to prevent hot carriers in the high-voltage transistor 13. Since the generation of the effect can be suppressed, the transistor 1 that exhibits excellent electrical characteristics without sacrificing the electrical characteristics of the transistors 12 and 13 is provided.
The semiconductor device 10 including 2 and 13 can be efficiently formed without increasing the number of mask processing steps.

<Specific Example 2> In the specific example 1 shown in FIG.
The example in which the side surface and the bottom surface of the second impurity region 22 of the low-voltage transistor 12 are covered with the third impurity region 23 is shown. As an alternative to this example, as shown in FIG. 2, only the side surface of the second impurity region 22 of the low-voltage transistor 12 can be covered with the third impurity region 23. The impurities for the impurity regions 23 of 3 shown in the specific example 2 are introduced by the ion implantation method from the oblique direction.

The low voltage transistor 12 included in the semiconductor device 10 of the second specific example is the same as that of the first specific example except that the impurity is introduced for the third impurity section 23. Low voltage transistor 1 on substrate 11
2, a gate 14 having a gate insulating film 15 and a gate electrode 16 for 2, a sidewall 19, and an extension 24.
A first impurity region 21 having a
2 and a third impurity zone 23. Although the high voltage transistor is omitted in FIG. 2 for simplification of the drawing, this high voltage transistor has the same configuration as the high voltage transistor 13 shown in FIG.

The impurities for the third impurity region 23 provided in the low voltage transistor 12 are the gate 1
4 on both sides of the substrate 11 from the upper side of the substrate 11 in an oblique direction approaching each other. The impurities for the third impurity region 23 introduced by this oblique ion implantation method are introduced so as to project in a direction closer to each other than the impurities in the third impurity region 23 of the first specific example.

Therefore, in the example shown in the second specific example, compared to the first specific example in which the ion implantation method is performed almost perpendicularly to the semiconductor substrate 11, the third impurity regions 23 are moved toward each other. It can be formed so as to greatly overhang. By introducing the impurities for the third impurity region 23 by the oblique ion implantation method, as in Example 1, the second impurity region 22 of the second impurity region 22 can be formed without sacrificing the electrical characteristics of the high voltage transistor. It is possible to more reliably prevent the execution channel length from being shortened due to heat treatment diffusion, and it is possible to more reliably prevent the threshold voltage of the low-voltage transistor 12 from lowering.

Although the method of forming the n-type channel semiconductor device on the semiconductor substrate showing the p-type conductivity type has been described above, instead of this, a semiconductor substrate showing the n-type conductivity type is used. , P-channel semiconductor devices can be formed in the same manner as described above.

In the above description, the impurities for the third impurity region, the impurities for the extension part, the second impurity,
The method for forming the semiconductor device by collectively activating the impurities by heat treatment after introducing the impurities for the impurity areas and the impurities for the first impurity areas has been described. Although the semiconductor device can be formed by appropriately changing the order of introducing each impurity and the order of heat treatment for activation, the third heat treatment is performed before the heat treatment of impurities for the second impurity region. The introduction of impurities for the impurity zone in place must be observed.

[0031]

As described above, in the method of manufacturing a semiconductor device according to the present invention, when forming the pair of impurity regions for the low-voltage semiconductor element and the high-voltage semiconductor element, the first low-voltage semiconductor element is formed. Thermal diffusion in the second impurity region having an impurity concentration lower than that of the impurity region of the third impurity region has a conductivity type opposite to that of the third impurity region.
Of the third impurity region, even if the impurity implantation for the second impurity region is set to suit the characteristics of the high-voltage semiconductor device.
Due to the diffusion prevention effect of the impurity region, the electrical characteristics of the low-voltage semiconductor element are not impaired.

Therefore, according to the manufacturing method of the present invention, each semiconductor element can be efficiently provided on a single semiconductor substrate without causing deterioration in performance of either the low-voltage semiconductor element or the high-voltage semiconductor element. Can be formed.

Further, according to the semiconductor device formed by the method according to the present invention, the drain current of the low-voltage semiconductor element can be increased by the extension of the first impurity region in the low-voltage semiconductor element. And the third
Since the impurity region of the second impurity region prevents unnecessary diffusion of the second impurity region, it is possible to suppress the occurrence of a short channel effect due to this unnecessary diffusion, while the second impurity region of the high voltage semiconductor device is Since the optimum setting is made to alleviate the electric field in the high-voltage semiconductor element, it is possible to effectively suppress the generation of hot electrons by the electric field alleviating action in the second impurity region of the high-voltage semiconductor element, It is possible to prevent the deterioration of electrical characteristics due to the generation of hot electrons.

[Brief description of drawings]

FIG. 1 is a process drawing showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view partially showing another semiconductor device manufactured by the manufacturing method according to the present invention.

[Explanation of symbols]

10 Semiconductor device 11 Semiconductor substrate 12 Low voltage transistor 13 High voltage transistor 14 gates 15 Gate insulation film 16 gate electrode 17 Areas where boron is introduced 18 Area where arsenic is introduced 19 Sidewall 20 Area where phosphorus is introduced 21 First Impurity Zone 22 Second Impurity Zone 23 Third Impurity Zone 24 Extension

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F048 AC01 BA01 BB03 BC05 BC06                       BC18 BD04 BG12 DA23                 5F140 AA06 AA21 AB01 BA01 BF01                       BF11 BG08 BH13 BH14 BH15                       BH36 BK02 BK10 BK21 CB01                       CF00

Claims (6)

[Claims] 1. A first conductivity type semiconductor substrate having a first element formation region and a second element formation region is provided with a first element formation region and a second element formation region, respectively. Forming a conductor pattern and a second conductor pattern, respectively, and forming a mask layer on the second element forming region, and using the mask layer and the first conductor pattern as a mask, A step of introducing ions of a first conductivity type into the first element formation region; a step of forming a sidewall on the first and second conductor patterns; a step of forming the first and second conductor patterns and the side; With the wall as a mask, first ions of the second conductivity type and second ions of the second conductivity type and having a diffusion coefficient larger than that of the first ions are formed in the first and second element formation regions. With ion A method of manufacturing a semiconductor device, comprising: a step of introducing; and a step of thermally diffusing the first ions and the second ions. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first element formation region and the second element formation region are electrically separated from each other by an insulating film. Of manufacturing a semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a second layer in the first element formation region using the mask layer and the first conductive pair pattern as a mask.
A method of manufacturing a semiconductor device, comprising a step of introducing conductive type ions. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductor pattern is used for a gate electrode of a first transistor, and the second conductor pattern is a second transistor. Used for the gate electrode of the first transistor, wherein the gate length of the first transistor is shorter than the gate length of the second transistor. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the ions of the first conductivity type are introduced with a predetermined inclination with respect to the surface of the semiconductor substrate,
A method of manufacturing a semiconductor device, characterized in that the semiconductor device is introduced under the conductor pattern. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising forming the first element using the mask layer and the first conductor pattern formed on the second element region as a mask. A method of manufacturing a semiconductor device, comprising the step of introducing ions of the second conductivity type into a region near the surface of the semiconductor substrate.