JP2003248704A - Semiconductor integrated circuit design verification method and layout tool - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily verity the restriction for burn-in examination of a wafer level in a design stage of a single chip. <P>SOLUTION: This method includes a floor plan process 100, a process 101 for placing the layouts same as that of the verified chip, in adjacent to upper, lower, left and right parts of the layout of the verified chip, a process 103 for reading a design tool by the restriction of the wafer level burn examination, and a process 104 for verifying a design rule. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design verification method and layout tool capable of verifying constraints in a wafer level burn-in test (WLBI).

[0002]

2. Description of the Related Art A wafer-level burn-in test responds to a demand for reducing the test cost of a semiconductor integrated circuit (LSI), which is increasing in scale, and a demand for reliability guarantee for a bare chip used in a multi-chip module or a chip-on-board. Has been adopted as a product and is expected to be expanded in the future.

[0003]

However, in order to perform the burn-in inspection at the wafer level, the layout of the input / output terminals of the LSI chip may be restricted by the adjoining chips on the wafer. In the past, such constraint verification had to be performed by the designer himself by extracting the coordinates at the stage of determining the floor plan.

As a problem at the time of development for performing a wafer-level burn-in inspection, a complicated input / output terminal arrangement that satisfies the wafer-level burn-in inspection constraint (WLBI constraint) due to the use of input / output terminal pitch and filler cells in the process. It can be mentioned. Therefore, there is a high possibility that the WLBI constraint will be violated only by paying attention to the layout of the chip itself, and if a mistake is found in the post-process of development, there is a risk of delaying development.

The present invention solves the above-mentioned conventional problems, and WLB for performing a wafer level burn-in inspection.
An object of the present invention is to provide a design verification method and a layout tool for a semiconductor integrated circuit, which makes it possible to easily verify the I constraint at the design stage of a single chip.

[0006]

In order to solve this problem, a semiconductor integrated circuit design verification method according to a first aspect of the present invention is a semiconductor integrated circuit design verification method using a layout tool. Floorplanning process (10
0), a step of arranging the same layout as the layout of the chip to be verified so as to be adjacent to the layout of the chip to be verified vertically and horizontally (101), and a step (103) of reading the design rule due to the constraint of the wafer level burn-in inspection. And the step of verifying the design rule (1
04) and are included.

According to the above configuration, it is possible to reproduce the state in which the chips to be verified are arranged on the wafer by using the layout tool, and by reading the design rule of the WLBI constraint as the design rule, the layout tool Since the design rule check can be used, the design rule due to the restriction of the wafer level burn-in inspection can be easily verified at the design stage of a single chip.

A semiconductor integrated circuit design verification method according to a second aspect of the present invention is the semiconductor integrated circuit design verification method according to the first aspect, wherein the coordinate information of the input / output terminal portion shape is extracted from the layout of the chip to be verified. This includes the step (1002) of performing.

According to the above configuration, since the design rule can be checked by using the coordinate information of the input / output terminal portion shape extracted from the layout of the chip to be verified, the wafer level burn-in inspection is automatically performed from the layout of the chip to be verified. It is possible to verify design rules based on constraints.

A semiconductor integrated circuit design verifying method according to a third aspect of the present invention is the semiconductor integrated circuit design verifying method according to the first or the second aspect, in accordance with a plurality of restrictions on a pad portion in a wafer level burn-in test. This includes a step (802) of arbitrarily adding or changing the pattern layer of the pad portion.

According to the above configuration, by using a plurality of pattern layers according to a plurality of constraints, the layout of the chip to be verified for performing the wafer level burn-in inspection includes a constraint other than the design rule of the WLBI constraint. It is possible to easily verify design rules based on multiple constraints at the design stage of a single chip.

According to a fourth aspect of the present invention, there is provided a layout tool for a semiconductor integrated circuit, wherein a floorplanning means and a layout which is the same as the layout of the chip to be verified are arranged adjacent to each other vertically and horizontally to the layout of the chip to be verified. Means, a means for reading the design rule due to the restriction of the wafer level burn-in inspection, a means for extracting coordinate information of the shape of the input / output terminal portion from the layout of the chip to be verified, and a means for verifying the design rule. Is.

According to the above configuration, the state in which the chip to be verified is placed on the wafer can be reproduced, and the design rule of the WLBI constraint is read as the design rule, so that the input extracted from the layout of the chip to be verified is read. Since the design rule can be checked by using the coordinate information of the shape of the output terminal portion, the design rule due to the constraint of the wafer level burn-in inspection can be easily verified at the design stage of a single chip.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a flowchart showing a method of design verification of a semiconductor integrated circuit according to Embodiment 1 of the present invention. In the present embodiment, by executing the design verification method shown in FIG. 1 using a layout tool, the design rule by the constraint of the wafer level burn-in test (the design rule for the WLBI constraint) is applied to the layout of the chip to be verified. To verify.

In the flowchart of FIG. 1, first, in step 100, a floor plan of the chip to be verified is implemented.
In step 102, a WLBI constraint design rule is prepared. Next, in step 101, the same layout as the layout of the chip to be verified is arranged adjacent to the top, bottom, left and right of the layout of the chip to be verified. As a result, the chips to be verified have the same conditions as when they are placed on the wafer. Then, in step 103, the design rule for WLBI constraint is read, and in step 104, verification for the WLBI constraint is performed.

Next, a method of arranging the same layout as the layout of the chip to be verified in step 101 adjacent to the layout of the chip to be verified in the vertical and horizontal directions, respectively,
This will be described with reference to FIGS. 2 to 4.

FIG. 2 is a layout diagram of the chip to be verified. In FIG. 2, the chip boundary 200 corresponds to a normal scribe lane layer. An input / output terminal area 203 is provided around the chip core, and input / output terminals are arranged in this area. The WLBI target input / output terminal 201 exists in the input / output terminal, and is subject to the input / output terminal restriction between chips on the wafer.

FIG. 3 is a layout diagram when the chips are arranged on the wafer. When manufacturing this LSI,
As described above, the chips 301 are arranged on the wafer 300. In the present invention, for the chip of FIG. 2 created by the layout tool, the state of being placed on the wafer as shown in FIG. 3 is reproduced to verify the WLBI constraint.

FIG. 4 shows the result of actually arranging the same layout as the chip of FIG. 2 adjacent to the layout of the chip of FIG. To do this, using the X coordinate on the horizontal axis and the Y coordinate on the vertical axis shown in FIG. 4, the lower left vertex of the chip boundary is set as the origin coordinate (0, 0) for the layout 400 of the chip to be verified, and , The chip size coordinate (X, Y) of the upper right vertex indicating the chip size is extracted.

Next, the extracted chip size coordinates (X,
The layout 40 of the chip to be verified is calculated using the X component of Y).
0 is translated in parallel by (−X, 0) to obtain the layout 401 of the reproduced chip adjacent to the left side of the verification target chip. Similarly, using the Y component of the chip size coordinate (X, Y),
The layout 400 of the chip to be verified is moved in parallel by (0, −Y), and the layout 4 of the reproduced chip adjacent to the lower side is arranged.
Get 02.

In the same manner, the layout 400 of the chip to be verified is moved in parallel by (X, 0) to obtain the layout 403 of the reproduction chip adjacent to the right side, and the layout 400 of the chip to be verified is (0, Y). By parallel translation to obtain the layout 404 of the reproduction chip adjacent to the upper side.

In this way, the chip 400 to be verified can be reproduced in the same state as when it was actually placed on the wafer. Here, an area 405 where the input / output terminal area of the layout 400 of the verification target chip and the input / output terminal area of the reproduction chip arranged adjacent to each other in the upper, lower, left and right directions is a target portion for verifying the WLBI constraint.

FIG. 5 is an enlarged view of a WLBI target input / output terminal 201 which is a target of input / output terminal restriction between chips on a wafer. In the input / output terminal 501, a pad section 500 is provided.
Exists. The center coordinates of the pad section 500 are referred to as pad section center coordinates 502. There are various methods for setting the design rule by the WLBI constraint, but here, it is assumed that the WLBI constraint is verified by using the center coordinates of the pad portion.

FIG. 6 is a flow chart showing a processing procedure for extracting the pad center coordinates. The layout data of the pad section is extracted in advance. In the flowchart of FIG. 6, an input / output terminal area is extracted in step 600. This input / output terminal area is the input / output terminal area 203 in FIG. Next, in step 601, the pad area is extracted. This pad area is the pad area 5 in FIG.
00.

Next, in step 602, the vertex coordinates of the pad portion are extracted, and in step 603, the coordinates where both X and Y are maximum and minimum are extracted. Using this value, in step 604 the midpoint of the extracted coordinates is calculated. In step 605, this midpoint is stored as the WLBI midpoint coordinate.

FIG. 7 shows steps 602 to 605 of FIG.
FIG. 7 is a coordinate diagram illustrating a process of extracting the center coordinates of the pad portion up to. In FIG. 7, 700 is a search coordinate (X,
Y) and 701 are pad area. In step 602, coordinates (lower left) 702, coordinates (lower right) 703, coordinates (upper right) 704, coordinates (upper left) 705 are extracted.

With respect to the extracted coordinates, the coordinates in which both X and Y are maximum and minimum are extracted. In the case of FIG. 7, the minimum coordinates are coordinates (lower left) 702 and the maximum coordinates are coordinates (upper right) 704. The midpoint of the coordinates is calculated from these two coordinates. As a result, the obtained coordinates become the midpoint coordinates of the pad portion and are stored as the midpoint coordinates of WLBI.

As a result, for the WLBI constraint verification location 405 shown in FIG. 4, the WLB midpoint coordinates stored in the process of extracting the pad center coordinates in FIG.
I Calculate the distance between the target pads. The calculated value is WLB
The presence or absence of the WLBI constraint violation is verified by comparing with the I constraint. As described above, according to the present embodiment, it is possible to verify the WLBI constraint using the layout tool.

(Embodiment 2) In addition to the WLBI constraint, there are constraints such as an assembly rule as a constraint of the pad layout of the LSI, and generally there are a plurality of constraints in the layout. Therefore, even if the pad layout satisfies the WLBI constraint, for example, if the assembly rule constraint is not satisfied, the layout study is performed again.

FIG. 8 is a flow chart showing a method for verifying the design of a semiconductor integrated circuit according to the second embodiment of the present invention, which is devised for verifying such a plurality of constraints.
In the present embodiment, by executing the design verification method shown in FIG. 8 using the layout tool, the layout of the chip to be verified to be subjected to the wafer level burn-in inspection includes constraints other than the WLBI constraint design rule. And verify the design rule with multiple constraints.

In the flowchart of FIG. 8, first, in step 800, the floor plan of the chip to be verified is implemented.
Next, in step 801, similarly to FIG. 4 in the first embodiment, the same layout as the layout of the chip to be verified is arranged adjacent to each other vertically and horizontally to the layout of the chip to be verified. As a result, the chips to be verified have the same conditions as when they are placed on the wafer.

Next, in step 802, the pad distance of the chip to be verified is extracted with respect to the pads in the left, right, top, and bottom chips arranged in step 801. Also, step 803
The design rule for constraint verification is changed in, and the design rule including multiple pad constraints to be verified is verified.

FIG. 9 is a diagram showing a layout example in which a plurality of pad layers are added in the step 802. In FIG. 9, reference numeral 901 denotes a pad layer pad that is verified for constraint 1, and 902 is a pad layer pad that is verified for constraint 2. Although 901 and 902 are different layers, they are displayed in an overlapping manner in FIG. 9.

In this way, different layers are allocated and prepared corresponding to a plurality of pad constraints. Then, in step 804, the pad constraint verification according to a plurality of design rules can be performed at once by performing the constraint verification according to the design rule of each pad constraint for each layer. As described above, according to the present embodiment, it is possible to verify a plurality of constraints including the WLBI constraint using the layout tool.

(Third Embodiment) FIG. 10 is a flowchart showing the processing steps of a layout tool for a semiconductor integrated circuit according to a third embodiment of the present invention. The processing of this layout tool will be described below with reference to the flowchart of FIG.

In step 1000, the floor plan of the chip to be verified is implemented by means of the floor plan, and step 1
In 001, the same condition as that when the chip to be verified is arranged on the wafer is realized by the means for arranging the same layout as the layout of the chip to be verified adjacent to the layout of the chip to be verified vertically and horizontally.

In step 1002, the pad coordinate information to be verified by the WLBI constraint is extracted by the means for extracting the coordinate information of the shape of the input / output terminal portion from the layout of the chip to be verified, and in step 1003, it is determined by the wafer level burn-in inspection constraint. By means of reading design rules, WL
Prepare a BI constraint design rule, and in step 1004,
The WLBI constraint is verified by the means for verifying the design rule.

Usually, in using the layout tool, the design rule for each process is read before the layout, and the layout is performed so as to satisfy this design rule. Furthermore, by checking the design rule of the layout tool after the layout is completed, it is verified whether the layout satisfies the design rule. On the other hand, the present invention realizes a method for verifying the WLBI constraint by loading the design rule for WLBI constraint as a design rule after the floor plan is implemented and using the design rule check of the layout tool.

[0039]

As described above, according to the present invention,
The layout tool can be used to reproduce the state in which the chip to be verified is placed on the wafer, and the design rule check of the layout tool can be used to check the design rule of the WLBI constraint. It is possible to obtain an excellent effect that it becomes possible to easily verify the design rule due to the inspection constraint at the design stage of the single chip.

Furthermore, according to the present invention, by using a plurality of pattern layers according to a plurality of constraints, the layout of the chip to be verified for performing the wafer level burn-in inspection is restricted other than the design rule of the WLBI constraint. It is possible to obtain an excellent effect that it becomes possible to easily verify a design rule including a plurality of constraints at the design stage of a single chip including the above.

[Brief description of drawings]

FIG. 1 is a flowchart showing a design verification method for a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of a verification target chip.

FIG. 3 is a layout diagram when chips are arranged on a wafer.

FIG. 4 is a layout diagram in which the same layout is arranged vertically and horizontally adjacent to the layout of the chip to be verified.

FIG. 5 is a diagram of input / output terminals subject to WLBI constraints.

FIG. 6 is a flowchart showing a processing procedure for extracting pad center coordinates.

FIG. 7 is a coordinate diagram illustrating a process of extracting pad unit center coordinates.

FIG. 8 is a flowchart showing a semiconductor integrated circuit design verification method according to a second embodiment of the present invention.

FIG. 9 is a layout diagram showing a layout example in which a plurality of pad layers are added.

FIG. 10 is a flowchart showing processing steps of a layout tool for a semiconductor integrated circuit according to a third embodiment of the present invention.

[Explanation of symbols]

100 floor plan process 101 placement process 102 rule preparation process 103 Rule reading process 104 Rule verification process 200 chip boundary 201 WLBI target input / output terminal 202 chip core 203 Input / output terminal area 300 wafers 301 chips 400 Chip to be verified 401, 402, 403, 404 Reproduction chip 405 WLBI constraint verification points 500 pad section 501 input / output terminal 502 Pad center coordinates 600 Input / output terminal area extraction process 601 Pad area extraction process 602 vertex coordinate extraction process 603 Maximum / minimum coordinate extraction process 604 Midpoint calculation process 605 Coordinate storage process 700 Search coordinates (X, Y) 701 pad area 702, 703, 704, 705 coordinates 800 floor plan process 801 placement process 802 Pad layer addition process for each constraint 803 Constraint design rule change process 804 Constraint verification process 901 Constraint 1 verification target pad 902 Constraint 2 verification target pad 1000 floor plan process 1001 placement process 1002 WLBI target coordinate extraction step 1003 Rule reading process 1004 Design rule check process

Claims (4)

[Claims] 1. A method for verifying the design of a semiconductor integrated circuit using a layout tool, comprising: a step of performing a floor plan; A method for verifying the design of a semiconductor integrated circuit, comprising: a step of arranging the semiconductor integrated circuit and a step of reading a design rule due to a constraint of a wafer level burn-in inspection; 2. The method of design verification of a semiconductor integrated circuit according to claim 1, further comprising a step of extracting coordinate information of an input / output terminal portion shape from the layout of the chip to be verified. 3. The semiconductor integrated circuit according to claim 1, further comprising a step of arbitrarily adding or changing a pattern layer of the pad portion in accordance with a plurality of constraints on the pad portion in the wafer level burn-in inspection. Design verification method. 4. A means for performing a floor plan, a means for arranging the same layout as the layout of the chip to be verified adjacent on the top, bottom, left and right of the layout of the chip to be verified, and a design rule due to the restriction of the wafer level burn-in inspection. A layout tool for a semiconductor integrated circuit, comprising: a reading unit, a unit for extracting coordinate information of input / output terminal portion shape from the layout of the chip to be verified, and a unit for verifying the design rule.