JP2003243368A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the reliability of dry etching. SOLUTION: For a conductive film deposited on a wafer,
In a step of performing a plasma dry etching process using the photoresist pattern formed on the conductive film as an etching mask, a change start point A to a change end point B of a light emission waveform of a desired wavelength detected from plasma during the dry etching process. By monitoring continuously, the uniformity of the etching rate of the film to be etched in the surface to be etched is measured, and the optimum value of the etching amount of the film to be etched is determined based on the uniformity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effectively applied to an etching technique in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art In a dry etching process, it is important to know the optimum value of the etching amount because the selectivity is poor as compared with the wet etching process. As a method of grasping the optimum value of the etching amount, there is a method of detecting a predetermined emission spectrum from plasma in the etching processing chamber, for example. For example, when an aluminum-based conductor film is etched by a dry etching method using a chlorine-based gas, sharp light emission with a wavelength of 396.1 nm corresponding to the atomic spectrum of aluminum is recognized in the light emission from plasma. By monitoring this light emission through a spectroscope, it is possible to detect the time when the aluminum-based conductor film disappears and grasp the optimum value of the etching amount. As a method that the present inventor has examined for this type of technology, there is, for example, the following method. That is, in the first technique, only the point of the change start time or the change end time of the emission waveform from the plasma is monitored to obtain the optimum value of the etching amount. In the second technique, the cross-sectional shape of a predetermined pattern is actually confirmed for each product, and the optimum etching amount is obtained. Further, the third technique measures the etching rate to obtain the optimum value of the etching amount.

The technique for detecting the etching end point is described, for example, in "LSI Handbook" p432-p433, published by Ohmsha Co., Ltd., November 30, 1984, and a spectroscopic analysis method and a laser beam interference method are disclosed. ing.

[0004]

However, in the above technique for grasping the optimum etching amount, the etching rate in the main surface of the wafer is not dependent on the in-plane position of the wafer, the pattern condition or the flatness of the wafer. There is a problem that the uniformity is not fully considered. For example, the etching rate differs between the center and the outer periphery of the wafer, and the outer periphery of the wafer has a higher etching rate than the center of the wafer. Further, in the pattern sparse region where the patterns are sparse and the pattern dense region where the patterns are dense, the pattern sparse region has a higher etching rate. Therefore, there is a problem that insufficient etching occurs at a low etching rate and excessive etching occurs at a high etching rate. In the first technique examined by the inventor, since only the point of the change start time or the change end time is monitored, it is not possible to grasp the uniformity of the etching rate within the wafer surface. Further, in the second technique, even if the actual pattern cross section after etching of the pattern sparse region and the pattern dense region is observed, it is possible to make a judgment only from the result of the observed pattern, and it is possible to confirm in a wide field of view. It may not be possible to overlook it. In addition, in the third measurement of the etching rate, the etching rate changes between the pattern sparse region and the pattern dense region, and therefore an accurate determination cannot be made.

An object of the present invention is to provide a technique capable of improving the reliability of etching.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, the film to be etched in the surface to be etched is etched by continuously monitoring the change start time to the change end time of the emission waveform of the desired wavelength detected from the plasma during etching. It has a step of measuring the uniformity of the speed and grasping the optimum value of the etching amount of the film to be etched based on the measurement.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In the following embodiments, when there is a need for convenience, description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are unrelated to each other. However, one of them is in a relationship of a modification, details, supplementary explanation, etc. of a part or all of the other.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.) of elements, it is clearly limited to a specific number when explicitly stated and in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless explicitly stated or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., except when explicitly stated and when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included or similar. This also applies to the above numerical values and ranges.

In all the drawings for explaining the present embodiment, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

Further, in this embodiment, a MIS • FET (Metal Insula) representing a field effect transistor is used.
tor Semiconductor Field Effect Transistor) MI
Abbreviated as S, p-channel type MIS • FET is abbreviated as pMIS, and n-channel type MIS • FET is abbreviated as nMIS.

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) The present inventor, for example, when forming a wiring pattern by plasma dry etching (hereinafter, also simply referred to as etching) for a product having a large difference in the density of the wiring pattern in the surface to be etched. When the etching conditions were set, a short circuit failure occurred due to insufficient etching in the pattern dense region. It was found that this is because the etching amount was insufficient in the pattern dense region having a slow etching rate due to the difference in etching rate between the pattern sparse region and the pattern dense region. At this time, the present inventor has confirmed that the emission waveform observed from the plasma has a long change time of emission due to the film to be etched and disappears and is gradually attenuated. From this, the present inventor has found that the uniformity of the etching rate can be obtained from the time from the start of the change of the emission waveform to the end of the change, and the optimum value of the etching amount can be accurately obtained.

FIG. 1 shows an emission waveform of a desired wavelength selectively obtained from plasma when a conductor film (film to be etched) is patterned by a plasma dry etching process. The horizontal axis represents time and the vertical axis represents voltage. The symbol A indicates the change start point. The waveform gradually attenuates (tilts to the right) at the boundary of the change start point A, and progresses in a direction in which etching is gradually finished. The symbol B indicates a change end point. The change end point indicates the time point when etching is completely completed (the stage where the patterns to be processed are completely insulated). The symbol C indicates the time zone from the change start point A to the change end point B.

In the first embodiment, the emission waveform of such a desired wavelength is continuously monitored. In particular, the change start point to the change end point in this light emission waveform are continuously monitored, the difference in etching rate between the maximum etching rate and the minimum etching rate of the conductor film is measured from the slope in the time period C, and The uniformity of the etching rate of the conductor film is measured from the etching rate difference, and the optimum value of the etching amount of the conductor film is grasped based on the measured uniformity.

FIG. 2 shows a detailed explanatory view of FIG. The time period C in which the light emission waveform is attenuated is a set (time t) at which etching is completed (etching completion time).
1, t2, t3 ... tn). For example, the time when the output voltage of the light emission waveform changes by ΔV (V) is aggregated as data. Where etching rate (ER)
Is calculated by ER = thickness of film to be etched (T) / processing time (t), the etching rate from the start of change of the emission waveform to the end of change is the etching rate at time t1 (ER1) = T / t1 (that is, maximum etching rate (ERmax) = etching rate at waveform change start time), etching rate at time t2 (E
R2) = T / t2, ... Etching rate (ERn) at tn = T / tn (that is, minimum etching rate (ERmin) = etching rate at waveform change end time). And the average value of etching rate (ERave)
Is ERave = (ER1 + ER2 + ... + ERn) /
n = ((T / t1) + (T / t2) + ... + (T / t
n)) / n = T / tave (tave: time at average etching rate). Where tave = n / ((1
/T1)+(1/t2)+...+(1/tn)).

Further, assuming that the thickness (T) of the film to be etched is uniform and constant in the wafer surface, the uniformity (Uni) of the etching rate is Uni = ((ERmax
−ERmin) / (ERave × 2)) × 100 = (((1 /
t1)-(1 / tn)) / ((1 / tave) × 2)) ×
100 = (((1 / t1)-(1 / tn)) /
((((1 / t1) + (1 / t2) + ... + (1 / t
n)) / n) × 2)) × 100. This equation can be used to monitor the uniformity of the wafer etch rate during wafer processing. In FIG. 3, the waveform gradually attenuates from the change start point to the change end point of the emission waveform, and the uniformity of the etching rate is ± 1 at the waveform end time of 100 seconds.
The case where a warning message is generated when it becomes 0% or more is illustrated.

As described above, according to the first embodiment, the etching amount is obtained by using the data obtained by measuring the emission waveform of the desired wavelength detected during the actual etching. Even in the case where a large etching rate difference occurs in the surface, a more optimal etching amount for the object to be etched can be obtained. Further, although the difference in pattern density and the in-plane flatness of the wafer are different for each product, according to the first embodiment, since the optimum etching amount can be obtained for each product, the reliability is high for each product. The etching process becomes possible. Further, by detecting the abnormality of the etching uniformity, it is possible to detect the fluctuation of the etching characteristics and also to generate the warning message of the defect occurrence. Further, it is possible to easily analyze the cause of the defect occurrence. For example, if a defect occurs even though only the etching apparatus is different and the other conditions are the same, it can be determined that there is a problem on the etching apparatus side. As described above, according to the first embodiment, the reliability of the etching process can be improved. In particular, in a semiconductor device, as the pattern becomes finer, the uniformity of the etching rate has an increasing influence on the pattern size and the opening uniformity, and further on the device performance and the yield. By using it in the device manufacturing process, it becomes possible to improve the yield, performance and reliability of the semiconductor device.

Next, a specific example of the method of manufacturing the semiconductor device according to the first embodiment will be described.

In the first embodiment, for example, the uniformity of the etching rate in the wafer surface of the film to be etched is measured by using a dummy wafer formed to have the same pattern shape as the product wafer, and the measurement result is obtained. A case will be described in which the etching conditions for the etching process of the product wafer are set on the basis of the above, and the etching process is performed on the film to be etched of the product wafer.

FIG. 4 shows a sectional view of the main part of the dummy wafer 1DW. The left side of FIG. 4 illustrates the pattern sparse region of the dummy wafer 1DW, and the right side of FIG. 4 illustrates the same pattern dense region of the dummy wafer 1DW as the left side of FIG. Further, FIG. 5 shows an enlarged cross-sectional view of a main part of the dummy wafer of FIG. A semiconductor substrate (hereinafter, simply referred to as a substrate) 1DS of the dummy wafer 1DW is made of, for example, single crystal silicon (Si), and a conductor film 3 is deposited on its main surface via an insulating film 2a. The conductor film 3 includes, for example, a conductor film 3a made of a metal nitride film such as titanium nitride and a conductor film 3b made of a metal film such as aluminum or an aluminum alloy (for example, aluminum-silicon-copper alloy) on the conductor film 3a. Further, a laminated conductor film having a structure in which a conductor film 3c made of a metal nitride film such as titanium nitride is further laminated thereon. A photoresist pattern 4a having a desired planar shape (hereinafter, simply referred to as a resist pattern) 4a is formed on the conductor film 3.

Subsequently, using the resist pattern 4a as an etching mask, a plasma dry etching process using a chlorine (Cl) -based gas such as Cl ₂ or BCl ₃ is performed to expose the resist pattern 4a. The conductor film 3 (3c to 3a) is removed by etching. As the dry etching device, for example, a microwave plasma dry etching device was used. However, the present invention is not limited to this, and various changes can be made. For example, a parallel plate type plasma dry etching apparatus may be used.

FIG. 6 shows a cross-sectional view of the main part of the dummy wafer 1DW after this dry etching process. The left side of FIG. 6 is the same area as the left side of FIG. 4, and the right side of FIG. 6 is the same area as the right side of FIG. Further, FIG. 7 shows an enlarged cross-sectional view of a main part of the dummy wafer 1DW of FIG. A dummy wiring pattern 5da made of the conductor film 3 is formed by the etching process. The optical waveforms obtained during this dry etching process are shown in FIGS. 8 and 9.
FIG. 8 shows an optical waveform obtained by monitoring light with a wavelength of 419.0 nm corresponding to, for example, the emission spectrum of TiCl in order to detect the etching amount of the conductor films 3a and 3c made of titanium nitride or the like. . FIG. 9 shows, for detecting the etching amount of the conductor film 3b made of aluminum or the like, for example, 396.1 nm corresponding to the emission spectrum of AlCl.
The optical waveform obtained by monitoring the light of the wavelength is shown. In either case, the entire emission waveform, especially the change starting point A
The change points B1 to B3 are continuously monitored from 1 to A3. From these detection results, in each of the conductor films 3a to 3c, the etching rate difference between the maximum etching rate and the minimum etching rate is measured from the slopes of the time zones C1 to C3, and the conductor film conductor films 3a to 3c are determined from the etching rate difference.
In each of the above, the uniformity of the etching rate in the wafer surface was measured, and based on that, the conductor film conductor films 3a to 3
The optimum value of the etching amount in each of c is grasped. These emission waveforms are monitored as follows. That is,
The light generated in the processing chamber of the dry etching apparatus during the dry etching is sent to the monochromator through the optical fiber cable attached to the dry etching apparatus, and only the light having a desired wavelength is selectively detected. The light of the desired wavelength selected through the monochromator is converted into an electric signal through the photoelectric conversion device, and the above emission waveform can be obtained. In the first embodiment, since the light in the processing chamber is detected in a state in which the entire main surface of the wafer is photographed, the light detecting section of the optical fiber cable may be provided at one place, and the structure of the detecting section can be simplified. Therefore, the cost of the dry etching apparatus can be reduced.

Next, FIG. 10 shows a sectional view of a main part of the product wafer 1W. The left side of FIG. 10 illustrates a pattern sparse region of the product wafer 1W, and the right side of FIG. 10 illustrates a pattern dense region of the same product wafer 1W as the left side of FIG. The enlarged cross-sectional view of the main part of FIG. 10 at this time is the same as FIG.

The substrate 1S of the wafer 1W for this product is made of, for example, single crystal silicon (Si), and the main surface (device surface) of the substrate 1S has a groove-type isolation portion (SGI (Shallo).
w Groove Isolation) or STI (Shallow Trench I
solation)) 6 is selectively formed. The groove-type separation portion 6 is formed by, for example, embedding a silicon oxide film in the groove formed on the main surface of the substrate 1S. Although a groove-shaped separation portion is illustrated here, the separation portion may be formed of a silicon oxide (SiO ₂ or the like) film by, for example, a LOCOS (Local Oxidization of Silicon) method.

In addition, the substrate 1S has the main surface from the main surface thereof.
A p-type well PWL and an n-type well NWL are selectively formed over a predetermined depth of S. p-type well PW
For example, boron is introduced into L, and phosphorus is introduced into the n-type well NWL. Then, nMISQn and pMISQp are formed in the active region surrounded by the isolation portion 6 in the regions of the p-type well PWL and the n-type well NWL, and the nMISQn and pMISQn and pMISQn thereof are formed.
A CMIS circuit is formed by ISQp.

The gate insulating film 7 of nMISQn and pMISQp is made of, for example, a silicon oxide film having a thickness of about 6 nm. The film thickness of the gate insulating film 7 here is a silicon dioxide equivalent film thickness, and may not match the actual film thickness. The gate insulating film 7 may be composed of a silicon oxynitride film instead of the silicon oxide film. That is, a structure may be adopted in which nitrogen is segregated at the interface between the gate insulating film 7 and the substrate 1S. The silicon oxynitride film is more effective than the silicon oxide film in suppressing the generation of interface states in the film and reducing electron traps.
The hot carrier resistance can be improved and the insulation resistance can be improved. Further, since the silicon oxynitride film is less likely to be penetrated by impurities than the silicon oxide film, the use of the silicon oxynitride film results in diffusion of impurities in the gate electrode material to the substrate 1S side. The fluctuation of the value voltage can be suppressed. To form a silicon oxynitride film, for example, the substrate 1S
May be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ .

The gate electrodes 8 of the nMISQn and the pMISQp are made of, for example, a low resistance polycrystalline silicon film, and a metal film such as a tungsten (W) film via a barrier metal film such as a tungsten nitride (WN) film. It is a so-called polymetal gate structure having a laminated structure of. However, the gate electrode structure is not limited to this, and may be, for example, a single film structure of a low-resistance polycrystalline silicon film, for example, a titanium silicide (TiSi _x ) film or a low-resistance polycrystalline silicon film. having a cobalt silicide (CoSi _x) film is laminated structure may be a so-called polycide structure. A side wall 9 made of, for example, a silicon oxide film is formed on the side surface of such a gate electrode 8. A cap film 10 made of, for example, a silicon oxide film or a silicon nitride (Si ₃ N ₄ etc.) film is formed on the upper surface of the gate electrode 8. The channels of nMISQn and pMISQp are formed in the portion of the substrate 1S immediately below the gate electrode 8.

The semiconductor region 11 for the source and drain of the nMISQn has a so-called LDD (Lightly Doped Drone) having an n ⁻ type semiconductor region and an n ⁺ type semiconductor region.
ain) structure. n ⁻ type semiconductor region and n ⁺
For example, phosphorus (P) or arsenic (As) is introduced into both of the n ^- type semiconductor regions, but the impurity concentration of the n ⁻ type is lower than that of the n ⁺ type. On the other hand, the semiconductor region 12 for the source and the drain of the pMISQp has a so-called LDD structure having a p ⁻ type semiconductor region and ap ⁺ type semiconductor region. Boron, for example, is introduced into both the p ⁻ type semiconductor region and the p ⁺ type semiconductor region, but the impurity concentration of the p ⁻ type is lower than that of the p ⁺ type.

Substrate 1S of wafer 1W for such a product
A conductor film 3 is deposited on the main surface via an insulating film 2a. The conductor film 3 is a laminated conductor film of the conductor films 3a to 3c similarly to the above. Here, in the pattern dense region, the conductor film 3 is electrically connected to the semiconductor regions 11 and 12 for the source and drain of the nMISQn and pMISQp through the contact holes CNT formed in the insulating film 2a. In the contact hole CNT, the conductor film 3a and the conductor film 13 such as tungsten stacked on the conductor film 3a are embedded. On this conductor film 3, a resist pattern 4a having a desired planar shape similar to that shown in FIG. 4 is formed.

Subsequently, by using the same dry etching apparatus as described above and using the resist pattern 4a as an etching mask, a plasma dry etching process using a chlorine (Cl) -based gas is carried out in the same manner as described above. The conductor film 3 (3c to 3c) exposed from the pattern 4a
a) is removed by etching. FIG. 11 shows a cross-sectional view of an essential part of the product wafer 1W after the dry etching process. The left side of FIG. 11 is the same area as the left side of FIG. 10, and the right side of FIG. 11 is the same area as the right side of FIG. The enlarged cross-sectional view of the main part of FIG. 11 at this time is the same as FIG. By the above etching process, the first layer wiring pattern 5a made of the conductor film 3 is formed. In this etching process, based on the information of the optimum value of the etching amount obtained when the dummy wiring pattern 5da of the dummy wafer 1DW is formed, for example, the etching time,
Etching conditions such as gas pressure, radio frequency (RF) power, etc. are set to optimum values for the product. As a result, it is possible to perform an etching process without excess or deficiency within the surface of the wafer 1W. Therefore, the yield, performance and reliability of the semiconductor device can be improved.
Also during this etching process, the emission waveform in the plasma (see FIGS. 8 and 9) is continuously monitored in the same manner as above. Then, the uniformity of the etching rate within the wafer surface is measured in the same manner as above. Whether or not the etching process is good can be determined by whether or not the uniformity of the etching rate measured at this time is within the range of the uniformity of the etching rate measured on the dummy wafer. Further, if the uniformity of the etching rate in the product wafer 1W exceeds the range of the uniformity of the etching rate in the dummy wafer 1DW, it can be determined that there is a problem on the dry etching apparatus side.

Subsequently, the resist pattern 4a is removed by an ashing process using plasma, and then a wiring forming process is similarly performed to manufacture a semiconductor device. FIG. 12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device, following FIG. 11. The left side of FIG. 12 is the same area as the left side of FIG. 11, and the right side of FIG. 12 is the same area as the right side of FIG. Here, the stage in which the second layer wiring pattern 5b is formed is shown. Insulating films 2b to 2d made of, for example, a silicon oxide film are interposed between the wiring patterns 5a and 5b of the first and second layers. Further, on the insulating film 2d, insulating films 2e and 2f made of, for example, a silicon oxide film are formed.
Is deposited and covers the second layer wiring pattern 5b. The structure of the wiring pattern 5b of the second layer also has the same conductor films 3a to 3c as the wiring pattern 5a of the first layer.
It has a laminated structure of. And this wiring pattern 5
A method similar to that for the wiring pattern 5a is adopted also in the dry etching formation of b. Therefore, according to the first embodiment, in the wiring formation by the dry etching process,
Optimal etching processing is possible not only for each product but also for each different wiring layer in the same product.

(Second Embodiment) In the second embodiment, a case will be described in which the present invention is applied to, for example, an ashing process of a photoresist film.

In the above-mentioned wiring forming step, the resist pattern (resist film) 4a used as an etching mask at the time of forming the wiring is treated with, for example, oxygen gas (O ₂ ) and a small amount of CF ₄
Although it is removed by performing a plasma ashing process using a mixed gas to which a CF-based gas such as the above is added, the ashing process of the resist pattern 4a is performed for the same reason as the etching process of the conductor film. The ashing speed may vary within the plane. When the ashing speed varies within the wafer surface, the wiring patterns 5a, 5 are formed in a region where the ashing speed of the resist film is relatively high, such as the outer periphery of the wafer or a pattern sparse region.
In some cases, the organic side wall film formed on the side wall of the wiring during the etching treatment of b is hardened and cannot be removed. It is said that this is due to fluorine (F) from a CF-based gas added to improve the ashing efficiency. However, if this side wall film is left, corrosion of the wiring patterns 5a and 5b is induced, causing disconnection failure, short circuit failure, etc., and lowering the yield and reliability of the semiconductor device.

Therefore, in the second embodiment, the resist pattern (resist film) 4 on the dummy wafer 1DW is used.
a is a CF such as CF _{4 in} oxygen gas (O ₂ ).
Continuously monitoring from the change start time to the change end time of the emission waveform of CO _x detected from the plasma during the removal by performing the plasma ashing treatment using the mixed gas to which a small amount of the system gas is added. Thus, the uniformity of the ashing rate of the resist pattern 4a on the surface of the dummy wafer 1DW is measured, and the optimum value of the ashing amount of the resist pattern 4a is grasped based on the measured uniformity. Then, when the resist pattern 4a on the product wafer 1W is removed by the plasma ashing process, the ashing condition is adjusted based on the information of the optimum value of the ashing amount obtained in the dummy wafer 1DW. As a result, the resist pattern 4a in the surface of the product wafer 1W can be removed by ashing in an optimum state. That is, the resist pattern 4a can be removed by ashing without leaving a sidewall film on the sidewalls of the wiring patterns 5a and 5b. Therefore, the yield and reliability of the semiconductor device can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first and second embodiments,
Although the dummy wafer is used to grasp the optimum value of the etching amount, the present invention is not limited to this, and the optimum value of the etching amount may be grasped with a product wafer. Alternatively, for example, the optimum value of the etching amount may be grasped by using the wafer which is processed in advance in the semiconductor device manufacturing line, and the etching process of the subsequent wafer may be performed by using the information.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case where the present invention is applied to the method of manufacturing a semiconductor device having an S circuit has been described, but the present invention is not limited to this. For example, a DRAM (Dynamic Random Access Memory), SR
AM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasable Programm)
device having a memory circuit such as able read only memory), a semiconductor device having a logic circuit such as a microprocessor, or a mixed-type semiconductor device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. It can also be applied to other semiconductor device manufacturing methods such as.

[0042]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

That is, by continuously monitoring the change start time to the change end time of the emission waveform of a desired wavelength detected from the plasma during etching, the uniformity of the etching rate of the film to be etched within the surface to be etched is improved. By improving the reliability of each etching process, it is possible to grasp the optimum etching amount in each etching process by having the step of measuring the Is possible.

[Brief description of drawings]

FIG. 1 is an explanation of an emission waveform of a desired wavelength selectively obtained from plasma when a film to be etched is patterned by plasma dry etching in a manufacturing process of a semiconductor device according to an embodiment of the present invention. It is a figure.

FIG. 2 is a detailed diagram of FIG. 1 and is an explanatory diagram of a method for calculating the uniformity of the etching rate.

FIG. 3 shows the uniformity of ± at the light emission waveform end time of 100 seconds.
It is explanatory drawing in case a warning message is generated when it becomes 10% or more.

FIG. 4 is a cross-sectional view of a main part of a dummy wafer.

5 is an enlarged cross-sectional view of a main part of the dummy wafer of FIG.

FIG. 6 is a cross-sectional view of essential parts of the dummy wafer during the manufacturing process of the semiconductor device, following FIG. 4;

7 is an enlarged cross-sectional view of a main part of the dummy wafer of FIG.

FIG. 8 is an explanatory diagram of a light emission waveform obtained during etching of a conductor film on a dummy wafer.

FIG. 9 is an explanatory diagram of a light emission waveform obtained during etching of a conductor film on a dummy wafer.

FIG. 10 is a cross-sectional view of essential parts of a product wafer.

11 is a cross-sectional view of essential parts of the product wafer following FIG.

FIG. 12 is a cross-sectional view of essential parts of the product wafer following FIG. 11.

[Explanation of symbols]

1DW dummy wafer 1DS semiconductor substrate 1W wafer 1S semiconductor substrate 2a to 2f insulating film 3,3a-3c Conductor film 4a Photoresist pattern 5da dummy wiring pattern 5a, 5b wiring pattern 6 Separation section 7 Gate insulation film 8 gate electrode 9 Sidewall 10 Cap film 11 Semiconductor area 12 Semiconductor area 13 Conductor film PWL p-type well NWL n-type well Qp p-channel type MIS • FET Qn n-channel type MIS • FET CNT contact hole

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 AA01 BB01 BB30 BB40 CC01                       CC05 DD04 DD65 FF14 FF18                       FF22 GG16 HH14                 5F004 AA01 CB09 DB08 DB26 EB02                 5F033 HH04 HH08 HH09 HH19 HH25                       HH27 HH33 HH34 JJ19 JJ33                       KK01 LL04 MM07 MM08 MM13                       MM15 NN06 NN07 QQ08 QQ09                       QQ10 QQ12 QQ37 RR04 RR06                       TT08 VV16 XX03                 5F048 AC03 BA01 BB05 BB08 BB09                       BB11 BC06 BE03 BF02 BF11                       BF16 BG12 BG14 DA25

Claims (5)

[Claims] 1. Uniformity of etching rate of a film to be etched in a wafer surface by continuously monitoring a change start time to a change end time of a light emission waveform of a desired wavelength detected from plasma during dry etching. Is measured and the optimum value of the etching amount of the film to be etched is grasped based on the measured value. 2. A predetermined process is performed by depositing a conductor film on a wafer, forming a masking pattern on the conductor film, and etching the conductor film exposed from the masking pattern using the masking pattern as a mask by a dry etching method. In the dry etching process, the wafer is formed by continuously monitoring a change start time to a change end time of an emission waveform of a desired wavelength detected from plasma during the etching. A method of manufacturing a semiconductor device, comprising the step of measuring the uniformity of the etching rate of the conductor film in a plane and grasping the optimum value of the etching amount of the conductor film based on the uniformity. 3. A step of depositing a laminated conductor film having a laminated structure of a first conductor film and a second conductor film on a wafer, a step of forming a masking pattern on the laminated conductor film, and using the masking pattern as a mask. There is a step of forming a predetermined laminated conductor film pattern by etching the laminated conductor film exposed therefrom by a dry etching method, and in the dry etching treatment, light emission of a desired wavelength detected from plasma during etching. The uniformity of the etching rate of the laminated conductor film in the wafer plane is measured by continuously monitoring the change start time to the change end time of the waveform, and the optimum value of the etching amount of the laminated conductor film is measured based on the uniformity. A method of manufacturing a semiconductor device, comprising: 4. A predetermined process is performed by depositing a conductor film on a wafer, forming a masking pattern on the conductor film, and etching the conductor film exposed from the masking pattern using the masking pattern as a mask by a dry etching method. And a pattern dense region in which the predetermined conductor film patterns are densely arranged, and a pattern dense region in which the predetermined conductor film patterns are densely arranged in the surface to be etched. In the dry etching process, by continuously monitoring from the change start time to the change end time of the emission waveform of the desired wavelength detected from the plasma during the etching, the conductor film in the wafer surface is changed. A process of measuring the uniformity of the etching rate and grasping the optimum value of the etching amount of the conductor film based on the measurement A method of manufacturing a semiconductor device, comprising: 5. A predetermined process is performed by depositing a conductor film on a dummy wafer, forming a masking pattern on the conductor film, and etching the conductor film exposed therefrom using the masking pattern as a mask by a dry etching method. In the step of forming the conductor film pattern, the etching of the conductor film in the wafer surface is performed by continuously monitoring the change start time to the change end time of the emission waveform of the desired wavelength detected from the plasma during etching. A step of measuring the uniformity of the speed and grasping the optimum value of the etching amount of the conductor film based on the uniformity, a step of depositing the conductor film on a product wafer, and a step of forming the masking pattern on the conductor film. Step, dry etching the conductor film exposed from the masking pattern as a mask In the step of forming a predetermined conductor film pattern by etching by the method, it is possible to perform the etching process while setting the etching condition based on the optimum value information of the etching amount of the conductor film grasped using the dummy wafer. A method for manufacturing a characteristic semiconductor device.