JP2003132110A - Dummy element adding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate a correction of wiring, to eliminate reexecution of CTS, and to shorten TAT for verifying the timing by dispersively arranging dummy elements. SOLUTION: A dummy element adding process (S3, and S4) in a layout of a logic gate of an integrated circuit is characterized by dispersively arranging the dummy elements used for correcting logic by predetermining an insertion rate of the dummy elements to the number of respective cells of a net list including the dummy elements on the layout when requiring to correct the layout because of the occurrence of problems of the logic change and timing not converging.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for adding a dummy element, and more particularly to a method for adding a dummy element which facilitates wiring correction.

[0002]

2. Description of the Related Art Generally, when designing a logic of an integrated circuit or the like, the logic change in the layout of the logic gate,
There may be a problem that timing does not converge, and layout correction may be required. In such a case, a dummy element used for logic correction is arranged in an integrated circuit or the like.

FIG. 15 is a design flow chart including the addition of a dummy element in the conventional example. The method of adding a dummy element will be described with reference to FIG. First, the HDL description list 101 is created in the "circuit design process" of step S1. Next, the netlist (Net
list) 102 is created. In the "dummy circuit connection" in the next step S4d, the netlist 102
Connect the dummy circuit list 104 prepared in advance to
After adding the dummy circuit, the netlist 103 is created. According to the netlist 103 after the dummy circuit is added, the "layout process" of step S5 is performed, and the presence or absence of logic correction is checked in step S6. If there is a logic correction, the wiring is corrected in step S7 and there is no logic correction. For example, the layout is completed in step S8.

In this case, as shown in the circuit diagram of FIG. 16, the dummy element includes a circuit in which a flip-flop 21, a NAND gate 22, a NOR gate 23, and an inverter 24 are connected in series, a NAND gate 31, a NOR gate 32, and a flip-flop. It is assumed that the dummy circuit 26 in which the groups 33 are connected in series is connected. In this case, in the dummy circuit 26, a dummy circuit including many dummy elements is connected to a specific net on the netlist 103, and the layout is performed using the netlist 103 with the dummy added.

The layout of this conventional IC is shown in FIG.
Shown in. That is, the layout of the conventional IC 10 is such that the dummy element 12a is arranged after the normal element 11 is arranged.
Are placed together in a certain area. Therefore, if there is a correction using the dummy element 12a, a long correction wiring 14a from the correction point 13 to the dummy element 12a is required.

FIG. 18 shows a CTS (Clock Tree Synthesis) including the addition of a dummy element of another conventional example.
The design flow diagram when executing is shown. The CTS is a method of automatically inserting / distributing a buffer to be inserted between a clock driver and a sequential circuit for layout of a clock wiring in layout in consideration of fan-out limitation and logic in order to secure the timing of clock wiring. A description will be given along this flow.

Here, steps S1 to S4d
Thus, the step of creating the netlist 103a after the dummy circuit is added is the same as the case of FIG. According to the netlist 103 after adding the dummy circuit, step S5b
Perform "layout process" including CTS of
Check whether there is a logical correction in 6 and if there is a logical correction,
The wiring is corrected and the CTS is re-executed in step S7a. If no wiring is corrected, the layout is completed in step S8.

When the layout including the CTS is performed in the "layout step" of step S6, the same circuit as the circuit diagram of FIG. 16 is used, and the F / F21 and the dummy F / F33 are used.
If the dummy F / F33 is used for the logic correction, it is necessary to execute the CTS again because the delays of the clock lines are not aligned or the clock line of the dummy F / F33 is connected to the power supply and GND. .

As described above, in the conventional dummy circuit connection, a dummy circuit including many dummy elements is connected to a specific net on the netlist, and layout is performed using the netlist with the dummy added. When a logic change (specification change, etc.) is made after this layout, the layout is corrected using dummy elements.

[0010]

However, the conventional dummy addition method has the following problems. The first problem is that, as shown in FIG. 17, after the normal element 11 is arranged, the dummy elements 12a are collectively arranged in a certain region. Therefore, if there is a correction using the dummy element 12a, the correction point 13 To the dummy element 12a, a long repair wiring 14a is required.

In this way, the correction point 13 and the dummy element 12 are
There is a problem in that the wiring 14a becomes long because the position a is far away and a long wiring 14a must be drawn to a portion where a necessary dummy element is present, and the wiring correction 13 and the timing verification TAT become long.

A second problem is that since the position of the correction portion 13 and the dummy element 12a are far from each other, the wiring cannot be corrected. Therefore, the ground element correction may be necessary without using the inserted dummy element 12a. .

Further, when the layout including the CTS is performed, the delays of the clock lines of the F / F and the dummy F / F are not aligned, and the clock line of the dummy F / F is connected to the power supply and GND. Therefore, when the dummy F / F is used for the logic correction, there is a problem that the CTS has to be executed again.

It is an object of the present invention to provide a dummy adding method in which dummy elements are dispersedly arranged to facilitate wiring correction, eliminate CTS execution again, and shorten TAT for timing verification.

[0015]

According to the structure of the present invention, in the method of adding a dummy element at the time of laying out a logic gate of an integrated circuit, there is a problem that logic change and timing do not converge and layout correction becomes necessary. It is characterized in that dummy elements used for logic correction are automatically distributed on the layout.

In the present invention, when automatically arranging on the layout, it is possible to predetermine the insertion ratio of the dummy elements with respect to the number of each cell of the netlist including the dummy elements. As the element, a dummy element having a circuit different from the circuit of the normal element which is the source of the dummy element can be provided.

Further, in the present invention, when a dummy element is added, the normal element and the dummy element on the netlist are set as one layer, and the normal element is combined into a block including the normal element and the dummy element. The dummy elements can be replaced, and the addition of the dummy elements is added so as to prevent the load of the netlist to which the dummy elements are added from increasing.
After performing the automatic placement, the input of the dummy element can be reconnected to the power supply by using the ECO, and further, the specific element is replaced with the block including the dummy element prepared in advance, so that the dummy element is replaced. Has the same effect as adding. The block including the dummy element can be created in advance as a library.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart for explaining an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are partial views before and after correction of a netlist used in the dummy insertion method, and FIGS. 3 (a) and 3 (b). FIG. 3 is a circuit diagram of an example of a circuit used in the dummy insertion method.

First, a description will be given according to the flow chart of FIG. HDL description 1 in the "circuit design process" of step S1
01 is created, and the netlist 102 is created from the HDL description 101 by "logical synthesis" in the next step S2. The description so far is the same as the conventional one.

In this embodiment, in order to dispose the dummy elements in a dispersed manner on the layout, the "dummy circuit adding step" of steps S3 and S4 in the flowchart of FIG. 1 is added to automatically add the dummy elements to the netlist. 10
Added on 3. That is, the insertion ratio of the dummy element for each cell number of the netlist 103 is determined in advance.

In this "dummy circuit adding step", first,
In the "search for the number of elements" in step S3 of FIG. 1, a program is created and searched for how many cells are present in the netlist 102. Next, in "add dummy element" in step S4, a program is created so as to have a predetermined ratio and dummy elements are added on the netlist 103.

For example, when adding 20% of NAND gates and 10% of inverters, one out of five NAND gates on the netlist 102 before dummy addition (for example, 1, 6, 11, 16 ... ) For the NAND
NAND of the dummy element so that the gate and the input are the same
A gate is added, and 1 out of 10 inverters on the netlist 102 (for example, 1, 11, 21, 31 ...)
On the other hand, a dummy element inverter is added so that the input is the same as that of the inverter element. The output of the added dummy element is OPEN.

The netlists before and after the addition of the dummy elements are shown in FIGS. 2A and 2B, and an example of the circuit diagram thereof is shown in FIGS. 3A and 3B. That is, as shown in FIG. 2A, the instance list, the function name, and the net name of the net list before the dummy element addition are "FF1, F", respectively.
F, DATA CLK RST Q1 "" ND1, NA
ND, IN1 Q1 OUT1 "" NR1, NOR I
N2 OUT2 OUT3 "..." IN1, INV, OU
T3 OUT4 ”, and as shown in FIG. 2B,“ ND DMY, NA ”is placed between the instance names ND1 and IN1.
"ND, IN1Q1 OPEN" is added, and "IN DMY, INV, OUT3" is added after the instance name IN1.
OPEN ”has been added.

Further, as shown in the circuit diagram of FIG. 3A, a circuit in which a flip-flop 21, a NAND gate 22, a NOR gate 23 and an inverter 24 are connected in series is added to the circuit shown in FIG.
As shown in (b), a dummy element composed of a NAND gate 22a whose output is open in parallel with the NAND gate 22, and an inverter 24 whose output is open in parallel with the inverter 24.
A dummy element made of a is provided.

By thus adding the flow of the "dummy circuit adding step" and creating the additional program, dummy elements are automatically added on the netlist so as to have a predetermined ratio. It

Next, the "layout process" of step S5
When the automatic placement is performed in, the added dummy element is placed near the net to which the element is connected.
It looks like the layout diagram. That is, the normal elements 11 of the IC 10 and the added dummy elements 12 are dispersed and arranged at different positions. Therefore, even if the normal element 11 has a repaired portion 13, a dummy element 12 located nearby can be used.
4 can be shortened. When a logic change is made after the layout in step S5, the layout is corrected by the ECO, but the dummy element added at this time is used. Incidentally, the ECO is a function of a layout tool which, when the layout design is completed or a part of the netlist is changed during the design, produces the layout result up to the present and corrects only the changed part. . At this time, since the dummy elements are dispersed and arranged,
The correction wiring 14 inside can be shortened.

As described above, in the present embodiment, since the dummy elements are arranged in a dispersed manner, the wiring using the dummy at the time of wiring correction is short, and the timing convergence is easy and the correction TAT is short. There is a feature that you can

FIG. 5 shows C as a second embodiment of the present invention.
Flow chart explaining the case of TS execution, FIGS. 6 (a) and 6 (b)
Is a partial view of the netlist used in the dummy insertion method before and after correction, and FIGS. 7A and 7B are circuit diagrams of examples of circuits used in the dummy insertion method. , CTS is required to add an F / F. That is, as shown in FIG.
It is a flow of an embodiment of CTS execution when it is not necessary to perform.

Similar to FIG. 1, the HDL description 101 is created in the "circuit design process" of step S1 and the netlist 0 is created from the HDL description 101 by "logic synthesis" of step S2.
Create 2. Here, a "dummy circuit adding step" is added to automatically add dummy elements on the netlist, but the insertion ratio of the dummy elements with respect to each cell number on the netlist is determined in advance.

In this "dummy circuit adding step", first,
In the "F / F element number search" in step S3a, a program is created to search how many cells are present in the netlist. Next, in "add dummy element (F / F)" in step S4a, a program is created so as to have a predetermined ratio and dummy elements are added on the net list.

The netlists before and after the addition of the dummy elements are shown in FIGS. 6A and 6B, and an example of the circuit diagram thereof is shown in FIGS. 7A and 7B, respectively. That is, the netlist before the addition of the dummy element is similar to the case of FIG. 2A in FIG. 6A, which is “FF” between the instance names FF1 and ND1 as shown in FIG. 6B. DMY, FF,
"DATA CLK RST open" is added, and "IN DMY, INV, O" is added after the instance name IN1.
UT3 OPEN "has been added.

In the circuit in this case, the circuit diagram of FIG. 7 (a) is similar to the circuit diagram of FIG. 3 (a), but with the F / F 21 as shown in FIG. 6 (b). A dummy element including an F / F 21a having an open output and a dummy element including an inverter 24a having an open output are provided in parallel with the inverter 24.

For example, in the case of adding 20% of F / F, one of five F / Fs (1, 6, 11, 16 ...) on the netlist before dummy addition is added to the F / F. F / F of the dummy element is added so that the input is the same as the element. In this case, the output of the added dummy F / F is OPEN.
And Next, automatic layout and CTS are performed in the "layout process" of step S5.

In this embodiment, by connecting the dummy F / F clock (terminal C in the figure) and the normal F / F clock, the delay of the clock lines of the normal F / F and the dummy F / F is reduced. It can be adjusted by CTS. Therefore, even if the logic is changed after the layout and the dummy F / F is used, the delay of the clock of the dummy F / F already matches the delay of the clock of the normal F / F.
It is not necessary to execute S, and the man-hours for layout correction can be greatly reduced.

Next, when a dummy element is added in the dummy circuit adding step as the third embodiment of the present invention, the number of inputs is the same, such as element B for element A and element D for element C. The method of adding different elements will be described below. The flow in this case is similar to that of FIG.
The case where the circuit of (a) is changed to the circuit diagram showing the circuit example of FIG. 8 is shown. That is, N for the NAND gate 22
The OR gate 25 is connected to the inverter 24 in the buffer 2
An example of adding 7 is shown.

This flow is based on FIG. 1, and the HDL description 101 is created in the "circuit design process" of step S1. HDL description 1 by "logical synthesis" in step S2
The netlist 102 is created from 01. A "dummy circuit adding step" in the flowchart is added, and a dummy element is automatically added on the netlist in step S4. In this case, the insertion ratio of the dummy element with respect to each cell number on the net list is determined in advance.

In the "dummy circuit adding step", first,
In the "search for the number of elements" in step S3, a program is created and searched for how many cells are present in the netlist 102. Next, "add dummy element" in step S4
At, a program is created so that the ratio becomes a predetermined ratio, and dummy elements are added on the netlist 102.

For example, when NOR gate is added by 20% and buffer is added by 10%, the netlist 10 before dummy addition is added.
1 of 5 (1, 6, 11, 1) NAND gates on 2
6th), a NOR gate 25 of a dummy element is added so that the input is the same as that of the NAND gate 22,
1 out of 10 inverters 24 on the netlist (1,
Inverter element 2 for 11, 21, 31 ...
So that the input is the same as 4
To add. In this case, the output of the added dummy element is O
It is PEN.

Also in this case, by adding a "dummy circuit adding step" flow and creating an additional program, dummy elements are automatically added on the netlist so as to have a predetermined ratio. .

Next, the "layout process" of step S5
In Fig. 4, when the automatic placement is performed, the added dummy element is placed near the net to which the element is connected.
The dummy elements added as described above are arranged at different positions. When the logic is changed after the layout, the layout is corrected by the ECO, but the dummy element added at this time is used.

This ECO is a function of the layout tool that corrects only the changed part by utilizing the layout result up to the present when the layout design is completed or a part of the netlist is changed during the design. is there. At this time, since the dummy elements are dispersed and arranged, the correction wiring can be shortened as shown in FIG.

As described above, in the present invention, since the dummy elements are arranged in a dispersed manner, the wiring using the dummy at the time of wiring correction is short, and the timing convergence is easy and the correction TAT can be shortened. I can.

FIG. 9 is a flow chart for explaining the fourth embodiment of the present invention. When a dummy element is added in the dummy circuit adding step, the normal element and the dummy element on the netlist are set as one layer. However, FIG. 10 is a circuit diagram of a circuit example in which a normal element is replaced with a block in which a normal element and a dummy element are combined.

In the flow of FIG. 9, the HDL description 101 is created in the circuit design process of step S1. A netlist 102 is created from the HDL description 101 by logic synthesis in the next step S2, and then a dummy element adding program is created and executed in a dummy circuit adding step. The insertion ratio of the dummy element for each cell number on the net list 101 is determined in advance.

In the number-of-elements search in step S3, the number of cells in the netlist 101 is searched,
In the "replacement with a block including addition of a dummy element" in step S4b, replacement with a block including a dummy element is performed as follows so that the dummy elements are added at a predetermined ratio. A block including this dummy element needs to be created in advance as a library.

For example, when adding 20% NAND and 10% NOR gate, the netlist 10 before dummy addition
The element is replaced with a block including a dummy for 1 out of 5 (1, 6, 11, 16 ...) of the NAND on 2
The element is replaced with a block including a dummy for one out of ten (1, 11, 21, 31 ...) Of the inverters 24 on the netlist 103. The output of the added dummy element is OPEN. In the layout process of step S5, when automatic placement is performed, the added dummy element is placed near the net to which the element is connected, and each added dummy element is placed at a different position as shown in FIG. .

When the logic is changed after the layout as described above, the layout is corrected by the ECO.
At this time, the hierarchy of the portion replaced with the block including the dummy element is expanded and used.

FIG. 11 is a flow chart for explaining the fifth embodiment of the present invention, and FIGS. 12 (a) and 12 (b) are circuit diagrams showing its circuit example. In the present embodiment, in order to prevent the load of the netlist to which the dummy element is added from increasing, there is a case where the input of the dummy element is reconnected to the power supply using the ECO after the dummy element is added and the automatic placement is performed. Show.

Description will be given along the flow of FIG. The HDL description 101 is created in the circuit design process of step S1, and the netlist 102 is created from the HDL description 101 by logic synthesis in step S2. Furthermore, step S3
In the dummy circuit adding step of 4, a dummy element adding program is created and executed. Further, the insertion ratio of the dummy element with respect to each cell number on the net list 102 is determined in advance.

First, in the search for the number of elements in step S3, the number of cells in the netlist 102 is searched. In "add dummy element" in step S4, a dummy element is added as in the first embodiment. Furthermore, steps S11, S12, S13, S5, S6.
Automatic layout is performed in the layout process including S7.
As a result, the added dummy elements are arranged near the net to which the elements are connected, and the respective dummy elements are arranged in a dispersed manner.

Since the load of the net to which the dummy element is added increases due to the wiring to the dummy element and the gate capacitance of the dummy element, in order to reduce the load, from the net list 103 after the dummy element is inserted, the step S10
Then, the input of the dummy element is changed to the power source to create the changed netlist 105, and using this netlist 105, the ECO including the input change of the dummy element portion in step S12 and the wiring of the dummy element portion in step S13 By doing so, only the input terminal of the dummy element portion is reconnected to the power supply on the layout.

In this case, the circuit of FIG.
As shown in FIG. 3A, as in FIG. 3B, a dummy element including an NAND gate 22a having an open output in parallel with the NAND gate 22 and a dummy element including an inverter 24a having an open output in parallel with the inverter 24 are provided. However, as shown in FIG. 12B, the NAND gate 22b and the inverter 24b whose input terminals are respectively connected to the external terminals 26a and 26b are provided.

As a result, the layout is such that the dummy elements are arranged in a dispersed manner and the load on each net does not increase. If a logical change is entered after this layout, EC
The layout is corrected by O, but the dummy element added at this time can be used.

FIG. 13 is a flow chart for explaining the sixth embodiment of the present invention, and FIG. 14 is a circuit diagram showing its circuit example. This embodiment has the same effect as adding a dummy element by replacing a specific element with a block including a dummy element prepared in advance. For the block including the dummy element, in step S20, the element including the dummy element needs to be created in advance and created as the library 106 including the dummy element.

In the flow of FIG. 13, description will be given along the flow. In the circuit design process of step S1, HDL
The description 101 is created, and the netlist 102 is created from the HDL description 101 by logic synthesis in step S1.
A dummy element addition program is created and executed in the dummy circuit addition step. Here again, the insertion ratio of the dummy element for each cell number on the net list 102 is determined in advance.

In the search for the number of elements in step S3, the number of cells in the netlist 102 is searched. At this time, separately in the device creation process including the dummy in step S20, a library 106 including a device group including two devices is created in advance for normal device replacement. As shown in the circuit diagram of FIG. 14, the elements in this case are, for example, gates 22b and 24b including two NAND gates and two NOR gates.

In the case of this element addition and position determination, the elements on the netlist 102 are replaced with the elements including the dummy as follows so that the ratio becomes a predetermined rate.
For example, 20% NAND gate and 10 NOR gate
% When adding, NA on netlist before adding dummy
1 of 5 ND gates (1,6,11,16 ... th)
Is replaced with an element with a dummy element, and one out of ten inverters on the netlist (1, 11, 21, 31 ...) Is replaced with an element with a dummy element. The output of the added dummy element is OPEN, and the input of the dummy element portion is connected to the power supply.

In the layout process of step S5,
When automatic placement is performed, the added dummy element is placed near the net to which the element is connected, and each dummy element is placed at a different position. When the logic change in step S6 is made after this layout, the layout is corrected by the ECO. At this time, the hierarchy of the portion replaced with the block including the dummy element is expanded and used.

[0059]

As described above, according to the structure of the present invention, the following effects can be obtained. First, the first
The effect of is that the dummy elements are arranged in a dispersed manner, so that the wiring using the dummy elements can be shortened when the wiring is modified.

The second effect is that since the correction wiring can be shortened, the timing can be easily converged and the correction TAT can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a method of adding a dummy element according to a first embodiment of the present invention.

2A and 2B are list diagrams before and after the netlist used in FIG. 1 is added.

3A and 3B are circuit diagrams illustrating addition of a dummy element used in FIG.

FIG. 4 is a layout diagram of an IC for explaining addition of a dummy element in FIG.

FIG. 5 is a flowchart illustrating a dummy element addition method according to the second embodiment of the present invention.

6A and 6B are list diagrams before and after the netlist used in FIG. 2 is added.

7A and 7B are circuit diagrams illustrating addition of a dummy element used in FIG.

FIG. 8 is a circuit diagram illustrating addition of dummy elements according to a third embodiment of the present invention.

FIG. 9 is a flowchart illustrating a dummy element addition method according to a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating addition of a dummy element used in FIG.

FIG. 11 is a flowchart illustrating a method of adding a dummy element according to the fifth embodiment of the present invention.

12A and 12B are circuit diagrams illustrating addition of a dummy element used in FIG.

FIG. 13 is a flowchart illustrating a dummy element addition method according to the sixth embodiment of the present invention.

FIG. 14 is a circuit diagram illustrating addition of a dummy element used in FIG.

FIG. 15 is a flowchart illustrating a method of adding a dummy element in a conventional example.

16 is a circuit diagram illustrating addition of a dummy element used in FIG.

FIG. 17 is a layout diagram of an IC for explaining addition of dummy elements in FIG.

FIG. 18 is a flowchart illustrating another conventional dummy element adding method.

[Explanation of symbols]

10 IC 11 Normal element 12, 12a Dummy element 13 correction points 14,14a Corrective wiring 21,21a, 33 flip-flops 22,22a, 31 NAND gate 23, 25, 32 NOR gate 24, 24a inverter 26 Dummy circuit 27 buffers 101 HDL description list 102 Netlist 103 Dummy additional netlist 104 Dummy circuit list 105 Dummy element change netlist 106 Dummy element library S1 to S20 processing steps

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 21/82 CR F Term (Reference) 5B046 AA08 BA05 5F038 CA02 CA07 CA18 CD05 CD06 EZ20 5F064 BB05 BB06 BB07 BB19 DD02 DD03 DD13 DD14 DD24 DD26 EE02 EE03 EE54 FF09 FF36 FF48 HH12

Claims (6)

[Claims] 1. A dummy element used for logic correction when a logic change or timing convergence problem occurs in a method of adding a dummy element at the time of layout of a logic gate of an integrated circuit, and the layout correction is required. The method for adding dummy elements is characterized in that the elements are automatically distributed on the layout. 2. The dummy element addition according to claim 1, wherein a dummy element insertion ratio with respect to each cell number of a netlist including a dummy element is determined in advance when the elements are automatically distributed on a layout. Method. 3. The method of adding a dummy element according to claim 1, wherein a dummy element having a circuit different from a circuit of a normal element which is a source of the dummy element is provided as the dummy element. 4. When adding a dummy element, the normal element and the dummy element on the netlist are set as one layer, and the normal element is replaced with a block including the normal element and the dummy element. Alternatively, the method of adding a dummy element described in 3 above. 5. The input of the dummy element is connected to a power source by using an ECO after the dummy element is added and automatic placement is performed so as to prevent the load of the netlist to which the dummy element is added from increasing. The method for adding a dummy element according to claim 2, 3 or 4, wherein the dummy element is added. 6. The same effect as adding a dummy element by replacing a specific element with a block including a dummy element prepared in advance. The method of adding a dummy element according to claim 2, 3, 4, or 5, wherein the block including the dummy element is created in advance as a library.