JP2003123069A - Image processing method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the image processing speed of contrast correction. In an image processing method for converting image data of an input image based on a set data conversion condition and correcting the contrast of the input image, the image data of the input image is divided into a plurality of blocks each having a plurality of pixels. The setting data conversion condition is obtained based on image data representing a block. Therefore, the number of pixels to be processed is reduced, and the processing speed can be improved.

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an image processing method for converting image data of an input image based on a set data conversion condition and correcting the contrast of the input image. 2. Description of the Related Art Conventionally, contrast correction of an input image is performed by
Based on the image data of all the pixels of the input image, setting data conversion conditions for performing contrast correction by a technique such as histogram flattening have been obtained. [0003] However, in the above-described conventional configuration, the number of pixels to be processed increases with the improvement in the quality of various image input devices, and the processing speed of image processing decreases significantly. Came to be. The present invention has been made in view of such circumstances, and an object thereof is to improve the image processing speed of contrast correction. According to a first aspect of the present invention, there is provided an image processing method for converting image data of an input image based on a set data conversion condition and correcting the contrast of the input image. The image data is divided into a plurality of blocks each having a plurality of pixels, and the setting data conversion condition is obtained based on the image data representing each block. Therefore, the number of pixels to be processed is reduced, and the processing speed can be improved. Embodiments of the present invention will be described below with reference to the drawings. The photographic print system DP according to the present embodiment is known as a so-called digital mini-lab machine, and as shown in FIG. 4, a developed photographic film 1 (hereinafter simply referred to as “film 1”). ), An image input device IR for inputting image data for producing a photographic print from a memory card, MO or CD-R, etc., and an exposure process for exposing the image data input by the image input device IR to photographic paper 2.・ Developing device EP
It is composed of [Schematic Configuration of Image Input Apparatus IR] As shown schematically in FIG.
, An external input / output device 4 having a memory reader, an MO drive, a CD-R drive, etc., and a general-purpose small computer system. A main controller 6 is provided for executing the control of the entire photo print system DP in addition to the control. The main controller 6 further displays a simulated image simulating the finished print image and various control information. Monitor 6a
And an operation console 6b for performing manual setting of exposure conditions and inputting control information. The film scanner 3 includes a halogen lamp 1
0, a light control filter 11 for adjusting the color balance of light emitted from the halogen lamp 10, and a light control filter 1
Mirror tunnel 12 that evenly mixes light passing through 1
A film mask unit 13 provided with a transport mechanism 13a and a film mask (not shown) for positioning the film 1 at a predetermined reading position, and a CCD line sensor unit 14 for photoelectrically converting a frame image of the film 1
And the image of the film 1 is transferred to the CCD line sensor unit 1
A lens 15 for forming an image on the optical path 4, a mirror 16 for bending the optical path by 90 degrees, a processing circuit 17 for amplifying and A / D converting an output signal of the CCD line sensor unit 14, and the entire film scanner 3 And a reading control device 18 for controlling the reading operation. The CCD line sensor unit 14 has about 5
CCD line sensors in which 000 CCD elements are arranged in the width direction of the film 1 are arranged in three rows.
Red, green, and blue color filters are formed on the light receiving surface of the D-line sensor, respectively, and the frame image of the film 1 is color-separated and detected. The reading control device 18 is configured to read the film mask unit 13 based on a reading command from the main control device 6.
The transport movement of the film 1 set in the camera 1 is started, and the image data of the frame image of the film 1 output from the processing circuit 17 is output to the main controller 6. As shown in FIG. 1, the main controller 6 includes a mosaic processing section 40 for mosaic processing the image data input from the film scanner 3, a mosaic processing control section 44 for controlling the mosaic processing section 40, An image processing unit 42 for performing various types of image processing and an output image memory 43 for storing image data processed by the image processing unit 42 are provided. The image data input from the film scanner 3 is used for producing a photographic print. The image is processed into a suitable image and stored in the output image memory 43. The image data stored in the output image memory 43 is converted into exposure image data for exposure processing by the exposure / developing apparatus EP after performing density correction and the like according to an instruction input by an operator as necessary. You. The image processing unit 42 performs correction processing such as density correction, sharpness correction, and contrast correction.
Therefore, the density correction unit 50 and the sharpness correction unit 51
The contrast correction unit 52 and the like are configured by software as described later. Among these, the contrast correction unit 52 executes the contrast correction processing by so-called histogram flattening. However, instead of creating a histogram based on image data of all pixels, the contrast correction unit 52 reduces the number of data to be processed and generates a histogram. Make it. That is, the mosaic processing unit 40 divides the image input from the film scanner 3 into a plurality of blocks vertically and horizontally, and, for each block, image data representing pixels belonging to the block (specifically, average data ) Is performed, and a histogram is created from the image data after the mosaic processing, thereby speeding up the arithmetic processing. As shown in FIG. 1, the mosaic processing section 40 executes a main part of the mosaic processing for obtaining image data representative of each block. Buffer 61 and mosaic buffer 62 for temporarily storing
And a FIFO memory 63 for temporarily storing image data input from the film scanner 3, and both the original image data input from the film scanner 3 and the image data mosaiced by the mosaic generator 60. An input image memory 64 for storing is provided as a main part. Among them, the mosaic generation unit 60 is configured by a logic circuit (more specifically, a PLD) and performs mosaic processing by hardware.
The above-described various image processes are executed by software. The outline of the operation of the mosaic processing unit 40 and the contrast correction using the processing result of the mosaic processing unit 40 will be described. Image data received from the film scanner 3 and stored in the FIFO memory 63 is input data. It is sent to the image memory 64 and the mosaic generator 60
The image data subjected to the mosaic processing by the mosaic generation unit 60 is sequentially stored in the mosaic buffer 62, and the image data in the mosaic buffer 62 is transmitted to the input image memory 64 and stored. Image processing unit 42
Prepares a density histogram by sequentially reading the mosaic-processed image data of the image data stored in the input image memory 64, and generates image data conversion data for correcting the bias of the distribution of the density histogram. To the data conversion table 41. Thereafter, as a process of the contrast correction unit 52, a contrast conversion process is performed on the original image data, which has not been subjected to the mosaic process, stored in the input image memory 64 based on the information of the data conversion table 41. The internal configuration of the mosaic generation unit 60 is a mosaic processing pipelined, and as shown in FIG. 2, a first processing unit 70 for calculating the average of the image data of the row elements in one block. Second processing unit 7 for calculating the average of the image data of the column elements with respect to the processing result in first processing unit 70
1 is provided. The first processing unit 70 includes a first flip-flop F1 that sequentially receives image data of each pixel.
And a second flip-flop F2 for temporarily holding the added value of the input image data, and a first flip-flop F2 for adding the output of the first flip-flop F1 and the output of the second flip-flop F2.
An adder AD1, a third flip-flop F3 that temporarily holds the output of the first adder AD1, and a first divider DV1 that divides the output of the third flip-flop F3 by the number of pixel columns of the block are provided. Has been. The second processing unit 71 includes a fourth flip-flop F4 for receiving the output of the first processing unit 70, and a fifth flip-flop F5 for temporarily storing the added value of each block.
A second adder AD2 that adds the output of the fourth flip-flop F4 and the output of the fifth flip-flop F5, a sixth flip-flop F6 that temporarily holds the output of the second adder AD2, A second divider DV2 for dividing the output of the flip-flop F6 by the number of pixel rows of the block;
A seventh flip-flop F7 for temporarily holding the output of the second divider DV2. Although not shown in FIG. 2, the same clock signal is input to the first to seventh flip-flops, and the flip-flops operate synchronously. Each flip-flop is provided in parallel with a number corresponding to the number of bits of the image data to constitute a parallel register. The first processing unit 70 and the second processing unit 71 perform a mosaic processing control unit 44 for pipeline processing.
The mosaic processing control unit 44 outputs a control signal to the mosaic generation unit 60. The control signal is a flag indicating position information of the pixel to be processed in the block, and includes “FstPx”, “LstPx”, and “FsPx”.
There are four types, “tLn” and “LstLn”. The value of each flag is assigned to each pixel, and the contents are
This will be described with reference to FIGS. 5 to 8 which show a simplified arrangement of pixels of an image to 12 pixels × 9 pixels. In the following description, a case will be described as an example in which one block is configured by pixels in three rows and three columns to form a mosaic. First, in "FstPx" in FIG. 5, only the pixels in the leftmost column of each block are at "H" level, and the other pixels are at "L" level. “LstPx” in FIG.
Only the pixels in the rightmost column of each block are set to “H” level,
Other pixels are at the “L” level. “FstL” in FIG.
In “n”, only the pixels in the top row of each block are at “H” level, and the other pixels are at “L” level. In “LstLn” in FIG. 8, only the pixels in the lower row of each block are at the “H” level, and the other pixels are at the “L” level. On the other hand, the mosaic generation section 60 receives the signals of these flags and controls the first to fifth signals for controlling the operation of the logic circuit.
The control logic circuits 72, 73, 74, 75, and 76 are provided. The mosaic processing control unit 44 controls the “Fst
Px "," LstPx "," FstLn "and" Lst
Ln ”at the same timing as when the image data of the pixel is input to the first flip-flop F1.
Output to the control logic circuit 72. Further, the mosaic processing control unit 44 supplies “H” to the first control logic circuit 72 during the valid period of the image data input to the first flip-flop F1.
A “Valid” signal which becomes a level is output. The general operation of the mosaic generator 60 will be described below. In the following, description will be made in the positive logic. The image data is sequentially sent to the first flip-flop F1 in the same order as the raster scanning, and is sequentially input to the first flip-flop F1 from the image data of the pixel at the upper left corner. When the image data is input, at the same time, the signal of each flag of the pixel and the “Valid” signal are also input to the first control logic circuit 72. In the first control logic circuit 72, “Fs
tPx ”and“ Valid ”are input to an AND gate,
Since the output is output to the clear input of the second flip-flop F2, the output of the second flip-flop F2 is output only when the image data of the first pixel in each row of each block is input to the first flip-flop F1. Reset. A first adder AD that adds the output of the first flip-flop F1 and the output of the second flip-flop F2
Since the output of 1 is input to the second flip-flop F2, the data is added as the image data is input to the first flip-flop F1 sequentially. The output of the first adder AD1 is input to the third flip-flop F3. The third flip-flop F3 completes the addition of the image data of the pixels of one row in each block by the first adder AD1. Then, the output of the first adder AD1 is not held until the completion result is output. That is, the first control logic circuit 72 converts the input signal of each flag and the “Valid” signal into
The data is input to the first flip-flop F1 and then delayed by a delay circuit corresponding to a delay time from the input of the data to the output of the first adder AD1 until the effect thereof appears, and then output to the second control logic circuit 73. Further, the second control logic circuit 73 outputs “L” input from the first control logic circuit 72.
stPx ”and“ Valid ”are input to an AND gate, and the output thereof is latched by a third flip-flop F3.
Since the image data is output to the enable terminal, the image data of the last pixel in each row of each block is added by the first adder AD1, and only when the output is determined, is the output of the first adder AD1 determined by the clock signal input to the clock terminal. 1 adder AD
1 is held in the third flip-flop F3. The output of the third flip-flop F3 is input to the first divider DV1, where it is divided by the number of columns of pixels in each block to obtain an average value of image data in each row of each block. For this purpose, the first divider DV1 is supplied with the column number data of the pixels of each block. The output of the first divider DV1 is held in the fourth flip-flop F4. The second control logic circuit 73 outputs the signal of each of the flags input from the first control logic circuit 72 and “Val
After the signal "id" is delayed by a delay circuit for a time corresponding to a delay time from when the data is input to the third flip-flop F3 to when the output of the first divider DV1 has its influence, the third control is performed. The third control logic circuit 74 outputs the average value of the image data of the pixels in any row of any block from the logical product of the input “LstPx” and “Valid”. Is held in the fourth flip-flop F4, and accordingly,
If the data held in the fourth flip-flop F4 is the average value of the upper row of each block, the output of the fifth flip-flop F5 is reset. That is, in the third control logic circuit 74, “FstLn” and “Valid” are input to the AND gate, and the output thereof is output to the clear input of the fifth flip-flop F5. The output of the fifth flip-flop F5 is reset only when the average value of the image data of the pixel is input to the fourth flip-flop F4. On the other hand, when the data held in the fourth flip-flop F4 is the average value of the rows other than the top row of each block, the image data is read from the intermediate buffer 61 and input to the fifth flip-flop F5. . Since the intermediate buffer 61 adds the average value of a certain row in a certain block in the second adder AD2 because the image data is input in the same order as the raster scanning, the intermediate buffer 61 adds the average value of the next row of the block. Before the addition, the addition process is performed for other blocks, so that the data in the middle of adding the average value of each row of each block is temporarily stored and held. The third control logic circuit 74 includes a counter for designating a storage address for storing data for each block in the row direction. The input "LstPx"
The address is sequentially incremented by counting the pulse of the logical product of the data and "Valid", and the count value is reset as the count value corresponding to the number of blocks in the row direction is counted. Accordingly, the address of the intermediate buffer 61 is changed in synchronization with the reception of new data from the first processing unit 70 by the fourth flip-flop F4, and the next time the data of the same block is received, the same address as the previous time is used. Is to be specified. Therefore, when the average value of the image data of a certain row in a certain block is input, the second adder AD2 adds the integrated value to the previous block and outputs the sum to the sixth flip-flop F6. . When the second adder AD2 completes the addition of the average value of the image data of one row of the block and outputs the completion result, the sixth flip-flop F6 outputs the second adder AD2.
Hold the output of That is, the third control logic circuit 74
Indicates the input signal of each flag and “Valid”
The signal is delayed by a delay circuit for a time corresponding to a delay time from when data is input to the fourth flip-flop F4 to when the signal appears on the output of the second adder AD2, and then the fourth control logic circuit 75, and the fourth control logic circuit 75 further inputs “LstPx” and “Valid” input from the third control logic circuit 74 to the AND gate, and outputs the output thereof to the sixth flip-flop F6. When the addition of the average value of the row elements of the image data input from the first divider DV1 is completed, the value is held in the sixth flip-flop F6. The fourth control logic circuit 75 further determines that the signal received from the third control logic circuit 74 is “Vali”
d ”and“ LstPx ”are“ H ”level and“ LstPx ”
Only when “Ln” is at the “L” level, writing of input data is instructed to the intermediate buffer 61, and the output of the sixth flip-flop F 6, which is the added value during the calculation of a certain block, is stored in the intermediate buffer 61. You. The output of the sixth flip-flop F6 is input to the second divider DV2, where the output is divided by the number of rows of pixels in each block, and the average value of the image data in the lower row of each block is calculated by the seventh flip-flop. When input to F7, the average value of the image data of all the pixels of the block is output. For this purpose, the row number data of the pixels of each block is input to the second divider DV2. The seventh flip-flop F7 holds the output value when the second divider DV2 outputs the average value of the image data of all the pixels in each block. That is, the fourth control logic circuit 75 converts the input signal of each flag and the “Valid” signal into
The delay is delayed by a delay circuit corresponding to a delay time from when data is input to the sixth flip-flop F6 to when its effect appears on the output of the second divider DV2, and then output to the fifth control logic circuit 76 Further, the fifth control logic circuit 76 outputs “L” input from the fourth control logic circuit 75.
stPx ”,“ LstLn ”and“ Valid ”
The second divider DV2 outputs the average value of the image data of all the pixels in each block because the signal is input to the D gate and its output is output to the latch enable terminal of the seventh flip-flop F7. At this time, the seventh flip-flop F7 holds the output value. Fifth control logic circuit 76
Further instructs the mosaic buffer 62 to write the input data in synchronization with the data holding of the seventh flip-flop F7, and stores the output data of the seventh flip-flop F7. [Schematic Configuration of Exposure / Developing Apparatus EP]
The developing device EP includes an exposure unit 20 having a PLZT print head 20a inside a housing, and an exposure unit 20.
An exposure control device 21 for controlling the exposure, a developing processing unit 22 for developing the photographic paper 2 exposed by the exposure unit 20,
A development control device 23 for controlling the photographic paper transport system in the development processing section 22 and managing the development processing liquid; a printer control device 24 for controlling the entire exposure / development device EP; A photographic paper transport system PT for transporting the photographic paper 2 pulled out of the magazine 8 to the development processing unit 22 by a large number of transport rollers 25 and the like is provided. Outside the housing of the exposure / developing apparatus EP, a sorter 26 for classifying the photographic paper 2 developed and dried by the development processing section 22 for each order, and a discharge port 22a
A conveyor 27 for transporting the photographic paper 2 discharged from the printer to a sorter 26 is provided. An operation console 29 for inputting various control information and a monitor 30 for displaying various control information are also provided. Has been. Further, a cutter 28 for cutting the long photographic paper 2 drawn from the photographic paper magazine 8 into a set print size is provided in the middle of the transport path of the photographic paper transport system PT. [Photo Print Production Operation] Next, the operation of producing a photo print by the photo print system DP having the above configuration will be schematically described. When the operator instructs to make a photographic print for the frame image of the film 1,
The main controller 6 instructs the film scanner 3 to read the film 1, sequentially receives the image data of the film 1 from the reading controller 18, performs the above-described image processing, and then performs the output image memory 43. To record. On the other hand, when the operator gives an instruction to make a photographic print for image data recorded on a recording medium such as a memory card, MO, or CD-R, the main controller 6 sends the corresponding drive of the external input / output device 4 to the corresponding drive. To read the image data, sequentially receive the image data from the drive, and record it in the memory. Based on the image data input as described above, the main controller 6 converts a simulated image, which may be obtained when a print is made with the image data, into an image processing circuit (not shown). To calculate
It is displayed on the monitor 6a. The operator operates this monitor 6
Observing the simulated image on “a”, if an appropriate image is not obtained, a correction input operation of the exposure condition is performed from the console 6b. The image processing circuit of the main control unit 6 generates exposure image data for each of red, green, and blue under predetermined calculation conditions according to the input image data and its correction input. The exposure image data is sent to the printer control device 24 of the exposure / developing device EP, and is stored in a memory provided in the printer control device 24. When the printer control device 24 detects that the front end of the photographic paper 2 has been transported to the predetermined exposure start position based on the transport information of the photographic paper 2 obtained from the photographic paper transport system PT, the exposure control device 21 Command the start of the exposure operation to
The image data for exposure is sequentially transmitted to the exposure control device 21 at a speed corresponding to the exposure processing speed of the exposure unit 20.
The exposure control device 21 operates each optical shutter of the PLZT print head 20a based on the received exposure image data to form a latent image of a print image on the printing paper 2.
The photographic paper 2 exposed by the exposure unit 20 is transported to the developing section 22 by the photographic paper transporting system PT, and is developed by sequentially passing through the developing tanks. Is the outlet 2 after further drying treatment
It is discharged from 2a onto a conveyor 27 and is sorted by a sorter 26 for each order.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a main part according to an embodiment of the present invention. FIG. 2 is a block diagram of a mosaic generating unit according to an embodiment of the present invention. FIG. 4 is a block diagram of a photo print system according to the embodiment; FIG. 4 is an external perspective view of the photo print system according to the embodiment of the present invention; FIG. 5 is an explanatory diagram of flags according to the embodiment of the present invention; FIG. 7 is an explanatory diagram of a flag according to an embodiment of the present invention. FIG. 7 is an explanatory diagram of a flag according to an embodiment of the present invention. FIG. 8 is an explanatory diagram of a flag according to an embodiment of the present invention. 52 Contrast correction unit 60 Mosaic generation unit

Claims (1)

1. An image processing method for converting image data of an input image based on a set data conversion condition and correcting the contrast of the input image, wherein the image data of the input image is divided into a plurality of pixels. An image processing method for dividing the data into a plurality of blocks and obtaining the setting data conversion condition based on image data representing each block.