JP2003116271A - Step-down converter and FET driving method of step-down converter - Google Patents

Abstract

(57) Abstract: A step-down converter that reduces switching loss, prevents input voltage Vin from being directly limited to the absolute maximum rated value of main switch Q1, and prevents through current from flowing. A step-down converter that regulates an input voltage to a constant voltage and outputs the input voltage, wherein an FET (Q
1) switching means for switching between receiving and shutting off the input voltage, and stepping down the input voltage to output the voltage;
FET for switching the FET (Q1)
A drive circuit including a driving unit and a gate charging unit for performing gate charging of the FET (Q1);
The FET is based on the output of the step-down means so that the gate charge is performed when T (Q1) is off.
A timing signal generating circuit for generating a signal for controlling the driving timing of the driving means and the gate charging means;

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step-down converter in a switching power supply, and more particularly to an improvement for driving a P-channel FET, which is the main switch of the step-down converter, to reduce a shoot-through current and a switching loss. Is.

[0002]

2. Description of the Related Art Conventionally, step-down converters in switching power supplies are well known. FIG. 3 is a main part configuration diagram showing an example of this type of step-down converter. This step-down converter is a P-channel FET that is a main switch that switches between receiving and cutting off an input voltage by switching.
Q1, diode D1, inductor L1, capacitor C1, error amplifier 10, and comparator CP1
And a drive circuit 20. In addition, with Q1,
Diode D1, inductor L1, capacitor C1
The part consisting of is a step-down means for stepping down the input voltage and outputting a constant voltage.

The error amplifier 10 shifts the output voltage Vout relative to the reference voltage Vref, that is, the output voltage Vou.
It detects a deviation (difference) between the voltage obtained by dividing t and the reference voltage Vref, and is composed of resistors R7 and R8 connected in series and an error amplifier 11. The error amplifier 11 outputs
The difference between the voltage obtained by dividing Vout by resistors R7 and R8 connected in series and the reference voltage Vref is appropriately amplified and output. This output, that is, the error voltage is large when the divided voltage is smaller than the reference voltage Vref, and is small when the divided voltage is larger than the reference voltage Vref.

The comparator CP1 compares the magnitude of such an error voltage with a triangular wave signal having a constant amplitude and compares it with a high level (hereinafter abbreviated as H) or low level (hereinafter abbreviated as L).
The binary signal of is output. The drive circuit 20 turns on / off the main switch Q1 based on the output of the comparator CP1, and is composed of an N-channel FET Q2 and a resistor R1. The resistor R1 is connected between the source and gate of Q1. The source of Q2 is connected to the gate of Q1, the drain is connected to a common line (usually 0V), and the output of the comparator CP1 is added to the gate.

In such a configuration, the output voltage Vout
Rises, the divided voltage (A) by the resistors R7 and R8 also rises, the output of the error amplifier 11 falls, and the output (B) of the comparator CP1 has a shorter time width of H as shown in FIG. When the output of CP1 is H, the drive circuit 20
Q2 is turned on (On), and the main switch Q1 is turned On. Therefore, when the time width of H of the CP1 output becomes short, the time width of On of the switch Q1 also becomes short, and as a result, the output voltage Vout decreases. Conversely, when the output voltage Vout drops, the H time width of the CP1 output becomes longer, the On time width of Q1 becomes longer, and the output voltage Vout rises.

As described above, when the output voltage Vout is going to rise, it is controlled so as to be lowered, and conversely, when the output voltage Vout is going down, it is controlled to be raised. In short, according to such a configuration, the divided voltage A is V
It is controlled to be equal to ref, and the output voltage Vout is automatically kept constant.

Now, in such a configuration, the operation when Q1 turns on (TurnOn) or turns off (TurnOff) is as follows. (1) When Q1 is turned on When the drive signal B which is the output of the comparator CP1 becomes H, Q2 becomes ON. As a result, the gate of Q1 becomes 0V, so the gate-source voltage Vgs of Q1 is −
It becomes Vin and Q1 becomes On.

(2) When the drive signal B becomes L when Q1 is turned off, Q2 is turned off. As a result, a gate charge current flows through the resistor R1 to the gate of Q1, the gate-source voltage Vgs of Q1 becomes 0 V, and Q1 turns off.

The case where the drive circuit has the structure shown in FIG. 5 is as follows. This drive circuit 20a is shown in FIG.
The drive circuit 20 has a resistor R2 added thereto. The resistor R2 is inserted between the gate of Q1 and the source of Q2. The operation in such a configuration is as follows.

(1) When the drive signal becomes H when Q1 is turned on, Q2 becomes ON. As a result, Vgs of Q1 becomes −R1 (R1 + R2) × Vin, and Q1 becomes On. (2) When the drive signal becomes L when Q1 is turned off, Q2 becomes OFF. As a result, a gate charge current flows through the resistor R1 to the gate of Q1, Vgs of Q1 becomes 0V, and Q1 turns off.

Another drive circuit is a drive circuit 20b shown in FIG. This drive circuit 20b
Is composed of Q2, Q3, Q4, R1 and R2. In the P-channel FET Q2, its source and gate are connected to the source of Q1, and its drain is an N-channel FE.
It is connected to the source of TQ3. The drain of Q3 is connected to the common line and the gate is N-channel FETQ
4 sources. The source of Q3 is connected to the gate of Q1 via the resistor R2. Q4
Has a source connected to the gate of Q2 via a resistor R1, a drain connected to a common line, and a drive signal applied to the gate.

The operation in such a configuration is as follows. (1) When the drive signal at the turn-on of Q1 becomes L, Q4 becomes OFF, and the gate potentials of Q2 and Q3 become Vin. This makes Q2 O
ff and Q3 are On. As a result, Vgs of Q1 is -V
It becomes in and Q1 becomes On.

(2) When the drive signal becomes H when Q1 is turned off, Q4 becomes ON, and Q2 and Q
The gate potential of 3 becomes 0V. As a result, Q2 is On,
Q3 turns off. Therefore, the gate charge current flows into the gate of Q1 by Q2, and Vgs of Q1 is 0V.
And Q1 is turned off.

The reason why such a drive circuit must be used conventionally is as follows. Due to the principle of the step-down converter, the source terminal of the P-channel FET Q1 must be connected to Vin, which is a stable potential. Therefore, the On and Off operations of Q1 are realized by setting the gate potential to be equal to or lower than Vin. Normally, V is external
Since there is no voltage source with a voltage higher than in, set Q1 to O
The gate is shorted to the source or has the same potential as the source in order to turn it on.

The simplest implementation of this is the configuration of FIG. However, in this circuit, when Q1 is on, Vgs becomes -Vin, so Vin is limited to the absolute maximum rating of Vgs. The circuit of FIG. 5 removes the limitation of Vgs by dividing Vin by R1 and R2.
The voltage applied to Vgs in this circuit is -Vin x R1
/ (R1 + R2). In FIG. 6, R1 in FIG. 3 is replaced with a FET.

[0016]

However, such a conventional circuit has the following problems. (1) In the case of FIG. 3 and FIG. 5, in order to reduce the power loss (Vin) ² / R1 × Duty (where Duty is the duty ratio of On / Off of Q2) due to the resistor R1, R1 may be increased. However, in that case, the gate charge current for turning off Q1 is reduced, so that the switching loss at the time of turning off is increased. On the contrary, if R1 is reduced to reduce the switching loss, the power loss due to R1 will increase. Due to such a trade-off, there is a problem that the efficiency cannot be improved.

(2) In the case of FIG. 6, although the loss of R1 can be suppressed by replacing R1 with Q2, since the Vgs of Q1 changes in the range of −Vin to 0V, the input voltage Vin is the Vgs of Q1. Limited by absolute maximum ratings.

Also, in this circuit, inserting a voltage dividing resistor as shown in FIG. 5 limits the gate charge current for turning off Q1, and as a result increases switching loss. No resistance can be inserted.

Further, the drive signal is H → L or L →
When it changes to H, Q2 and Q3 momentarily turn on simultaneously.
In this state, a large current (through current) flows, which causes noise. Further, the loss due to the through current increases in proportion to the switching frequency, which is a serious problem in high frequency switching.

An object of the present invention is to solve the above problems, to reduce switching loss and to reduce the input voltage V
It is to realize a step-down converter in which in is not directly limited to the absolute maximum rated value of the main switch Q1 and a through current does not flow.

[0021]

In order to achieve such an object, the invention of claim 1 is a step-down converter which regulates an input voltage to a constant voltage and outputs it, wherein a main switch FET (Q1) is provided. To switch between receiving and shutting off the input voltage to lower and output the input voltage, FET driving means for switching the FET (Q1), and gate charge of the FET (Q1). A drive circuit having a gate charge means for performing the above and a drive timing of the FET drive means and the gate charge means based on the output of the step-down means so that the gate charge is performed when the FET (Q1) is in an off state. A timing signal generating circuit for generating a control signal is provided. According to such a configuration, since the timing is controlled so that the gate charge is not performed when the FET is in the ON state, the through current as seen in the conventional circuit does not flow, and the FET turn-off time is reduced. As a result, the switching loss can be significantly reduced compared to the conventional case.

In this case, the FET drive means of the drive circuit is the FE of the main switch as in claim 2.
A resistor (R connected between the source and emitter of T (Q1)
1), the drain is connected to a common line, the source is connected to the gate of the FET (Q1) through a resistor (R2), and the output signal of the timing signal generating circuit is added to the gate of the FET (Q3). ) Is desirable. With this configuration, the input voltage is Q
There is an effect that it can be made larger than the absolute maximum rated value of Vgs of 1.

Further, the gate charging means of the drive circuit is, as in claim 3, arranged with a voltage dividing circuit (R5, R6) composed of a resistor for dividing the input voltage, and inserted between the voltage dividing circuit and the common line. An FET (Q4) that is driven on / off by a signal from the timing signal generating circuit and a FET that is connected between the source and gate of the FET (Q1) of the main switch and is driven on / off by the divided voltage of the voltage dividing circuit. It is desirable to configure from (Q2). According to such a configuration, since the gate charge of Q1 is performed by Q2, the turn-off time of Q1 can be significantly shortened as compared with the case of the conventional example.

Further, the timing signal generating circuit has voltage dividing means for obtaining two high and low levels of voltage (V1, V2) from the output voltage of the error detecting means, and the two levels. And the triangular wave signal are compared with each other, and when the triangular wave signal becomes lower than the low level voltage (V2), the comparator (CP1) which outputs an H level signal and the triangular wave signal are higher than the high level voltage (V1). Is also provided with another comparator (CP2) that outputs an H-level signal when
It is desirable to drive the FET (Q3) of the FET driving means with the output of and the FET (Q4) of the gate charging means with the output of the other comparator (CP2).

The invention of claim 5 is the FE of the main switch.
In a method of driving a FET in a step-down converter that switches between receiving and shutting off an input voltage by switching T (Q1) to output a predetermined voltage, the FET (Q1) is turned on / off in accordance with the output to drive the FET. The output is controlled to be constant and the FET (Q
At the time of turn-on in 1), F
The gate-source voltage of ET is set to be equal to or lower than the input voltage, and when the FET (Q1) is turned off, the gate charge is performed immediately after the turn-off is driven to perform the FET.
It is characterized in that the turn-off time of (Q1) is shortened. According to this method, the input voltage is FE
Even if the maximum rated voltage between the gate and the source of T is exceeded, the switching loss at turn-off is reduced, and a large through current does not flow.

[0026]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a step-down converter according to the present invention. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals. In FIG. 1, 30 is a timing signal generating circuit and 20c is a drive circuit.

The timing signal generation circuit 30 compares the output voltage of the error amplifier 10 with the triangular wave signal (voltage) and generates a signal for controlling the drive timing of the drive circuit 20c.

The timing signal generation circuit 30 includes resistors R3 and R4 connected in series between the output terminal of the error amplifier 10 and a common line, a triangular wave signal generation circuit 31 for generating a triangular wave signal VT, and an error voltage V1. And triangular wave signal V
A comparator CP2 for comparing T, a voltage V2 obtained by dividing the error voltage V1 by resistors R3 and R4, and a triangular wave signal VT
It is composed of a comparator CP1 for comparing.

The output of the comparator CP2 becomes H when the triangular wave signal VT is larger than the error voltage V1 and becomes L in the opposite case. On the other hand, the comparator CP
The output of 1 becomes H when the triangular wave signal VT is smaller than the divided voltage V2, and becomes L in the opposite case.

The drive circuit 20c has a main switch Q.
FE that controls the gate potential of 1 to drive Q1 on and off
It has a T drive circuit and a gate charging means for rapidly charging the gate of Q1 when Q1 is in the off state, and is configured as follows.

That is, the drive circuit 20c includes a P-channel FET Q2 and N-channel FETs Q3 and Q4.
And resistors R1, R2, R5 and R6.
The source of Q1 to which the input signal Vin is applied is connected to one end of a resistor R1, the source of Q2 and one end of a resistor R5, and the gate of Q1 is connected to the other end of the resistor R1, the drain of Q2 and the resistor R2. One ends are connected together.

The source of Q3 is connected to the other end of the resistor R2, the drain is connected to a common line, and the output of the comparator CP1 of the timing signal generating circuit 30 is added to the gate.

The gate of Q2 is connected to the common connection point of R5 and resistor R6 connected in series. The input voltage Vin is applied to the source of Q4 via series-connected resistors R5 and R6, the drain thereof is connected to the common line, and the gate thereof is connected to the output terminal of the comparator CP2.

Here, the portion composed of the resistor R1 and the resistors R2 and Q3 is called the FET Q1 driving means, and the portion composed of Q2 and the resistors R5, R6 and Q4 is called the gate charging means.

In such a configuration, the error amplifier 1
The error voltage V1 detected at 0 is input to the timing signal generation circuit 30, and the drive circuit is operated based on the comparison result obtained here to drive the main switch Q1 on / off.

In this case, in the timing signal generating circuit 30, the error voltage V2 input to the comparator CP1 is made smaller than the error voltage V1 input to the comparator CP2, so that the rectangular wave voltages at the timings shown in FIG. It is output from the comparators CP2 and CP1.

When the output of the comparator CP2 is H (the output of the comparator CP1 is L at this time), Q
4 becomes On and Q2 becomes On. On the contrary, when the output of the comparator CP2 is L, Q2 is Off.

On the other hand, when the output of the comparator CP1 is H (the output of the comparator CP2 is L at this time), Q3 becomes On and Vgs of Q1 is -Vin * R1 /.
(R1 + R2) and Q1 becomes On. When the output of the comparator CP1 is L, Q1 is Off.

Next, the operation when Q1 turns on or off will be described. (1) When Q1 turns on Immediately before the turn-on of Q1, the output of the comparator CP2 is L, so Q4 is off and Q2 is off. In this state, when the output of the comparator CP1 becomes H, Q3 becomes ON and Q1 turns on. Q
Since Q2 is Off before 3 becomes On, a through current does not flow.

When Q3 is in the ON state, Vgs of Q1 is
Vin × R2 / (R1 + R2). Therefore, FIG.
Unlike the conventional drive circuit of, Vin is Vg of Q1
It can be made larger than the absolute maximum rating Vs (max) of s. Also, R
Since the value of 1 may be a large value, the values shown in FIGS.
The power loss due to R1 is extremely smaller than that of the drive circuit of FIG.

(2) When Q1 turns off, the output of the comparator CP1 becomes L and Q3 turns off. After that, since the output of the comparator CP2 becomes H, Q4 becomes On, and thereby Q2 becomes On. At this time, since Q3 is already in the OFF state, no through current flows. Since the gate charge of Q1 is performed not by the resistor R1 but by the resistor Q2, the turn-off time of the resistor Q1 can be significantly shortened compared with the case of only the resistor R1 as in the circuits of FIGS. Can be significantly reduced.

As described above, according to the present invention, a through current does not flow, Vin can be made larger than the absolute maximum rating of Vgs of Q1, and resistance R1 can be a large value, so that the power loss here can be made extremely small. In addition, it is possible to shorten the turn-off time of Q1 and significantly reduce the switching loss.

Since Q2, Q3, and Q4 may be small-signal FETs, the gate capacitance is small, and high-speed On / Off is possible with a small gate charge current and discharge current.
Is possible. Therefore, the resistors R5 and R6 may have a much larger value than the resistors R1 and R2 of the conventional example shown in FIG. 5, so that the power loss due to these resistors becomes small.

Since the switching loss at turn-on is generally smaller than that at turn-off, the switching loss at turn-on does not increase much even if the gate charge extracting resistor R2 is made large. Therefore R
Larger values may be used for 1 and R2.

It should be noted that the present invention is not limited to the above-described embodiments, and includes many changes and modifications without departing from the essence thereof.

[0046]

As described above, the present invention has the following effects. (1) Since the gate charge of Q1 is performed when the FET Q1 is turned off, a through current does not flow. Since the through current does not flow, there is no loss due to the through current as in the past, and noise due to the through current does not occur. (2) The gate charge can significantly reduce the turn-off time of Q1 as compared with the conventional case.

(3) The resistance value of the resistor R1 connected between the source and gate of Q1 can be increased. Since the gate charge is performed even with a large resistance value, the switching loss at the turn-off of Q1 can be made smaller than in the conventional case. (4) Since the resistance value of the resistor R1 may be large, the power consumption by R1 can be easily reduced. (5) Since Vgs of Q1 is divided by resistors R1 and R2,
The input voltage Vin is not limited by Vgs of Q1.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a step-down converter according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation.

FIG. 3 is a main part configuration diagram showing an example of a conventional step-down converter.

FIG. 4 is an operation waveform diagram in a conventional step-down converter.

FIG. 5 is a diagram showing an example of another conventional drive circuit.

FIG. 6 is a diagram showing an example of another conventional drive circuit.

[Explanation of symbols]

10 Error amplifier 11 Error amplifier 20c drive circuit 30 Timing signal generation circuit 31 Triangular wave signal generation circuit Q1, Q2 P-channel FET Q3, Q4 N-channel type FET D1 diode L1 inductor C1, C2 capacitors R1 to R9 resistance CP1, CP2 comparator

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H730 AA02 AA07 AA14 AS01 BB13                       BB57 DD04 DD28 DD32 FD01                       FF02 FG05 FG25                 5J055 AX04 AX27 BX16 CX19 DX12                       DX53 EX07 EY00 EY01 EY05                       EY10 EY12 EY21 EZ00 EZ09                       EZ10 EZ28 FX05 FX19 FX32                       GX01 GX04 GX05

Claims (5)

[Claims] 1. A step-down converter which regulates and outputs an input voltage as a constant voltage, wherein a FET (Q1) of a main switch is switched to switch between receiving and shutting off the input voltage, and stepping down the input voltage. Step-down means for outputting and FET for switching the FET (Q1)
A drive circuit including a drive means and a gate charge means for performing gate charge of the FET (Q1); and a drive circuit based on the output of the step-down means so that the gate charge is performed when the FET (Q1) is in an off state. A step-down converter comprising a timing signal generation circuit for generating a signal for controlling the drive timing of the FET drive means and the gate charge means. 2. The FET drive means of the drive circuit comprises a resistor (R1) connected between the source and emitter of the FET (Q1) of the main switch, a drain connected to a common line and a source connected to a resistor ( FET connected to the gate of the FET (Q1) via R2) and to which the output signal of the timing signal generating circuit is applied
2. The step-down converter according to claim 1, wherein the step-down converter is composed of (Q3). 3. The gate charge means of the drive circuit is composed of a resistor and divides the input voltage by a voltage divider circuit (R).
5, R6), an FET (Q4) inserted between the voltage dividing circuit and a common line and driven on and off by a signal from the timing signal generating circuit, and an FE of the main switch.
3. The step-down converter according to claim 1, comprising a FET (Q2) connected between the source and gate of T (Q1) and turned on / off by the divided voltage of the voltage dividing circuit. 4. The timing signal generating circuit is configured to output a voltage (V) of two levels, high and low, from the output voltage of the error detecting means.
1, V2) and the voltage of these two levels and the triangular wave signal are respectively compared, and when the triangular wave signal becomes lower than the low level voltage (V2), an H level signal is output. A comparator (CP1) and another comparator (CP2) that outputs a signal of H level when the triangular wave signal becomes higher than the high level voltage (V1) are provided, and the output of the comparator (CP1) is used to output the FET driving means. The FET (Q3) is driven, and the FET of the gate charging means is driven by the output of the other comparator (CP2).
4. The step-down converter according to claim 3, which is configured to drive (Q4). 5. A FET in a step-down converter that outputs and outputs a predetermined voltage by switching the input and output of an input voltage by switching the FET (Q1) of a main switch.
In the driving method described above, the FET (Q1) is controlled to be turned on / off in response to the output so that the output becomes constant, and when the FET (Q1) is turned on, the FET is divided by a voltage dividing means using a resistor. The gate-source voltage of the FET is set to be equal to or lower than the input voltage, and when the FET (Q1) is turned off, the gate charge is performed immediately after driving the turn-off to shorten the turn-off time of the FET (Q1). FET driving method of step-down converter.