JP2003115190A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce power consumption without impairing high-speed operation during burst read operation. SOLUTION: Sense amplifiers respectively amplify parallel read data from memory cells. At least one of the read amplifiers that amplifies the amplified read data has a higher driving capability than the other read amplifiers. The connection switching circuit connects the sense amplifier to a predetermined read amplifier according to the address. By replacing the read data before amplification by the read amplifier, the read data output first during the burst operation can be amplified by the read amplifier having a high driving capability. The data output circuit outputs read data corresponding to a read amplifier having a high driving capability at the time of a burst read operation. Therefore, even in a semiconductor memory in which the output order of read data can be switched according to the address or the operation mode, the read operation time can be reduced, and the power consumption can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption of a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 19 shows a conventional general SDRAM (Synch
ronous DRAM) shows an overview. SDRAM includes a column decoder CDEC, a memory cell array ALY, a plurality of sense buffers SB, a command decoder CMD, and a read control circuit RCN.
It has a T, a data output circuit OUT, and a plurality of input buffers BUF that receive signals from the outside. SDRAM is a control circuit that operates according to a row address
It has a row decoder and the like.

The column decoder CDEC activates the column line selection signal CL1 (or CL2-CL4) of the address signal ADD supplied from the outside according to the column address.
The memory cell array ALY has a plurality of memory cells MC, a plurality of sense amplifiers SA corresponding to the memory cell arrays MC, and a column switch CSW. In the memory cell array ALY, the read data DT read in parallel from a plurality of memory cells MC during a read operation are respectively sense amplifiers.
Amplified by SA. After this, for example, the column line selection signal CL
1 is activated, the corresponding column switch CSW turns on,
Data D of the memory cell MC corresponding to the column line selection signal CL1
T is transmitted to the local data bus DB.

The command decoder CMD decodes a command signal CNT supplied from the outside and outputs the decoding result to the read control circuit RCNT. Read control circuit RCNT
Activates the read control signal RDZ in synchronization with the clock signal CLK when the decode result indicates a read command. The read control circuit RCNT also generates a control signal for operating the above-mentioned column decoder CDEC. The sense buffer SB is activated according to the read control signal RDZ. The sense buffer SB amplifies the read data DT on the local data bus DB to the CMOS level and outputs the amplified data to the common data bus CDB. That is, the sense buffer SB operates as a read amplifier that further amplifies the read data DT amplified by the sense amplifier SA.

The data output circuit OUT is a common data bus CDB.
The read data DT is received through and the received read data DT is output to the outside in synchronization with the internal clock signal CLKZ synchronized with the clock signal CLK supplied from the outside. Figure 2
0 indicates the burst read operation of the SDRAM described above. In this example, the word line is already activated in response to the row address signal at the start of the timing diagram, and the data DT1-DT4 read from the plurality of memory cells MC are
Each is amplified by the sense amplifier SA. The burst length is set to "4". Here, the burst length is
This is the number of read data that are continuously output in one read operation. As will be described later, the read control circuit RCNT
Is the read control signal RDZ corresponding to the burst length.
, The sense buffer SB operates the number of times corresponding to the burst length, and the read data DT is transferred to the common data bus.
Output to CDB sequentially.

First, a read command RD and a column address (not shown) are supplied in synchronization with the 0th clock signal CLK (FIG. 20 (a)). The read control circuit RCNT in FIG. 16 controls the column decoder CDEC to activate the column line selection signal CL1 according to the column address (FIG. 20 (b)). The column switch CSW is turned on by the activation of the column line selection signal CL1, and the read data DT1 is transmitted to the local data bus line DB (FIG. 20).
(C)).

The read control circuit RCNT has a clock signal CL.
The read control signal RDZ is activated in synchronization with K to operate the sense buffer SB (FIG. 20 (d)). The sense buffer SB is the read data DT on the local data bus line DB.
Amplify 1 to the CMOS level and output the amplified data to the common data bus line CDB (FIG. 20 (e)). Since the sense buffer SB has to drive the common data bus CDB having a long wiring length, it is necessary to speed up the operation and increase the driving capability. The data output circuit OUT outputs the read data DT received via the common data bus line CDB to the outside in synchronization with the internal clock signal CLKZ (FIG. 20).
(F)).

After that, in the first to third clock cycles, the same operation as described above is executed, and the read data DT2-DT4 are sequentially output to the outside. That is, the read control signal RDZ is activated the number of times corresponding to the burst length, and the sense buffer SB executes the amplifying operation that number of times.

[0009]

As described above, the sense buffer SB is composed of a circuit that operates at high speed in order to amplify the data DT read from the sense amplifier SA to the CMOS level at high speed. Furthermore, the sense buffer SB
Is a common data bus CDB that loads the amplified data
It is designed to have a sufficiently high drive capacity because it must be output to. Therefore, the sense buffer SB
Consumes a large current. Also, the sense buffer SB
Operate simultaneously as many as the number of bits of the data terminal. Therefore, the power consumption of SDRAM during read operation is
It largely depends on the power consumption of the sense buffer SB.

During the burst read operation, the sense buffer SB and its control circuit operate the number of times corresponding to the burst length. Therefore, power consumption is further increased. In order to transmit the read data DT to the data output circuit OUT at high speed, the common data bus CDB is generally taken measures such as increasing the wiring width and reducing the resistance.
Alternatively, the transfer time of the read data DT is shortened by inserting a buffer with high driving capability in the middle of the common data bus CDB. However, this type of countermeasure is a factor that further increases power consumption.

An object of the present invention is to provide a semiconductor memory capable of significantly reducing the current consumption of the read operation as compared with the conventional one. In particular, it is to reduce the power consumption during the burst read operation.

[0012]

According to another aspect of the semiconductor memory of the present invention, the plurality of sense amplifiers respectively amplify the parallel read data read from the plurality of memory cells.
The switching circuit connects the sense amplifier to a predetermined read amplifier according to an address supplied from the outside. By replacing the read data before amplification by the read amplifier,
The read data that is first output during the burst read operation can always be amplified by the read amplifier having a high driving capability. Therefore, even in the semiconductor memory in which the output order of the read data can be switched according to the address or the operation mode, the read operation time can be shortened and the power consumption can be reduced.

The plurality of read amplifiers respectively amplify the read data amplified by the sense amplifiers to predetermined logic levels. At least one of the read amplifiers has a higher driving capability than the other read amplifiers. A read amplifier with high drive capability can drive the data bus line at a higher speed than other read amplifiers. The read data amplified by the read amplifier having a high driving capability is transmitted to the data output circuit earlier than other read data, so that the data read time can be shortened. The drive capability of the read amplifier can be easily adjusted by, for example, the size of the gate width of the transistor included in the read amplifier.

The data output circuit outputs the read data corresponding to the read amplifier having a high driving capability first during the burst read operation for outputting the parallel read data read from the memory cells to the outside in series. Therefore, in the burst read operation, the time until the first read data is output is shortened. On the other hand, there is a considerable margin before the data output circuit outputs the second and subsequent read data. For example, when the semiconductor memory is a clock synchronous type, there is a margin of at least 1 clock cycle. Therefore, the read amplifier that amplifies the second and subsequent read data can correctly perform the read operation even if the drive capability is low. Since the driving capability of some of the read amplifiers can be lowered, the power consumption during the burst read operation can be reduced. The data output circuit has, for example, a parallel-serial conversion circuit that serially outputs the parallel read data output from the read amplifier.

According to another aspect of the semiconductor memory of the present invention, the sense amplifier and the read amplifier are connected by a column switch. During the burst read operation, the column switch is turned on in the first clock cycle of the read operation and simultaneously transmits the read data to the read amplifier. Since a plurality of column switches can be turned on at the same time, a circuit for controlling the column switches can be simply constructed.

According to another aspect of the semiconductor memory of the present invention, a data bus line connected to a read amplifier having a large driving capability has a lower impedance than a data bus line connected to another read amplifier. Therefore, the read data to be output first can be transmitted to the data output circuit earlier. The impedance of the data bus line can be easily adjusted according to the wiring width of the data bus line, the material of the wiring, or the type of wiring layer in which the data bus line is formed.

According to another aspect of the semiconductor memory of the present invention, the read control circuit generates a plurality of read control signals for activating the read amplifiers. The read control circuit activates the read control signal corresponding to the read amplifier having a high driving capability before the other read control signals. By shifting the operation timing of the read amplifier, it is possible to reduce the peak current during the burst read operation. At this time, unless the activation timing of the read control signal for amplifying the read data to be output first is changed,
The output time of read data will not be delayed.

According to another aspect of the semiconductor memory of the present invention, when the burst length, which is the number of times the read data is continuously output, is set to a single value, that is, when the normal read operation is executed instead of the burst read operation. Data is output by operating a read amplifier with high driving capability. Therefore, a normal read operation can be executed at high speed.

According to another aspect of the semiconductor memory of the present invention, a plurality of blocks each having a memory cell, a sense amplifier, a read amplifier, a data output circuit and a data bus line are formed corresponding to a plurality of data terminals. For this reason,
Even in a so-called multi-bit semiconductor memory, the read operation time can be shortened and the power consumption can be reduced. According to another aspect of the semiconductor memory of the present invention, the blocks are arranged along the first direction, and the data bus lines are arranged along the second direction orthogonal to the first direction. Since the data bus lines are always wired in the same direction, the wiring length of the data bus lines can be shortened, and the wiring resistance and wiring capacitance of the data bus lines can be minimized. As a result, the read operation time can be further shortened and the power consumption can be reduced.

According to another aspect of the semiconductor memory of the present invention, the blocks are arranged along the arrangement direction of the data terminals. Therefore, the block corresponding to each data terminal can be arranged near the data terminal, and the wiring length of the data bus line can be further shortened. According to another aspect of the semiconductor memory of the present invention, each block is divided into a plurality of memory areas along the second direction. Then, a plurality of independently operable banks are formed by the memory regions arranged in the first direction. That is, when the data bus lines are wired in the same direction, by arranging the banks along the wiring direction (second direction) of the data bus lines, the read data read from the memory cells can be read in the second direction. It is possible to propagate along only. As a result, the signal line such as a data bus line for transmitting read data can be minimized, and the read operation time can be further shortened.

According to another aspect of the semiconductor memory of the present invention, the plurality of sense amplifiers respectively amplify the parallel read data read from the plurality of memory cells. The switching circuit connects the sense amplifier to a predetermined read amplifier according to an address supplied from the outside. By exchanging the read data before amplification by the read amplifier, the read data first output during the burst read operation can be always amplified by the read amplifier having high driving capability. Therefore, even in the semiconductor memory in which the output order of the read data can be switched according to the address or the operation mode, the read operation time can be shortened and the power consumption can be reduced.

The plurality of read amplifiers amplify the read data amplified by the sense amplifiers to predetermined logic levels. At least one of the read amplifiers has a higher driving capability than the other read amplifiers. A read amplifier with high drive capability can drive the data bus line at a higher speed than other read amplifiers. The switch circuit is arranged close to the read amplifier. The switch circuit transfers the data amplified by the read amplifier to the data bus line in order from the read amplifier with the highest driving capability during the burst read operation in which the parallel read data read from the memory cells are continuously output to the outside in series. Output. That is, the data bus line is
Read data is serially transferred. The data output circuit sequentially outputs the read data transmitted from the switch circuit via the data bus line.

In the burst read operation, since the first read data is amplified by the read amplifier having high driving ability, the read time is shortened. There is a considerable margin before outputting the second and subsequent read data. For example, when the semiconductor memory is a clock synchronous type, there is a margin of at least 1 clock cycle. Therefore, the read amplifier that amplifies the second and subsequent read data can correctly perform the read operation even if the drive capability is low. Since the driving capability of some of the read amplifiers can be lowered, the power consumption during the burst read operation can be reduced.

Since the number of data bus lines can be reduced, the chip size can be reduced. Moreover, since the length of the data line from the read amplifier to the switch circuit can be shortened, the drive capability of the read amplifier can be reduced. As a result, the power consumption can be further reduced.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first semiconductor memory of the present invention.
2 shows an embodiment of the present invention. This embodiment corresponds to claims 1 to 3. Detailed description of the same circuits and signals as in the related art will be omitted. This semiconductor memory is an SDRAM that uses a CMOS process on a silicon substrate.
Is formed as. SDRAM is a column decoder CDE
C, memory cell array ALY, four sense buffers SB1-SB
4 (read amplifier), command decoder CMD, read control circuit RCNT, data output circuit OUT, output control circuit OCNT,
And multiple input buffers BUF that receive signals from external sources
have. Column decoder CDEC, memory cell array
The basic configuration of the ALY and command decoder CMD is the same as that of FIG. 16 described above. The SDRAM has a control circuit that operates according to a row address, a row decoder, and the like, in addition to the illustrated components. In this example, the configuration corresponding to one data terminal DQ will be described, but actually, the path for transmitting the read data DT is formed by the number of bits of the data terminal.

In this embodiment, during the burst read operation, the column decoder CDEC simultaneously activates the column line selection signals CL1-CL4 corresponding to the read data DT output to the outside. That is, the plurality of column switches CSW corresponding to the burst length are simultaneously turned on. Therefore, the local data bus lines DB1-DB4 are formed corresponding to the column switches CSW, respectively. Local data bus line DB1-
DB4 is connected to sense buffers SB1-SB4, respectively.

The sense buffers SB1-SB4 are connected to the common data bus lines CDB1-CDB4, respectively. That is,
The transmission path of the read data DT read from the memory cell MC to the data output circuit OUT is independent. The sense buffer SB1 connected to the local data bus line DB1 shown by a thick frame in the figure has a higher operation speed and a higher driving capability than the other sense buffers SB2-SB4. The common data bus line CDB1 connected to the sense buffer SB1 has a larger wiring width and a smaller wiring resistance than the other common data bus lines CDB2-CDB4. Because of this, the sense buffer
The read data DT amplified by SB1 is transmitted to the data output circuit OUT in a short time. It should be noted that the increase of the wiring capacitance due to the widening of the wiring width is slight (when the width is doubled, the increase of the wiring capacitance is about 1.1 times).

The read control circuit RCNT receives the read control signal RDZ when the decoding result indicates a read command.
To the sense buffer SB1-SB4, and the timing signal EXT
Output PZ and INTPZ to the output control circuit OCNT. The output control circuit OCNT outputs the output timing signals I1Z-I4Z to the data output circuit OUT in synchronization with the timing signals EXTPZ and INTPZ.

FIG. 2 shows details of the sense buffers SB1-SB4 in FIG. The sense buffers SB1-SB4 have a differential amplifier circuit 10a and an output latch 10b. The differential amplifier circuit 10a has two differential input sections composed of nMOS transistors, a current mirror section that supplies a current to the differential input section, and an nMOS transistor that connects the sources of the differential input section to the ground line VSS. ing. Differential amplifier circuit 10a
Are activated when the read control signal RDZ is activated (high level). The output latch 10b is composed of an RS flip-flop.

The differential amplifier circuit 10a receives the positive logic read data DB1Z (or DB2Z-DB4Z) and the negative logic read data DB1X (or DB2X-DB4X) at the respective differential input sections, and executes the amplifying operation. To do. The amplification result is latched by the output latch 10b and output to the common data bus line CDB1 (or CDB2-CDB4). Here, "Z" and "X" at the end of the signal indicate positive logic and negative logic, respectively.

Differential amplifier circuit 10 connected to the ground line VSS
In the nMOS transistor a, the symbol "i" indicates the current consumed when the differential amplifier circuit 10a operates. In the output latch 10b, the symbol "m" indicates the transistor size of the NAND gate. More specifically, the symbol "
m "is the gate width W of the transistor forming the NAND gate
And the channel length L, W / L, and the consumption current (= driving capability) of the output latch 10b. In this embodiment, "i" and "m" of the sense buffer SB1 corresponding to the common data bus line CDB1 are the other common data bus lines CDB
"I" and "" of sense buffer SB2-SB4 corresponding to 2-CDB4
It is designed to be three times as large as m ". In other words, the sense buffer S connected to the common data bus lines CDB2-CDB4.
"I" and "m" of B2-SB4 are 1/3 of the conventional one.

Therefore, the consumption current of the differential amplifier circuit 10a connected to the common data bus line CDB1 is "I", and the consumption current of the differential amplifier circuit 10a connected to the common data bus lines CDB2-CDB4 is "1". / 3 · I ”, four differential amplifier circuits 1
The current consumption of the entire 0a is "2I". Conventionally, the total current consumption of the four differential amplifier circuits 10a is “4I”, which means that the current consumption is reduced to half.

Similarly, the consumption current of the output latch 10b connected to the common data bus line CDB1 is "M", and the consumption current of the output latch 10b connected to the common data bus line CDB2-CDB4 is "1 / 3.M". ", The total current consumption of the four output latches 10b is" 2M ". Conventionally, four output latches 1
The current consumption of the entire 0b is "4M", which means that the current consumption is reduced to half.

Therefore, the current consumption of the entire sense buffers SB1-SB4 can be halved compared to the conventional one. For example, when "I" and "M" are 0.3mA and 0.2mA, respectively, the current consumption of sense buffers SB1-SB4 is 2mA.
1mA which is half of (0.3mA × 4 ＋ 0.2mA × 4) ([0.3mA + 1/3
・ 0.3mA × 3] + [0.2mA + 1/3 ・ 0.2mA × 3]). The reduction amount of the current consumption of the sense buffers SB1-SB4 compared to the conventional one is
An SDRAM with 8 data terminals has a capacity of 8mA (1mA x 8), and an SDRAM with 16 data terminals has a capacity of 16mA (1mA x 8).
16). As described above, according to the present invention, the greater the number of data terminals, the greater the effect of reducing power consumption.

3 and 4 show the details of the output control circuit OCNT. The configuration that combines FIG. 3 and FIG. 4 is the output control circuit OCNT. FIG. 3 shows a 2-bit binary counter in the output control circuit OCNT. This binary counter is a conventionally used circuit such as a refresh address counter. This kind of counter is
Since the counting operation is performed in synchronization with the clock signal (the counting cycle is low), the transistor size is small and the power consumption is also small. Therefore, by arranging the binary counter, the layout size does not increase significantly and the power consumption does not increase significantly.

In FIG. 3, the counters at the front stage and the rear stage are reset by a high level pulse of the timing signal EXTPZ. The counter in the previous stage uses the timing signal INTP
Inverts the level of the counter signal INT1X in synchronization with the rising edge of Z. The counter at the latter stage is the counter signal INT1.
The level of the counter signal INT2X is inverted in synchronization with the falling edge of X.

FIG. 4 shows the output timing signal I1 using the counter signals INT1X and INT2X output from the binary counter.
3 shows a logic circuit for generating Z-I4Z. In this logic circuit, one of the output timing signals I1Z-I4Z changes to a high level according to the levels of the counter signals INT1X and INT2X. FIG. 5 shows the operation of the output control circuit OCNT.
The output control circuit OCNT activates the timing signal EXTPZ for a half clock period in synchronization with the clock signal CLK supplied with the read command RD (FIG. 5A). Further, the output control circuit OCNT activates the timing signal INTPZ for a half clock period in synchronization with the next clock signal CLK sequentially (FIG. 5B). The timing signal INTPZ is activated a number of times smaller than the burst length by one. The binary counter in FIG. 3 operates in synchronization with the timing signals EXTPZ and INTPZ,
The counter signals INT1X and INT2X are output (FIG. 5 (c)).
The logic circuit of FIG. 4 receives the counter signals INT1X and INT2X,
The output timing signals I1Z-I4Z are sequentially set to high level in synchronization with the rising edge of the clock signal CLK (see FIG. 5).
(D)).

FIG. 6 shows details of the data output circuit OUT. In the present invention, the read data DT1 to DT4 of the number corresponding to the burst length “4” are transferred in parallel to the data output circuit OUT. Therefore, it is necessary for the data output circuit OUT to convert the read data DT1 to DT4 in parallel to serial. The data output circuit OUT includes switch circuits 12a, 12b, 12
c, 12d, NAND gate 14, output latch circuit 16, 1
8 and a tri-state output buffer 20. The switch circuits 12a-12d transmit the read data supplied to the common data bus lines CDB1-CDB4 to the NAND gate 14 when the output timing signals I1Z-I4Z are at high level, respectively. Also, the switch circuits 12a-12d
Transmits a high level to the NAND gate 14 when the output timing signals I1Z-I4Z are low level, respectively.

The output timing signals I1Z-I4Z change to only one high level within one clock cycle as shown in FIG. Therefore, the three inputs of the four-input NAND gate 14 are always at the high level. Therefore, when the read data is output, the NAND gate 14 operates as an inverter that inverts the read data supplied to the common data bus lines CDB1-CDB4.

The output latch circuits 16 and 18 are circuits for controlling the pMOS transistor and the nMOS transistor of the output buffer 20, respectively. The output latch circuits 16 and 18 are
The inverted data of the read data output from the NAND gate 14 is taken in when the internal clock signal CLKZ is at a low level, and the taken data is inverted to generate the internal clock signal CL.
Output to the output buffer 20 when KZ is at a high level. The output latch circuits 16 and 18 reset the internal latches and output the high level and the low level, respectively, when the output inhibit signal HZ is at the high level. That is, the output (data terminal DQ) of the output buffer 20 becomes high impedance when the output prohibition signal HZ is at high level.

FIG. 7 shows the burst read operation of the SDRAM described above. In this example, the word line is already activated in response to the row address signal at the start of the timing diagram, and the data DT1-DT4 read from the plurality of memory cells MC are amplified by the sense amplifier SA, respectively. There is. The burst length is set to "4". The read latency is set to "2". Here, the read latency is the number of clocks from the reception of the read command RD to the output of the first read data. In this embodiment, the read control circuit RCNT is
The read control signal RDZ is activated only in the first clock cycle regardless of the burst length, and the sense buffers SB1 to SB4
Operates only in the first clock cycle.

First, the read command RD and the column address (not shown) are supplied in synchronization with the 0th clock signal CLK (FIG. 7A). The read control circuit RCNT in FIG. 1 controls the column decoder CDEC and activates all the column line selection signals CL1-CL4 necessary for the burst read operation (FIG. 7 (b)). Column line selection signals CL1-CL4
The activation of causes the four column switches CSW to turn on,
The read data DT1-DT4 are transmitted to the local data bus lines DB1-DB4, respectively (FIG. 7 (c)).

The read control circuit RCNT has a clock signal CL.
The read control signal RDZ is activated in synchronization with K (Fig. 7).
(D)). By activating the read control signal RDZ,
The sense buffers SB1 to SB4 of 3 simultaneously start operating. Sense buffers SB1-SB4 are local data bus lines DB1-DB4
The above read data DT1-DT4 are amplified to CMOS level respectively, and the amplified data are shared data bus lines CDB1-CDB4
Output to.

In this embodiment, the read control signal RDZ
Is activated only once in one burst read operation. Therefore, when the burst length is "4", the number of operations of the control circuit (for example, the read control circuit RCNT) related to the read control signal RDZ is one fourth of the conventional number.
As a result, the power consumption of these control circuits is 1/4 of the conventional power consumption.
become.

As described with reference to FIG. 2, the common data bus line
The sense buffer SB1 connected to CDB1 has a larger driving capability than the other sense buffers SB2-SB4. Therefore, the common data bus line CDB1 is connected to the other common data bus lines CDB2-CDB4.
It changes faster than that of Fig. 7 (e). That is, the read data DT1 is transmitted to the data output circuit OUT at high speed. The common data bus lines CDB2-CDB4 are read data DT2
-Transmit DT4 at low speed (Fig. 7 (f)). Read data
Since DT2-DT4 are output in the second and subsequent clock cycles, there is no problem even if the transmission speed is slow. Then, the data output circuit OUT outputs the read data DT1 received via the common data bus line CDB1 to the outside in synchronization with the internal clock signal CLKZ (FIG. 7 (g)). The controller (not shown) of the system in which the SDRAM is installed synchronizes the read data with the rising edge of the second clock signal.
Capture DT1 (read latency = "2").

After this, the data output circuit OUT sequentially outputs the read data DT2-DT4 on the common data bus lines CDB2-CDB4 to the outside in synchronization with the first to third internal clock signals CLKZ (FIG. 7 ( h), (i), (j)). As described above, in the present embodiment, the drive capability of the sense buffer SB1 is set higher than the drive capabilities of the other sense buffers SB2-SB4. The data output circuit OUT first outputs the read data DT1 amplified by the sense buffer SB1. Therefore, in the burst read operation, the time until the first read data is output can be shortened.

Since the drive capability of the sense buffers SB2-SB4 is lowered, the power consumption during the burst read operation can be reduced. There is a margin of one clock cycle before the data output circuit outputs the second and subsequent read data. Therefore, even if the driving capability of the sense buffers SB2-SB4 is low, the read data DT2-DT4 can be correctly output in synchronization with the second and subsequent clock cycles.

During the burst read operation, the column switch CSW was turned on in synchronization with the first clock cycle. Since a plurality of column switches CSW can be turned on at the same time, a circuit that controls the column switches CSW can be simply configured. The impedance of the common data bus line CDB1 connected to the sense buffer SB1 having a large driving capability is set lower than that of the other common data bus lines CDB2-CDB4. Therefore, the read data DT1 to be output first can be transmitted to the data output circuit OUT earlier.

FIG. 8 shows a second embodiment of semiconductor memory according to the present invention. This embodiment corresponds to claims 1 to 4. The same circuits and signals as the circuits and signals described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the read control circuit RCNT corresponds to the sense buffers SB1 to SB4, and the read control signals RDZ1 to
Output RDZ4. The activation timings of the read control signals RDZ1-RDZ4 are sequentially shifted. Other configurations are the first
Is the same as the embodiment of.

FIG. 9 shows the burst read operation of the SDRAM in the second embodiment. In this example, the read control signals RDZ1-RDZ4 are sequentially activated (see FIG. 9).
(A)), the start of the operation of the sense buffers SB1 to SB4 is gradually delayed. Therefore, the current consumption of the sense buffers SB1 to SB4 can be dispersed. That is, the peak current during the read operation can be reduced.

The transmission of the read data DT2-DT4 to the common data bus lines CDB2-CDB4 becomes slower than that of the first embodiment (FIG. 9B). However, read data DT2-DT4
Is output in the second and subsequent clock cycles,
There is no problem if the transmission speed is slow. Also in this embodiment, the same effect as that of the above-described first embodiment can be obtained. Furthermore, in this embodiment, the peak current during the burst read operation can be reduced. At this time, the output time of the read data is not delayed unless the activation timing of the read control signal for amplifying the read data output first is changed.

FIG. 10 shows a third embodiment of semiconductor memory according to the present invention. This embodiment corresponds to claims 1 to 3 and claim 5. Regarding the circuits and signals that are the same as the circuits and signals described in the first embodiment,
The same reference numerals are given and detailed description thereof is omitted. In this embodiment, the switching circuit 22 is arranged between the column switch CSW and the sense buffers SB1 to SB4. The switching circuit 22 is a circuit that operates according to the address and data output modes and changes the output order of read data that is continuously output during the burst read operation. The switching circuit 22 connects the local data bus lines DB1-DB4 to any of the data bus lines DBO1-DBO4 in accordance with the mode signals SEQZ, INTZ and the address signals A0Z, A0X, A1Z, A1X. Where the mode signals SEQZ, INTZ
Are signals that are respectively activated in the sequential mode and interleave mode described later. The address signals A0Z, A0X, A1Z and A1X are complementary signals generated from the lower address supplied together with the read command.

The data bus lines DBO1-DBO4 are connected to the common data bus lines CDB1-CDB4 via the sense buffers SB1-SB4, respectively.
It is connected to the. Other configurations are the same as those in the first embodiment. FIG. 11 shows the correspondence between the addresses supplied from the outside and the output order of read data. In this figure, the read data is 4 in one read operation.
In case of continuous output, that is, burst length is "4"
The case is shown. The SDRAM of this embodiment has a sequential mode and an interleave mode in the order of outputting read data.

In the sequential mode, the address signal
When A0 and A1 are "00", "01", "10", and "11", the read data read to the local data bus lines DB1, DB2, DB3, and DB4 are first output. In the subsequent clock cycles, the number at the end of the read local data bus line DB is incremented so that the 2-bit binary counter counts up.

In the interleave mode, the address signal
When A0 and A1 are "00" and "10", the read data output first is the same as in the sequential mode. On the other hand, when the lower addresses A0 and A1 are "01" and "11", the read data of the local data bus lines DB1 and DB3 are output interchangeably. Thus, the local data bus line DB
By switching the connection relationship between 1-DB4 and the common data bus lines CDB1-CDB4, read data is output in a predetermined order.

When the burst length, which is the number of times the read data is continuously output, is set to "1", that is, when the normal read operation is executed instead of the burst read operation, the sense with high driving capability is detected. Buffer SB
Read data is output using only 1 and the common data bus line CDB1 with low resistance (the leftmost column "C" in the figure).
Supports DB1 "). Therefore, normal read operation can be executed at high speed.

12 and 13 show details of the switching circuit 22 for realizing the correspondence shown in FIG. FIG. 12 shows a switching circuit 22a corresponding to the sequential mode, and FIG. 13 shows a switching circuit 22b corresponding to the interleave mode. Switching circuit 2 of FIG.
2a has four switch circuits 22c for connecting one of the local data bus lines DB1-DB4 to the data bus line DBO1 (or DBO2-DBO4) and a logic circuit 22d for controlling these switch circuits 22c. There is. Logic circuit 22d
Has four NAND gates activated by the mode signal SEQZ. NAND gate has address signals A0Z and A0
Decode X, A1Z, A1X. The number entered in the NAND gate indicates the address. When that address is supplied, the NAND gate is activated and outputs a low level. Each switch circuit 22c is activated by activation of the NAND gate.
One of the CMOS transmission gates inside turns on to connect the local data bus line DB and the data bus line DBO. For example,
When the address "00" is supplied, the NAND gate at the top of the figure is activated, and the local data bus lines DB1-DB4 are connected to the data bus lines DBO1-DBO4, respectively. Then, as shown in FIG. 10, the data bus lines DBO1-DBO4 are connected to the common data bus lines CDB1-CDB4 via the sense buffers SB1-SB4.
Connected to.

In the switching circuit 22b of FIG. 13, the logic circuit is activated by the mode signal INTZ indicating the interleave mode. Further, the arrangement of the local data bus lines DB1-DB4 connected to each switch circuit 22c is different from that of the switching circuit 22a described above. The other configuration is the switching circuit 22.
same as a. In the switching circuit 22b, for example, when the address "10" is supplied, the third NAND from the top of the figure
The gate is activated and the local data bus lines DB2, DB1,
DB4 and DB3 are connected to the data bus lines DBO1-DBO4, respectively.

FIG. 14 shows two address generation circuits 24 for generating address signals A0Z, A0X and address signals A1Z, A1X, and a column generation circuit 26 for generating column line selection signals CL1-CL4. Column generation circuit 2
6 is formed in the column decoder CDEC of FIG. The address generation circuit 24 includes a CMOS transmission gate 24a,
Latch 24b, inverters 24c, 24d, and NAND
It has gates 24e and 24f. CMOS transmission gate 2
4a internally transmits the address signal received when the read control signal READZ is at a high level. Latch 24b is CMOS
The address signal A0 (or A1) supplied from the transmission gate 24a is latched. The inverters 24c and 24d output the latched address signal and an inverted signal of the address signal. The NAND gates 24e and 24f are activated except during the burst read mode and output the latched address signal and the inverted signal of the address signal.

Here, the read control signal READZ is as shown in FIG.
This signal is synchronized with the 0 read control signal RDZ. The address generation circuit 24 receiving the address signal A0 always outputs the address signals A0Z and A0X in synchronization with the read control signal READZ, and outputs the address signals A0PZ and A0PX in synchronization with the read control signal READZ except during the burst read operation. To do. In other words, during the burst read operation, the address signals A0PZ and A0PX all change to high level, and during normal read operation that outputs read data according to the address, the address signals A0PZ and A0PX are supplied from the outside. It changes according to the address.

The column generation circuit 26 outputs a read control signal.
A delay circuit 26a for delaying READZ and four A's for decoding the address signals A0PZ and A0PX when the read control signal READZ is activated and outputting them as column line selection signals CL1-CL4
Has an ND circuit. In burst read mode,
Since the address signals A0PZ and A0PX all change to the high level, the column line selection signals CL1-CL4 are read control signals REA.
It is activated simultaneously in synchronization with DZ. Column line selection signal CL
1-CL4 is activated after the delay circuit 26a connects the local data bus lines DB1-DB4 and the data bus lines DBO1-DBO4. That is, by connecting the data bus lines DB and DBO in advance, read data can be transmitted to the sense buffers SB1 to SB4 at high speed.

Also in this embodiment, the same effect as that of the above-mentioned first embodiment can be obtained. Further, in this embodiment, the switching circuit 22 can always amplify the read data first output during the burst read operation by the sense buffer SB1 having a high driving capability. Therefore, even in the SDRAM in which the output order of the read data can be switched according to the address or the operation mode (sequential mode or interleave mode), the read operation time can be shortened and the power consumption can be reduced.

When the burst length is set to "1",
The read data was output by operating the sense buffer SB1 with high driving ability. Therefore, a normal read operation can be executed at high speed. FIG. 15 shows a fourth embodiment of semiconductor memory according to the present invention. This embodiment corresponds to claims 1 to 3 and claims 6 to 9. The same circuits and signals as the circuits and signals described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the memory cell array ALY
Are divided corresponding to the data terminals DQ.
Further, in order to output the read data to the outside, the same circuits and signal lines as in the first embodiment are formed for each section. These circuits, the signal lines, and the divided memory cell array ALY form a plurality of blocks. The blocks are arranged along the arrangement direction (first direction) of the data terminals DQ.

For example, in the block corresponding to the data terminal DQ0, there are four sense buffers SB1-SB4, four local data bus lines DB01-DB04, and four common data bus lines CDB.
01-CDB04 and the data output circuit OUT are formed, and the column line selection signals CL01-CL04 are supplied to the memory area. The second number from the end of the signal line and the signal indicates the number of the data terminal DQ. Like the first embodiment, the sense buffer SB1 indicated by a thick frame is designed to have a higher driving capability than the other sense buffers SB2-SB4.

Common data bus lines CDB01-CDB04 are arranged along a second direction orthogonal to the first direction. Direction of read data transmission path and common data bus line CDB0
Since the wiring directions of 1-CDB04 are the same, the common data bus lines CDB01-CDB04 can be efficiently wired and the wiring length can be shortened. Further, since the blocks are arranged along the arrangement direction of the data terminals DQ, it is possible to arrange the blocks corresponding to the respective data terminals DQ near the respective data terminals DQ, and the common data bus line The wiring length can be further shortened.

The memory cell array ALY is divided into two memory areas in the vertical direction of the drawing for each section. Then, the banks BK0 and BK1 are formed by the memory regions arranged in the horizontal direction in the figure.
Are formed. The banks BK0 and BK1 can operate independently. By combining the memory cells corresponding to each DQ into one area to form a memory area and further configuring banks BK0 and BK1 at the top and bottom of the figure, both banks BK0 and BK1
The read data read from can be easily transmitted to the common data bus line CDB wired in the vertical direction in the figure. As a result, the wiring length of the common data bus line CDB can be minimized, and the wiring resistance and wiring capacitance can be reduced. Therefore, the sense buffer S that drives the common data bus line CDB
The drive capacity of B1-SB4 can be reduced and the power consumption during read operation can be reduced. When the driving capabilities of the sense buffers SB1 to SB4 are the same as those in the first embodiment, the read operation time can be shortened.

Also in this embodiment, the same effect as that of the above-mentioned first embodiment can be obtained. Further, in this embodiment, blocks are formed corresponding to the data terminals DQ, respectively. Therefore, even in a so-called multi-bit SDRAM having a plurality of data terminals, the read operation time can be shortened and the power consumption can be reduced. The blocks respectively corresponding to the data terminals DQ are arranged along the arrangement direction (first direction) of the data terminals DQ, and the common data bus line CDB is arranged along the second direction orthogonal to the first direction. . Therefore, the wiring length of the data bus line can be minimized, and the wiring resistance and wiring capacitance of the data bus line can be minimized. As a result, the read operation time can be further shortened and the power consumption can be reduced.

The memory cell array ALY in each block is
Divided into a plurality of memory areas along the second direction, a plurality of banks BK0 and BK1 that can operate independently are formed by the memory areas arranged in the first direction. Therefore, read data read from the memory cell can be transmitted only by the wiring along the second direction. As a result, the signal line such as a data bus line for transmitting read data can be minimized, and the read operation time can be further shortened.

FIG. 16 shows a fifth embodiment of semiconductor memory according to the present invention. This embodiment corresponds to claims 1 to 6. The same circuits and signals as the circuits and signals described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, the read control circuit RCNT corresponds to the sense buffers SB1 to SB4, and the read control signals RCNT are respectively provided.
Output DZ1-RDZ4. The activation timings of the read control signals RDZ1 to RDZ4 are sequentially shifted as in the second embodiment (FIG. 9) described above. Other configurations are the same as those in the third embodiment.

Also in this embodiment, the above first to first
The same effect as that of the third embodiment can be obtained. Figure 1
7 shows a sixth embodiment of the semiconductor memory of the present invention. This embodiment corresponds to claims 1 to 3 and claims 6 to 9. Regarding the same circuit / signal as the circuit / signal described in the above embodiment,
The same reference numerals are given and detailed description thereof is omitted.

In this embodiment, the fourth embodiment (FIG. 1) is used.
The switching circuit 22 of the third embodiment (FIG. 10) is arranged between the memory cell array ALY partitioned corresponding to the data terminal DQ of 5) and the sense buffers SB1 to SB4. Other configurations are the same as those in the fourth embodiment. Also in this embodiment, the same effects as those of the above-described first, third, and fourth embodiments can be obtained.

FIG. 18 shows a semiconductor memory according to a seventh embodiment of the present invention. This embodiment corresponds to claims 1 to 3 and claims 6 to 10. The same circuits and signals as the circuits and signals described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the first
A part of the data output circuit OUT (FIG. 6) of the above embodiment is arranged at a position close to the sense buffers SB1 to SB4. That is, the switch circuits 12a, 12b, 12c, 12d (second switch circuit) and the NAND gate 14 of FIG. 6 are arranged near the sense buffers SB1-SB4. The data output circuit OUT1 is composed of output latch circuits 16 and 18 and a tri-state output buffer 20. Other configurations are the same as those in the fourth embodiment.

In this embodiment, the sense buffers SB1-SB
Data output circuit OUT1 from 4 (to be exact, NAND gate 14)
By connecting one common data bus line CDB to the read data, the read data amplified by the sense buffers SB1 to SB4 can be transmitted to the data output circuit OUT1. Also in this embodiment, the same effects as those of the above-described third embodiment can be obtained. Furthermore, since the number of common data bus lines CDB can be reduced, the chip size can be reduced. In addition, the common data bus lines CDB1- driven by the sense buffers SB1-SB4
Since the length of CDB4 can be shortened, the sense buffer SB1-SB4
Drivability can be reduced. As a result, power consumption can be reduced.

In the above-described first embodiment (FIG. 1), the read data output from the sense buffers SB1-SB4 are transmitted to the data output circuit OUT via the common data bus lines CDB1-CDB4, respectively. The example in which the switch circuits 12a to 12d in the data output circuit OUT perform parallel / serial conversion has been described. The present invention is not limited to such an embodiment. For example, the switch circuits 12a to 1 shown in FIG.
2d and NAND gate 14 are connected to sense buffers SB1-SB4
It is also possible to arrange read data which is arranged in close proximity to and which has undergone parallel / serial conversion to output to the data output circuit OUT via one common data bus line. In this case, as in the first embodiment,
The power consumption during burst read operation can be reduced. Furthermore, since the number of common data bus lines can be reduced, the chip size can be reduced.

In the above embodiment, the common data bus line is used.
The example in which the wiring resistance is lowered by making the wiring width of CDB1 larger than the wiring widths of the other common data bus lines CDB2-CDB4 has been described. The present invention is not limited to such an embodiment. For example, the wiring resistance and the wiring capacitance may be lowered by changing the material of the wiring between the common data bus line CDB1 and the other common data bus lines CDB2-CDB4. Alternatively, the wiring resistance and the wiring capacitance may be lowered by changing the wiring layer of the common data bus line CDB1 and the other common data bus lines CDB2-CDB4. In this case, the common data bus line CDB1 may be formed of metal wiring, and the common data bus lines CDB2-CDB4 may be formed of polysilicon wiring.

The invention described in the above embodiments is organized and disclosed as a supplement. (Supplementary Note 1) A plurality of memory cells, a plurality of sense amplifiers for amplifying parallel read data read from the memory cells, and the read data amplified by the sense amplifiers are respectively amplified to predetermined logic levels, A plurality of read amplifiers having at least one driving capability higher than the other driving capability, a switching circuit for connecting the sense amplifier to a predetermined read amplifier according to an address supplied from the outside, and read data continuously externally. A read data amplified by the read amplifier in the burst read operation to be output to the read amplifier, the data output circuit sequentially outputting the read data corresponding to the read amplifier having high driving capability, the read amplifier, and the data output circuit. And a plurality of data bus lines respectively connecting Characteristic semiconductor memory.

(Supplementary Note 2) In the semiconductor memory according to Supplementary Note 1, only one of the read amplifiers has a larger driving capability than the other read amplifiers. (Supplementary Note 3) In the semiconductor memory according to Supplementary Note 1, the height of the driving capability of the read amplifier is adjusted by the size of a transistor forming the read amplifier.

(Supplementary Note 4) In the semiconductor memory according to Supplementary Note 1, the data output circuit includes a parallel-serial conversion circuit that serially outputs the parallel read data output from the read amplifier. Semiconductor memory. (Supplementary Note 5) In the semiconductor memory according to supplementary note 1, there is provided a plurality of column switches that respectively connect the sense amplifier and the read amplifier, and the column switch includes:
During the burst read operation, the semiconductor memory is turned on in the first clock cycle of the read operation and simultaneously transmits the read data to the read amplifier.

(Supplementary Note 6) In the semiconductor memory according to Supplementary Note 1, it is preferable that the data bus line connected to the read amplifier having a large driving capability has a lower impedance than the data bus line connected to another read amplifier. Characteristic semiconductor memory. (Supplementary Note 7) In the semiconductor memory according to Supplementary Note 6, the impedance is adjusted by a wiring width of the data bus line.

(Supplementary Note 8) In the semiconductor memory according to Supplementary Note 6, the data bus line is adjusted by a material of a wiring forming the data bus line. (Supplementary note 9) The semiconductor memory according to supplementary note 8, comprising a plurality of wiring layers formed on a semiconductor substrate, wherein the impedance is adjusted according to a type of a wiring layer in which the data bus line is formed. A semiconductor memory characterized by.

(Supplementary Note 10) In the semiconductor memory according to supplementary note 1, a read control circuit for generating a plurality of read control signals for respectively activating the read amplifiers is provided, and the read control corresponding to the read amplifiers having high driving capability is provided. The signal is activated prior to the other read control signals.

(Supplementary Note 11) In the semiconductor memory according to Supplementary Note 10, the switching circuit connects the sense amplifier to a predetermined read amplifier according to an operation mode for setting an output order of the address and the read data. A semiconductor memory characterized by. (Supplementary Note 12) In the semiconductor memory according to supplementary note 1, when the burst length, which is the number of times the read data is continuously output, is set to a single value, only the read amplifier having high driving capability is operated to transfer data A semiconductor memory characterized by outputting.

(Supplementary Note 13) In the semiconductor memory according to supplementary note 1, a plurality of blocks each having the memory cell, the sense amplifier, the read amplifier, the data output circuit, and the data bus line, each block corresponding to a data terminal. A semiconductor memory comprising: (Supplementary Note 14) In the semiconductor memory according to supplementary note 13,
The semiconductor memory according to claim 1, wherein the blocks are arranged along a first direction, and the data bus lines are arranged along a second direction orthogonal to the first direction.

(Supplementary Note 15) The semiconductor memory according to Supplementary Note 14, wherein the first direction is an arrangement direction of the data terminals. (Additional remark 16) In the semiconductor memory according to additional remark 14,
Each of the blocks is divided into a plurality of memory areas along the second direction, and the memory areas arranged in the first direction form independently operable banks. Semiconductor memory.

(Supplementary Note 17) A plurality of memory cells, a plurality of sense amplifiers for amplifying parallel read data read from the memory cells, and the read data amplified by the sense amplifiers are set to predetermined logic levels. A plurality of read amplifiers that amplify and have at least one driving capability higher than other driving capabilities, a switching circuit that connects the sense amplifier to a predetermined read amplifier according to an address supplied from the outside, and the read amplifier. During a burst read operation in which adjacent read data are continuously output to the outside, the parallel read data amplified by the read amplifier are sequentially read from the read data corresponding to the read amplifier having high driving capability. Output to the switch circuit and the reading output from the switch circuit A semiconductor memory, comprising: a data output circuit for outputting output data; and a data bus line connecting the switch circuit and the data output circuit.

Although the present invention has been described in detail above, the above-described embodiments and modifications thereof are merely examples of the invention, and the invention is not limited thereto. Obviously, modifications can be made without departing from the invention.

[0088]

According to the semiconductor memory of the first aspect, in the burst read operation, the time until the first read data is output can be shortened, and at the same time, the power consumption can be reduced. Even in a semiconductor memory that can switch the output order of read data according to an address or an operation mode,
The read operation time can be shortened and the power consumption can be reduced. According to another aspect of the semiconductor memory of the present invention, the circuit for controlling the column switch can be simplified.

In the semiconductor memory of the third aspect, the read data output first can be transmitted to the data output circuit more quickly. According to the semiconductor memory of the fourth aspect, the peak current at the burst read operation can be reduced. On this occasion,
The output time of the read data is not delayed unless the activation timing of the read control signal for amplifying the read data output first is changed.

According to the semiconductor memory of the fifth aspect, not only the burst read operation but also the normal read operation can be executed at high speed. According to the semiconductor memory of the sixth aspect, even in the semiconductor memory having a plurality of data terminals, the read operation time can be shortened and the power consumption can be reduced. According to the semiconductor memory of claims 7 and 8, the wiring length of the data bus line can be minimized, and the wiring resistance and wiring capacitance of the data bus line can be minimized. As a result, the read operation time can be further shortened and the power consumption can be reduced.

According to the semiconductor memory of claim 9, the signal line such as the data bus line for transmitting the read data can be minimized,
The read operation time can be further shortened. Claim 10
In the semiconductor memory of, in the burst read operation,
The time until the first read data is output can be shortened, and at the same time the power consumption can be reduced. Even in a semiconductor memory in which the output order of read data can be switched according to an address or an operation mode, the read operation time can be shortened and the power consumption can be reduced.

Since the number of data bus lines can be reduced, the chip size can be reduced. Since the drive capability of the read amplifier can be reduced, power consumption can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment.

2 is a circuit diagram showing details of a sense buffer of FIG. 1. FIG.

FIG. 3 is a circuit diagram showing details of the output control circuit of FIG.

FIG. 4 is a circuit diagram showing details of the output control circuit of FIG.

5 is a timing diagram showing an operation of the output control circuit of FIG.

6 is a circuit diagram showing details of the data output circuit of FIG.

FIG. 7 is a timing chart showing a burst read operation according to the first embodiment.

FIG. 8 is a block diagram showing a second embodiment.

FIG. 9 is a timing chart showing a burst read operation of the second embodiment.

FIG. 10 is a block diagram showing a third embodiment.

FIG. 11 is an explanatory diagram showing correspondence between addresses and output order of read data.

12 is a circuit diagram showing details of the switching circuit of FIG.

13 is a circuit diagram showing details of the switching circuit of FIG.

FIG. 14 is a circuit diagram showing details of an address generation circuit and a column generation circuit according to a third embodiment.

FIG. 15 is a block diagram showing a fourth embodiment.

FIG. 16 is a block diagram showing a fifth embodiment.

FIG. 17 is a block diagram showing a sixth embodiment.

FIG. 18 is a block diagram showing a seventh embodiment.

FIG. 19 is a block diagram showing an outline of a conventional SDRAM.

FIG. 20 is a timing diagram showing a conventional read operation.

[Explanation of symbols]

10a differential amplifier circuit 10b output latch 12a, 12b, 12c, 12d switch circuit 14 NAND gate 16, 18 output latch circuit 20 output buffers 22 Switching circuit 24 address generation circuit 26 Column generation circuit BUF input buffer ALY memory cell array BK0, BK1 banks CDB1-CDB4 Common data bus line CDEC column decoder CL1-CL4 Column line selection signals CLK clock signal CMD command decoder CSW column switch DB1-DB4 Local data bus line DQ data terminal DT, DT1-DT4 Read data EXTPZ timing signal I1Z-I4Z output timing signal INTPZ timing signal MC memory cell OCNT output control circuit OUT data output circuit RCNT read control circuit RDZ read control signal SA sense amplifier SB1-SB4 Sense buffer

Claims (10)

[Claims] 1. A plurality of memory cells, a plurality of sense amplifiers for respectively amplifying parallel read data read from the memory cells, and each of the read data amplified by the sense amplifiers is amplified to a predetermined logic level. , A plurality of read amplifiers having at least one drive capability higher than other drive capabilities, a switching circuit connecting the sense amplifier to a predetermined read amplifier according to an address supplied from the outside, and read data continuously. A data output circuit that sequentially outputs the read data amplified by the read amplifier from the read data corresponding to the read amplifier having a high driving capability during a burst read operation to be output to the outside, the read amplifier and the data output And a plurality of data bus lines respectively connecting to the circuit Semiconductor memory, wherein the door. 2. The semiconductor memory according to claim 1, further comprising a plurality of column switches that respectively connect the sense amplifier and the read amplifier, wherein the column switch is the first of a read operation during the burst read operation. Turns on in a clock cycle,
A semiconductor memory, wherein the read data is simultaneously transmitted to the read amplifier. 3. The semiconductor memory according to claim 1, wherein the data bus line connected to the read amplifier having a large driving capability has a lower impedance than the data bus line connected to another read amplifier. And semiconductor memory. 4. The semiconductor memory according to claim 1, further comprising a read control circuit that generates a plurality of read control signals that activate each of the read amplifiers, the read control signal corresponding to the read amplifier having high driving capability. Are activated prior to the other read control signals. 5. The semiconductor memory according to claim 1, wherein when the burst length, which is the number of times the read data is continuously output, is set to a single value, only the read amplifier having high driving capability is operated, A semiconductor memory characterized by outputting data. 6. The semiconductor memory according to claim 1, further comprising a plurality of blocks each having the memory cell, the sense amplifier, the read amplifier, the data output circuit, and the data bus line, each block corresponding to a data terminal. A semiconductor memory characterized by being provided. 7. The semiconductor memory according to claim 6, wherein the blocks are arranged along a first direction, and the data bus lines are arranged along a second direction orthogonal to the first direction. A semiconductor memory characterized in that 8. The semiconductor memory according to claim 7, wherein the first direction is an array direction of the data terminals. 9. The semiconductor memory according to claim 7, wherein each of the blocks is divided into a plurality of memory areas along the second direction, and the blocks are independently arranged by the memory areas arranged in the first direction. A semiconductor memory having a plurality of operable banks formed therein. 10. A plurality of memory cells, a plurality of sense amplifiers for amplifying parallel read data read from the memory cells, respectively, and amplifying the read data amplified by the sense amplifiers to a predetermined logic level. A plurality of read amplifiers having at least one driving capability higher than other driving capabilities, a switching circuit connecting the sense amplifier to a predetermined read amplifier according to an address supplied from the outside, and a read circuit close to the read amplifier. The burst read operation that continuously outputs read data to the external
A switch circuit that sequentially outputs the parallel read data amplified by the read amplifier in order from the read data corresponding to the read amplifier having high driving capability, and data that outputs the read data output from the switch circuit. A semiconductor memory, comprising: an output circuit; and a data bus line connecting the switch circuit and the data output circuit.