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JP2003114242A - Integrated circuit - Google Patents

Integrated circuit

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Publication number
JP2003114242A
JP2003114242A JP2001308563A JP2001308563A JP2003114242A JP 2003114242 A JP2003114242 A JP 2003114242A JP 2001308563 A JP2001308563 A JP 2001308563A JP 2001308563 A JP2001308563 A JP 2001308563A JP 2003114242 A JP2003114242 A JP 2003114242A
Authority
JP
Japan
Prior art keywords
voltage
circuit
delay time
delay
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001308563A
Other languages
Japanese (ja)
Inventor
Koichi Yamazaki
浩一 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2001308563A priority Critical patent/JP2003114242A/en
Publication of JP2003114242A publication Critical patent/JP2003114242A/en
Withdrawn legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Control Of Voltage And Current In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit capable of selecting a different delay time without changing the inside. SOLUTION: A potential dividing circuit comprising resistances 102, 103 connected in series is constituted between external terminals VDD, VSS, and connected to the minus input terminal of a voltage comparator 104. The plus input terminal of the voltage comparator 104 is connected to a reference voltage circuit 101, and the output terminal is connected to a delay circuit 105. The delay circuit 105 has terminals CTL1, CTL2 for setting the delay time and can select the terminal as the need arises.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路に関す
る。
FIELD OF THE INVENTION The present invention relates to integrated circuits.

【0002】[0002]

【従来の技術分野】従来の集積回路は図2に示すような
回路である。これは、電源電圧を印加するために設けら
れた端子VDDと、VSSの間に直列に接続されている
抵抗202、抵抗203、からなる分圧回路と、一定電
圧を発生することのできる基準電圧発生回路201と、
電圧比較回路204と、遅延回路205で構成される。
電圧比較回路204は、複数のトランジスタからなり、
該分圧回路によって分圧された分圧電圧と基準電圧発生
回路201から発生された基準電圧を比較して、該分圧
電圧が該基準電圧よりも高い場合はHiが、逆に低い場
合はLoが出力されるものである。遅延回路205は、
電圧比較回路204の出力がHiからLo,あるいはL
oからHiに遷移した時に、一定の遅延時間を設け端子
VOUTをHiからLo,あるいはLoからHiに遷移
させるものである。
2. Description of the Related Art A conventional integrated circuit is a circuit as shown in FIG. This is a voltage dividing circuit composed of a resistor 202 and a resistor 203 connected in series between a terminal VDD provided to apply a power supply voltage and VSS, and a reference voltage capable of generating a constant voltage. A generation circuit 201,
It is composed of a voltage comparison circuit 204 and a delay circuit 205.
The voltage comparison circuit 204 includes a plurality of transistors,
The divided voltage divided by the voltage dividing circuit is compared with the reference voltage generated by the reference voltage generating circuit 201. If the divided voltage is higher than the reference voltage, Hi is, and conversely, if it is low. Lo is output. The delay circuit 205 is
The output of the voltage comparison circuit 204 changes from Hi to Lo, or L
When a transition is made from o to Hi, a certain delay time is provided and the terminal VOUT is transitioned from Hi to Lo or from Lo to Hi.

【0003】[0003]

【発明が解決しようとする課題】従来の集積回路では、
遅延回路を集積回路に内蔵した場合、外部から遅延時間
を選択することが出来ないため、必要に応じて異なった
遅延時間を設定するには、集積回路の内部を変更する必
要があった。
In the conventional integrated circuit,
When the delay circuit is built in the integrated circuit, the delay time cannot be selected from the outside, so that it is necessary to change the inside of the integrated circuit in order to set different delay times as needed.

【0004】また出荷検査時には、特に遅延時間が長い
場合に検査時間も長くなってしまうという課題があっ
た。
Further, at the time of shipping inspection, there is a problem that the inspection time also becomes long especially when the delay time is long.

【0005】[0005]

【課題を解決するための手段】上記の課題を解決するた
めに、外部に端子を設け遅延時間を選択できる構成にし
た。
In order to solve the above problems, an external terminal is provided so that the delay time can be selected.

【0006】[0006]

【発明の実施の形態】以下、本発明の実施例を図面を用
いて説明する。図1は本発明である電圧検出回路の回路
図である。外部端子VDDとVSSの間に直列に接続さ
れている抵抗102、抵抗103とがあり、入力された
電源電圧を所定の比率で分割することができる分圧回路
で構成されている。抵抗102と抵抗103との接合部
は、電圧比較回路104の−入力端子と接続されてい
る。一方、電源電圧の大きさに関係なく一定の基準電圧
を発生することのできる基準電圧回路101は電圧比較
回路104の+入力端子と接続されている。また遅延回
路105を付加して外部端子CTL1,CTL2を設
け、遅延時間を選択できるようにしてある。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a voltage detection circuit according to the present invention. There is a resistor 102 and a resistor 103 connected in series between the external terminals VDD and VSS, and the resistor 102 and the resistor 103 are composed of a voltage dividing circuit capable of dividing the input power supply voltage at a predetermined ratio. The junction between the resistors 102 and 103 is connected to the negative input terminal of the voltage comparison circuit 104. On the other hand, the reference voltage circuit 101 capable of generating a constant reference voltage regardless of the magnitude of the power supply voltage is connected to the + input terminal of the voltage comparison circuit 104. Further, a delay circuit 105 is added to provide external terminals CTL1 and CTL2 so that the delay time can be selected.

【0007】動作は、外部端子VSSをGNDとして、
外部端子VDDから入力された電圧は抵抗102、抵抗
103からなる該分圧回路で分圧される。この分圧され
た電圧は、電圧比較回路104において基準電圧発生回
路101で発生される基準電圧と比較される。ここで該
分圧電圧が基準電圧回路101よりも高くなった時、電
圧比較回路104はLoからHiに遷移するが、遅延回
路105により設定された遅延時間後に、VOUTがL
oからHiに遷移する。
In operation, the external terminal VSS is set to GND,
The voltage input from the external terminal VDD is divided by the voltage dividing circuit including the resistors 102 and 103. The divided voltage is compared with the reference voltage generated by the reference voltage generation circuit 101 in the voltage comparison circuit 104. Here, when the divided voltage becomes higher than the reference voltage circuit 101, the voltage comparison circuit 104 makes a transition from Lo to Hi, but VOUT becomes L after the delay time set by the delay circuit 105.
Transition from o to Hi.

【0008】遅延時間の設定はCTL1,CTL2とも
にOPEN状態では4秒、CTL1がLoレベル,CT
L2がOPEN状態では1秒、CTL1がOPEN,C
TL2がLoレベルでは0.25秒, CTL1,CT
L2ともにLoレベルでは遅延時間無しと、必要に応じ
て選択することができるようになっている。特に出荷検
査では遅延時間無しにすることで、検査時間を短縮して
いる。
The delay time is set to 4 seconds when both CTL1 and CTL2 are in the OPEN state, CTL1 is at the Lo level and CT is set.
1 second when L2 is OPEN, CTL1 is OPEN, C
When TL2 is Lo level, 0.25 seconds, CTL1, CT
For both L2 and Lo level, there is no delay time, and it can be selected as needed. Especially in shipping inspection, the inspection time is shortened by eliminating the delay time.

【0009】以上のように、遅延回路を集積回路に内蔵
した場合、外部から遅延時間を選択することが出来ない
ため、必要に応じて異なった遅延時間に設定するには、
集積回路の内部を変更する必要があるという課題を解決
している。ここまでの実施例は外部端子を2つの場合で
説明してきたが、外部端子数には制限はない。
As described above, when the delay circuit is built in the integrated circuit, the delay time cannot be selected from the outside. Therefore, to set different delay times as needed,
It solves the problem of having to change the inside of the integrated circuit. Although the embodiments so far have been described with two external terminals, the number of external terminals is not limited.

【0010】本実施例は集積回路であれば、C−MOS
(Complementaly Metal Oxid
e Semiconducter)回路、バイポーラト
ランジスタ回路などに限定することはなく、実現は容易
である。
If the present embodiment is an integrated circuit, it is a C-MOS.
(Complementary Metal Oxid
However, the invention is not limited to an eSemiconductor) circuit, a bipolar transistor circuit, and the like, and the realization is easy.

【0011】[0011]

【発明の効果】本発明の集積回路は、外部に端子を設け
遅延時間を選択できる構成にして、必要に応じて異なっ
た遅延時間に設定するには、集積回路の内部を変更する
必要をなくすという効果がある。
The integrated circuit of the present invention has a structure in which an external terminal is provided and a delay time can be selected, and it is not necessary to change the inside of the integrated circuit in order to set different delay times as needed. There is an effect.

【0012】また出荷検査時には、特に遅延時間が長い
場合に検査時間を短く出来るという効果がある。
Further, at the time of shipping inspection, there is an effect that the inspection time can be shortened especially when the delay time is long.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の集積回路図FIG. 1 is an integrated circuit diagram of the present invention.

【図2】従来の集積回路を示す図FIG. 2 is a diagram showing a conventional integrated circuit.

【符号の説明】[Explanation of symbols]

101 基準電圧回路 102 抵抗 103 抵抗 104 電圧比較回路 105 遅延回路 201 基準電圧回路 202 抵抗 203 抵抗 204遅延回路 101 Reference voltage circuit 102 resistance 103 resistance 104 Voltage comparison circuit 105 delay circuit 201 Reference voltage circuit 202 resistance 203 resistance 204 delay circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 電圧を所定の比率で分割することのでき
る電圧分割回路と、電圧の大きさに関係なく一定の基準
電圧を発生することのできる基準電圧発生回路と、入力
された該基準電圧と分圧回路にて分圧された電圧との大
きさを比較して出力信号を切り替えることができる電圧
比較回路と、電圧検出に遅延時間を持たせる遅延回路か
ら構成された、特定の電圧を検出することのできる遅延
付き電圧検出回路において、別に用意された端子の状態
により遅延時間を選択できることを特徴とする集積回
路。
1. A voltage dividing circuit capable of dividing a voltage at a predetermined ratio, a reference voltage generating circuit capable of generating a constant reference voltage regardless of the magnitude of the voltage, and the input reference voltage. And the voltage divided by the voltage dividing circuit, the output voltage can be compared by switching the output signal, and the voltage detection circuit has a delay time. An integrated circuit characterized in that a delay time can be selected according to the state of a separately prepared terminal in a voltage detection circuit with a delay that can be detected.
【請求項2】 電圧を所定の比率で分割することのでき
る電圧分割回路と、電圧の大きさに関係なく一定の基準
電圧を発生することのできる基準電圧発生回路と、入力
された該基準電圧と分圧回路にて分圧された電圧との大
きさを比較して出力信号を切り替えることができる電圧
比較回路と、電圧検出に遅延時間を持たせる遅延回路か
ら構成された、特定の電圧を検出することのできる遅延
付き電圧検出回路において、別に用意された端子の状態
により遅延時間を選択できることを特徴とする回路を含
む、二次電池保護用集積回路。
2. A voltage dividing circuit capable of dividing a voltage at a predetermined ratio, a reference voltage generating circuit capable of generating a constant reference voltage regardless of the magnitude of the voltage, and the input reference voltage. And the voltage divided by the voltage dividing circuit, the output voltage can be compared by switching the output signal, and the voltage detection circuit has a delay time. A secondary battery protection integrated circuit including a circuit capable of detecting a delay time in a voltage detection circuit with a delay that can be detected according to a state of a separately prepared terminal.
【請求項3】 電圧を所定の比率で分割することのでき
る電圧分割回路と、電圧の大きさに関係なく一定の基準
電圧を発生することのできる基準電圧発生回路と、入力
された該基準電圧と分圧回路にて分圧された電圧との大
きさを比較して出力信号を切り替えることができる電圧
比較回路と、電圧検出に遅延時間を持たせる遅延回路か
ら構成された、特定の電圧を検出することのできる遅延
付き電圧検出回路において、別に用意された端子の状態
により遅延時間を選択できることを特徴とする回路を含
む、集積回路。
3. A voltage dividing circuit capable of dividing a voltage at a predetermined ratio, a reference voltage generating circuit capable of generating a constant reference voltage regardless of the magnitude of the voltage, and the input reference voltage. And the voltage divided by the voltage dividing circuit, the output voltage can be compared by switching the output signal, and the voltage detection circuit has a delay time. An integrated circuit including a voltage detection circuit with delay capable of detecting, wherein the delay time can be selected according to the state of a separately prepared terminal.
JP2001308563A 2001-10-04 2001-10-04 Integrated circuit Withdrawn JP2003114242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001308563A JP2003114242A (en) 2001-10-04 2001-10-04 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001308563A JP2003114242A (en) 2001-10-04 2001-10-04 Integrated circuit

Publications (1)

Publication Number Publication Date
JP2003114242A true JP2003114242A (en) 2003-04-18

Family

ID=19127853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001308563A Withdrawn JP2003114242A (en) 2001-10-04 2001-10-04 Integrated circuit

Country Status (1)

Country Link
JP (1) JP2003114242A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10436856B2 (en) 2015-12-24 2019-10-08 Asahi Kasei Microdevices Corporation Magnetic sensor apparatus and current sensor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10436856B2 (en) 2015-12-24 2019-10-08 Asahi Kasei Microdevices Corporation Magnetic sensor apparatus and current sensor apparatus

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