JP2003111400A - High voltage power supply control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a protection operation when an output of a high-voltage power supply controlled by a sub PWM method is abnormal, and to realize a soft recovery at an automatic recovery. In a power supply that outputs a high voltage by switching of pulse width control (PWM), a high voltage transformer, a transistor for driving the high voltage transformer, a secondary output rectifying and smoothing circuit of the high voltage transformer, a high voltage output voltage detecting means, A sub-PWM for constant voltage control of an output by comparing an output voltage detected by the high voltage output voltage detecting means with a voltage generated by the D / A converter for generating a reference voltage;
And a circuit, wherein when the output abnormality detecting means detects the output abnormality, the pulse supplied to the main high-voltage transformer driving transistor is reduced by lowering the frequency of the oscillator to suppress the output.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a control method for a high voltage power supply.

[0002]

2. Description of the Related Art FIG. 4 shows a typical circuit example of a multi-output high-voltage power supply with pulse width control. A main PWM system that can accurately output the target output by monitoring the output voltage in a short cycle and controlling the switching on the input side, and the switching transistor on the input side using the switching pulse generated by the main PWM The result of detecting the output voltage by switching and the target reference voltage are set in the main P
It is equipped with a sub-PWM system that performs a comparison in a cycle slower than WM and switches the transistor connected to the output side according to the result to roughly control the output voltage. One main PWM for outputs requiring precision and multiple sub-Ps for other outputs
It has a configuration with a WM.

To explain the circuit operation, the transistor Q1
The high voltage transformer T1 is driven by intermittently switching the high voltage pulse, and the high voltage pulse appearing on the output side is rectified (D
1), a high voltage DC output is generated by smoothing (C1). The high-voltage output is detected by the detection resistance, and the resistance-divided value and the design target value Vref1 are compared by the comparator CP1. Whether the output voltage is higher or lower than the reference value Vref1 is determined by the output value of CP1. When the output is high, the up / down counter UD / C decrements the output value by one from the previous output value, and vice versa. If it is low, increase by one. The waveform is shown in FIG. Output values from the UD / C are indicated by n1, n2, n3 ... In the figure. The output of the oscillator OSC is connected to the down counter D / C, which is the OSC.
The output value from the UD / C is decreased one by one at every cycle time s of the output from. The output value from this counter is input to the comparator CP2 and compared with the reference value m for determining the off width from the CPU. When the reference value for determining the off width is smaller than the counter output, the pulse is turned on, and in the opposite case, it is turned off so that the off width is always constant and the on width is variable.
WM output is realized. The square wave at the bottom of the figure shows the output of CP2.

Explaining the sub PWM, the reference voltage of the comparator is determined by the output state once in several cycles of the main PWM, and the reference voltage of the comparator is compared with the detected value of the output voltage to determine the secondary side of the transformer. The connected transistor is turned on and off to finely adjust the output voltage. The drive pulse for the transformer drive is the main PW to simplify the circuit.
The output pulse of M is commonly used.

When an output is monitored and an abnormality such as an overvoltage or an overcurrent is detected, the output value of the conventional UD / C is manipulated to reduce the output. Once the output drops, it will be out of the abnormality detection. Therefore, the next time UD / C is output, a hard start-up will occur in an attempt to output the specified value.

[0006]

When the output of the high-voltage power supply becomes abnormal, the voltage may be high, and in the worst case, there is a danger of electric shock to the operator or fire. In the conventional circuit, there is a case in which the surge voltage or the inrush current becomes a problem when the recovery is hard after the abnormality is detected and the automatic recovery is performed. Also, a soft start in which the output value of UD / C is gradually increased is conceivable, but even in this case, it is a stepwise start depending on the oscillation cycle of the oscillator, and a gentle soft start cannot be finely set.

[0007]

According to the present invention, in order to solve the above problems, when an output abnormality is detected, not the UD / C output value but the oscillation frequency of the oscillator and the PWM off-width setting reference value are changed. Therefore, the output is reduced, and the automatic return is characterized by returning to software by changing two parameters.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a circuit block diagram showing a first embodiment of the present invention, and FIG. 2 shows waveforms at various parts during a protection operation.

When the abnormality detection circuit detects an output abnormality such as overvoltage or overcurrent, the information is sent to the CPU. The CPU judges that the output is abnormal, lowers the oscillation frequency of the OSC to a specified value, and keeps the PWM output off width at a constant value.
Raise to a value according to the oscillation frequency of SC. Assuming that the output value n of the UD / C is constant by this operation, s becomes shorter and the gradient of the triangular wave becomes larger, and as m increases, Toff is kept constant. It narrows and the output is reduced.

When the output is reduced, the output goes out of the abnormal state, and the CPU operates as follows in an attempt to return to the normal state.

The OSC oscillation frequency once lowered to the specified value is not restored to the same frequency as the normal state at the time of returning to the normal state, but is linearly provided with a certain time until the OSC returns to the normal state. Increase. At this time, the reference value m for determining the off width is decreased in synchronization with the increase of the oscillation frequency of the OSC so that the off width is constant.

By this operation, the pulse width gradually increases, so that the output can be restored softly.
In addition, since the degree of frequency increase and the return time to the normal state can be set by software, it is possible to make finely-tuned soft recovery settings.

(Second Embodiment) FIG. 3 shows a circuit block diagram of the second embodiment.

When an abnormality is detected and the output is temporarily lowered by the protection operation, and even if the output is restored by soft recovery as in the first embodiment, there is no problem in recovering as long as it is a temporary abnormality. When a permanent failure occurs due to the above reason, in the form of the first embodiment, the abnormality is detected and the output is reduced, and then the output is attempted to be restored. However, when the output starts, the abnormality is detected again and the output is reduced. Then, the intermittent operation such as is repeated.

Therefore, in this embodiment, one counter is provided to detect an abnormality and count the number of times the output is reduced.

As for the operation of the circuit, when an output abnormality is detected and detected, the oscillation frequency of the OSC decreases, the Toff determination reference value increases, the duty decreases, and the output decreases. After falling to the specified value, it tries to return to the normal state because it is out of the abnormal state. At this time, the soft recovery is performed by gradually changing the oscillation frequency of the OSC and the reference value for determining the off width. Here, if the abnormal state of the device continues, even if the output is restored, the abnormality is detected again and the OSC is detected.
The oscillation frequency of is reduced and protection operation starts. The added counter counts when an abnormal state is detected and the CPU is informed of the abnormal state, and when this continues for a prescribed number of times, the oscillation of the OSC is stopped.

The counting by this counter may be performed when the output voltage is detected and the voltage drops to a specified value.
It may be performed when a command to lower the frequency is issued from U to OSC.

When the output of the OSC is stopped after the specified number of times is counted, it is possible to display an error signal or a message on the operation section of the apparatus to inform the operator of the abnormality.

[0019]

The protection operation can be performed by changing the oscillator output during the operation of the protection circuit, and the fine soft recovery can be set during the automatic recovery.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a waveform showing the protection operation of the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment.

FIG. 4 is a circuit diagram of a conventional example.

FIG. 5 is a waveform showing the operation of the conventional example.

[Explanation of symbols]

C1 Output side smoothing capacitor in main PWM circuit Output side rectifier diode in D1 main PWM circuit D / A Digital / Analog converter D / C down counter OSC oscillator Q1 Switching transistor in main PWM circuit High voltage transformer in T1 main PWM circuit UD / C up / down counter Vref1 Output voltage control reference voltage

Claims (3)

[Claims] 1. A power supply for outputting a high voltage by pulse width control (PWM) switching, comprising: a first high voltage transformer; a first transistor for driving the first high voltage transformer; and a first high voltage transformer. The high voltage output voltage is provided with a first rectifying / smoothing circuit for rectifying and smoothing the secondary side output, a first high voltage output voltage detecting means, and a first output abnormality detecting means for detecting an abnormal state of the output. The output voltage detected by the detection means and the control reference voltage are compared by the first comparison means, and the PW is based on the comparison result.
A main PWM circuit that performs M control, a second high voltage transformer, and a second transistor that drives the second high voltage transformer,
A second rectifying and smoothing circuit for rectifying and smoothing the secondary side output of the second high voltage transformer, and a second high voltage output voltage detecting means,
A second output abnormality detecting means for detecting an abnormal state of the output, wherein the output voltage detected by the second high voltage output voltage detecting means and the voltage generated by the reference voltage generating D / A converter And a sub-PWM circuit for controlling the output at a constant voltage, and when the first or second output abnormality detecting means detects an output abnormality, a pulse to be supplied to the first high-voltage transformer driving transistor is supplied. It is characterized by narrowing the frequency of the oscillator to suppress the output. 2. The high-voltage power supply according to claim 1, wherein when an output abnormality is detected, the frequency of the oscillator is lowered to suppress the output once, the frequency of the oscillator is gradually raised to return to a soft state. . 3. The high-voltage power supply according to claim 1, when an output abnormality is detected, the frequency of the oscillator is lowered and the output is once held down, the frequency of the oscillator is gradually raised to return to a soft state. If the above continues, the same operation is performed again, and when this is repeated a specified number of times, the power supply is stopped by stopping the oscillator output.