JP2003111092A - Data conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive data conversion circuit with low power consumption without causing any color shift and positional deviation. SOLUTION: A sampling key signal calculation section 20 of the data conversion circuit 5 samples YUV data where a plurality of components are provided to one pixel into image data where a single component is provided to one pixel, calculates a key signal with a value corresponding to a correlation state between a target pixel and peripheral pixels of the YUV data and outputs composite data resulting from composing the sampled signal with the key signal. While one of first and second buffer memories 22, 23 stores the composite data in the unit of frames under the control of a write control section 21 and a read control section 24, the other outputs stored composite data. An interpolation section 25 individually executes piezoelectric interpolation processing according to the value of the key signal included in the composite data to output interpolation data to an EVF 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera such as a digital still camera or a digital video camera.
The present invention relates to a data conversion circuit that converts a component array of captured image data in a camera.

[0002]

2. Description of the Related Art FIG. 20 is a block diagram showing a schematic configuration of a conventional digital camera. In this digital camera, the light transmitted through the optical system 100 is detected by the CCD image pickup device 101 and converted into an analog signal. The image processing unit 103 performs gain adjustment, A / D conversion, etc. on the analog signal input from the CCD image pickup device 101 to generate a digital signal (raw image data) and outputs the digital signal to the image processing unit 103. . The original image data is subjected to digital image processing such as pixel interpolation, contour enhancement and color space conversion in the image processing unit 103, and then transferred and stored in the buffer area of the main memory 106. The CPU 107 reads out the image data stored in the buffer area and performs software processing on the image data, or the compression / expansion processing unit 110 compresses and encodes the read image data and records the image data in an IC memory via the card interface 108. Can be controlled to

Further, this digital camera is equipped with two types of display devices for electronically displaying captured image data. One is an LCD (Liquid Crystal Display) device 111 having a relatively large screen provided on the back surface of the digital camera, and the other is an electronic viewfinder (hereinafter referred to as EVF) provided at the eyepiece part of the digital camera. 114). A frame-sequential display that displays one frame in a frame-sequential format is used for the EVF 114. The user can select either one of the display devices by operating a switching button (not shown) provided on the digital camera. When displaying the moving image of the image data on these display devices, the CPU 107 causes the image processing unit 103 to sequentially output the low resolution image data and transfers the low resolution image data to the display signal processing unit 109 via the bus 115. LCD device 1
When a moving image is displayed at 11, the display signal processing unit 1
09 converts the image data into a video signal such as an analog RGB signal and outputs it to the LCD device 111. LCD
The device 111 displays a moving image by driving a liquid crystal panel or a backlight based on an input video signal.
It is also possible to transfer the video signal output from the display signal processing unit 109 to an external TV monitor via the cable 112 to display a moving image.

On the other hand, when displaying a moving image on the EVF 114, the display signal processing unit 109 transfers image data input via the bus 115 to the data conversion circuit 113. From the image processing unit 103, three primary color components of R (red), G (green), and B (blue) per pixel, or Y (luminance component), Cb (color difference component) per pixel,
Three components such as Cr (color difference component) are output in a dot-sequential format, and the data conversion circuit 113 uses the dot-sequential format data (hereinafter, dot-sequential format) in which the respective components of the transferred image data are arranged in pixel units. The data is referred to as data) and is converted into frame-sequential data arranged in frame units (hereinafter referred to as frame-sequential data) and output to the EVF 114. Figure 21
FIG. 4 is an explanatory diagram schematically showing image data in a dot sequential format of R, G and B. As shown in the figure, one frame is R
[0, 0], G [0, 0], B [0, 0], R [1, 0], G [1,0], B [1,
0], ..., R [i, j], G [i, j], B [i, j] ..., R [w-1, h-1],
G [w-1, h-1] and B [w-1, h-1] (i: horizontal pixel number, j: horizontal line number) are transferred in this order. In addition, FIG.
It is explanatory drawing which shows the image data of the frame sequential format of R, G, B typically. As shown in the figure, one frame has R [0,
0],…, R [w-1, h-1], G [0, 0],…, G [w-1, h-1], B
[0, 0], ..., B [w-1, h-1] will be transferred in this order. That is, R field only for R [0, 0], ..., R [w-1, h-1], G field only for G [0, 0], ..., G [w-1, h-1], Then, the B fields of only B [0, 0], ..., B [w-1, h-1] are transferred in this order.

The conventional data conversion circuit 113 is provided with a buffer memory for at least one frame, stores the input dot-sequential data for one frame in the buffer memory, reads it in a frame-sequential format, and has a high frame rate. Then, it was output to the EVF 114. For example, when the dot-sequential data is composed of 3 components of 8 bits for each color, a buffer memory having a capacity of total number of pixels × 3 bytes is required. However, when the buffer memory has a capacity of only one frame, frame sequential data may be read from the buffer memory in the process of writing the dot sequential data in the buffer memory. Since the EVF 114 takes in each color field in time series, there is a problem that a so-called “color shift” phenomenon occurs in which the subject is displayed at a different position for each color field when the subject is moving.

When displaying dot-sequential data on a display device such as the EVF 114, a so-called frame rate conversion is used when converting the interface display into a progressive display or outputting a frame according to the display speed of the display device. Is being done. However, when the frame rate conversion is performed in the buffer memory for one frame, as shown in FIG. 23, the fast moving subject 117 in the display image 116 appears to be misaligned between the upper portion 116a and the lower portion 116b of the display image 116. That is, so-called "positional deviation"
There is a problem that the phenomenon occurs.

In order to prevent the above-mentioned phenomenon caused by the dot-sequential-field-sequential conversion or the frame rate conversion, it is sufficient to prepare a buffer memory for two frames. FIG. 24 is a schematic diagram showing a data conversion circuit 113 having buffer memories 122A and 122B for two frames. In this data conversion circuit 113, the color space conversion circuit 120 converts the color space of the input dot-sequential data into the RGB space and outputs it.
The dot-sequential data output from the color space conversion circuit 120 is controlled by the write controller 121 to be written in either one of the first buffer memory 122A and the second buffer memory 122B. In addition, the read control unit 123, during a period in which dot-sequential data is written in either one of the buffer memories 122A or 122B,
From the other buffer memory 122B or 122A,
The frame sequential data is controlled to be read out at a high frame rate and output to the EVF 114.

[0008]

However, as shown in FIG.
In the data conversion circuit 113 shown in (1), a buffer memory for two frames must be prepared. This allows
Since the power consumption of the circuit increases, it is difficult to continuously use the digital camera for a long time, and the circuit scale also increases, which causes an increase in cost.

In view of the above problems, the present invention intends to solve the problem that the capacity of the buffer memory is not increased, the above-mentioned color shift phenomenon and position shift phenomenon are not caused, and the power consumption is low and the cost is low. The point is to provide a data conversion circuit.

[0010]

In order to solve the above problems, the invention according to claim 1 samples and outputs input image data having a plurality of components per pixel to image data having a single component per pixel. A sampling unit,
A key signal calculation unit that calculates a key signal having a value corresponding to a correlation state between a pixel of interest of the input image data and peripheral pixels, and image data output from the sampling unit and the key signal in frame units or fields. Write control means for controlling to store in the buffer memory in units, and read control means for controlling to read out the image data and the key signal stored in the buffer memory in frame units or field units. Pixel interpolation processing for interpolating a plurality of components per pixel for the image data read by the read control unit is individually executed according to the value of the key signal, and the interpolation data subjected to the pixel interpolation processing Is output to the display device.

According to a second aspect of the present invention, in the data conversion circuit according to the first aspect, the write control means outputs the combined data obtained by combining the image data and the key signal output from the sampling section. The image data is stored in the buffer memory, and the interpolation unit executes the pixel interpolation processing on the image data obtained by separating the combined data read from the buffer memory by the read control unit. Is.

According to a third aspect of the present invention, in the data conversion circuit according to the first aspect, the writing control means includes data in which the key signal is included in the lower bits of the image data output from the sampling section. Is stored in the buffer memory, and the interpolation section executes the pixel interpolation processing by extracting the image data and the key signal from the data read from the buffer memory by the read control means. Is.

The invention according to claim 4 is the data conversion circuit according to any one of claims 1 to 3, wherein the buffer memory is a first buffer memory and a second buffer memory.
The write control means controls the image data and the key signal to be alternately stored in the first buffer memory and the second buffer memory in frame units or field units, The read control means includes the first buffer memory and the second buffer memory.
During the period in which the data is written in one of the buffer memories, the data stored in the other memory is controlled to be read out in frame units or field units, and the interpolating unit controls the respective components in pixel units. The frame-sequential interpolation data in which the respective components are arranged in a frame unit or a field unit are generated from the image data in the dot-sequential form arranged in 1.

According to a fifth aspect of the present invention, in the data conversion circuit according to the fourth aspect, the interpolation section generates the frame-sequential interpolation data at a frame rate different from the frame rate of the input image data. It is a thing.

The invention according to claim 6 is the data conversion circuit according to any one of claims 1 to 3, wherein the buffer memory is a first buffer memory and a second buffer memory.
The write control means stores the image data output from the sampling section and the key signal alternately in the first buffer memory and the second buffer memory in frame units or field units. The read control means controls the data stored in the other memory in frame units while the data is written in one of the first buffer memory and the second buffer memory. Alternatively, the interpolation unit controls to read out in field units, and the interpolation unit outputs the interpolation data by executing the pixel interpolation process at a frame rate different from the frame rate of the input image data.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Configuration of digital camera. First, a configuration example of a digital camera incorporating the data conversion circuit according to the embodiment of the present invention will be shown, and then the data conversion circuit according to each embodiment will be described in detail. FIG. 1 is a functional block diagram showing the overall configuration of a digital camera 1 incorporating the data conversion circuit 5. The digital camera 1 includes an optical mechanism 2 having an AF (auto focus) control function and an automatic exposure control function, a CCD image pickup device 3 for receiving light transmitted through the optical mechanism 2, and a CCD image pickup operation. The analog image signal output from the element 3 is processed to obtain digital image data (original image data; Raw Image
Data), and an image processing unit 8 that performs digital image processing on the original image data.
Is equipped with. The timing generator 7 is C
CD drive unit 3A, analog signal processing unit 4, image processing unit 8
And a clock signal that regulates the operation timing of the data conversion circuit 5 is generated and supplied.

The CCD image pickup device 3 operates by receiving a drive signal from the CCD drive circuit 3A, and a charge storage section for storing carriers (electrons or holes) generated by the photoelectric effect, and an electric field for the stored carriers. And a charge transfer unit for applying and transferring. A single plate type color filter array for coloring incident light on a pixel-by-pixel basis is provided on the photosensitive portion of the CCD image pickup device 3. Therefore, in the photosensitive portion of the CCD image pickup device 12, R (red), G
Light colored by the three primary colors (green) and B (blue) or four colors such as Y (yellow), M (magenta), C (cyan), and G (green) is incident and photoelectric conversion is performed. Will be received. Instead of the CCD image pickup device 3, a CMOS image pickup device having no charge transfer section may be adopted.

The analog signal processing section 4 includes a CDS (Correl
ated Double Sampling circuit,
It is provided with an AGC (Automatic Gain Control) circuit and an A / D conversion circuit. CCD image sensor 3
Normally outputs a reference signal having a reference level of a black level and an image signal including the reference signal alternately in a time division manner.
The CDS circuit samples the reference signal and the image signal in order to remove the noise component contained in the image signal, and extracts and outputs the difference signal between the two signals. Also, A
The GC circuit outputs a signal in which the signal level of the differential signal input from the CDS circuit is optimized, and the A / D conversion circuit samples the input signal from the AGC circuit and quantizes it with a predetermined number of quantization bits. Raw image data (Raw Imag
e Data) is output.

The image processing section 8 is an integrated circuit which operates in synchronization with the clock signal supplied from the timing generator 7. The image processing unit 8 performs various shading correction processing, pixel interpolation processing, gamma correction processing, color space conversion processing, contour enhancement processing, resolution conversion processing, and the like on the original image data input from the analog signal processing unit 4. It has the function of executing digital image processing in real time. For example, in the pixel interpolation processing, the single plate color filter array interpolates a plurality of components per pixel for an image signal having only a single component per pixel. As a result, an image signal having three primary color components of R, G, B or four color components of complementary colors such as Y, M, C, G is generated per pixel.

The image signal output by the image processing unit 8 is transferred to the CPU (central processing unit) 11 or the main memory 9 via the bus 10 and subjected to various processes. CPU11
Can use the main memory 9 as a work area and execute various software processes on the image signal. Also, CP
The U11 activates the compression / decompression processing unit 16 to convert the image signal into a JPEG (Joint Photographic Expert Group).
p) method or motion JPEG method and the like, and then the compressed data is transferred to the interface section 15 and stored in a storage medium such as a memory card or output to an external device such as a personal computer. It is possible.

The CPU 11 can be further controlled to display still images (frames) continuously output from the image processing unit 8 on the LCD device 13 and the EVF 6 as moving images.
The LCD device 13 is a display device with a relatively large screen provided on the back surface of the digital camera 1, and the EVF 6 is a frame sequential display provided on the eyepiece part of the digital camera 1. When displaying consecutive frames picked up by the CCD image pickup device 3 on the LCD device 13, the CPU 11 causes the image processing unit 8 to output each frame which has undergone resolution conversion according to the resolution of the LCD device 13 and outputs the frames. The display signal processing unit 12 is controlled to be sequentially transferred via the display signal processing unit 12. The display signal processing unit 12 converts the transferred frame into a television signal and outputs it to the LCD device 13. The television signal can also be output to an external television monitor via the cable 14.

Further, when the continuous frames picked up by the CCD image pickup device 3 are displayed on the EVF 6, the display signal processing section 12 causes the digital RG transferred from the image processing section 8 to be displayed.
The B signal is transmitted according to ITU-R (International Telecommunication Union Radio Communications Division) Recommendation BT. A YUV444 format signal conforming to 601 is converted to a luminance signal (Y data) and a color difference signal (U data,
VUV data) and 24-bit width YUV data is output. The YUV data is converted from dot-sequential data to field-sequential data by the data conversion circuit 5 according to the present invention, and then output to the EVF 6 for moving image display.

The data conversion circuit 5 comprises a data writing / reading unit 26 and an interpolation unit 25. Data writing
In the reading unit 26, the sampling key signal calculating unit 20
Is used to sample the input YUV data, convert it into image data having a single component (Y component, U component or V component) per pixel, and output it. At the same time, as will be described later, focus on the input YUV data. It has a function of calculating a key signal having a value corresponding to a correlation state between a pixel and a peripheral pixel. The YUV data input to the sampling key signal calculation unit 20 has three components (Y component, U component) per pixel.
Component and V component), but is sampled into a single component per pixel in a predetermined array. Therefore, compared with the case of storing image data having N components (N ≧ 3) per pixel, the first buffer memory 22
And the required memory capacity for the second buffer memory 23 is 1
Since / N is sufficient and the number can be significantly reduced, it is possible to reduce the circuit scale and reduce the cost.

Further, the write control unit 21 stores the input data from the sampling key signal calculation unit 20 in the first buffer memory 22 and the second buffer memory 23 alternately in frame units or field units. To control. Here, the field means an even field composed of only even-numbered horizontal lines or an odd field composed of only odd-numbered horizontal lines. Further, the read control unit 24 reads the data stored in the other memory in frame units or field units during a period in which the data is written in one of the first buffer memory 22 and the second buffer memory 23. The output is output to the interpolating unit 25.

The interpolating unit 25 performs a pixel interpolating process for interpolating a plurality of components per pixel on the data read by the reading control unit 24 based on the key signal, as described later in detail. The data is output to EVF6.

An embodiment of the data conversion circuit 5 mounted on the digital camera 1 having the above configuration will be described in detail below.

Embodiment 1. 2 and 3 show a data conversion circuit 5 _{1 according} to the first embodiment of the present invention. Figure 2
3 and FIG. 3 are continuous with each other through the one-dot chain line according to the positional relationship shown in FIG. The data conversion circuit 5 _{1 according to the first} embodiment includes a data writing / reading unit 26 ₁ shown in FIG.
It is composed of an interpolation unit 25 ₁ shown in FIG.

The sampling / key signal calculating unit 20 of the data writing / reading unit 26 ₁ shown in FIG. 2 has the 24-bit width YUV data output from the display signal processing unit 12 as a single component per pixel. A sampling circuit 20A for converting into data and a key signal calculation circuit 20B for calculating a 2-bit width key signal described later on a pixel-by-pixel basis based on the YUV data are provided. FIG. 5 is an explanatory diagram showing the component array 40 of the data output by the sampling circuit 20A. The letters “Y”, “U”, and “V” are attached to the pixels having the Y component, the U component, and the V component, respectively.

The sampling circuit 20A samples each component according to the component array 40 shown in FIG. That is, the Y component (luminance component) is sampled on each horizontal line in a staggered array every other horizontal pixel, and the U component and the V component (color difference component) are sampled every other horizontal line and every other horizontal pixel. And output as 8-bit width pixel data. Then, the sampling circuit 20
The 8-bit width pixel data output by A and the 2-bit width key signal output by the key signal calculation circuit 20B are combined to form combined data of 10-bit width in the first buffer.
Memory (SRAM) 22 and second buffer memory (SR
AM) 23.

The data writing / reading unit 26 ₁ is provided with a first buffer memory 22 and a second buffer memory 23 forming two banks, and further for inputting to generate an address signal for writing data. Address generator 2
7, an input timing generator 28 for instructing the input address generator 27 of a timing for writing data, an output address generator 30 for generating an address signal for reading data, and
The output timing generator 29 for instructing the output address generator 30 at the timing of data reading is provided.

Both the first buffer memory 22 and the second buffer memory 23 are at least 320 × 240.
It has a storage capacity of pixels (= number of horizontal pixels × number of vertical pixels) × 10 bits. 320 x 240 of this storage capacity
The number of pixels corresponds to the number of display pixels of the EVF 6. These first buffer memory 22 and second buffer memory 22
Each of the memories 23 has a write enable terminal WE and a read enable terminal RE, and each enable terminal WE, RE has one of the AND gates 31, 32, 3
Control signals are supplied from 3, 34.

The 10-bit width combined data output from the sampling key signal calculating section 20 is input to the respective data input terminals Din of the first buffer memory 22 and the second buffer memory 23, and the respective buffer memories 22. , 23,
It is stored alternately in frame units or field units. While data is being written to the first buffer memory 22, while the data is being read from the second buffer memory 23, the signal level of the bank selection signal BSCT is "H (Hig
h) "and is maintained. During this period, the AND gate 31 which supplies a control signal to the write enable terminal WE of the first buffer memory 22 and the read enable terminal RE of the second buffer memory 23 are controlled. The H level signal is transmitted to the AND gate 34 which supplies the signal.
The H-level bank selection signal BSCT is inverted by the inverter 35 into an L (Low) level signal. This L level signal supplies an AND gate 32 which supplies a control signal to the read enable terminal RE of the first buffer memory 22 and an AND gate 33 which supplies a control signal to the write enable terminal WE of the second buffer memory 23. Is being supplied to. On the other hand, while the data is being written to the second buffer memory 23, the signal level of the bank selection signal BSCT is switched to "L" and maintained while the data is being read from the first buffer memory 22.

Both the input timing generator 28 and the input address generator 27 operate in synchronization with the supplied input pixel clock ICLK. The input timing generator 28 uses the input pixel clock ICLK and the horizontal synchronization signal HD based on the resolution conversion coefficients α and β (α and β: 1 or more) stored in the register 28A.
And the write enable pulse WEBL is generated using the vertical synchronizing signal VD and is output to the input address generator 27. Here, the horizontal synchronizing signal HD and the vertical synchronizing signal VD are supplied from the timing generator 7 shown in FIG. Further, α is a coefficient for resolution conversion of the image size of the YUV data in the horizontal direction by 1 / α times, and β is a coefficient for resolution conversion of the image size in the vertical direction by 1 / β times. . The values of the coefficients α and β are YU
The resolution of the V data is adjusted to match the resolution of the EVF.

The input address generator 27 is also provided.
Has an address counter (not shown) that increments the write address, and the address counter is
Each time the write enable pulse WEBL is input, the write address is incremented to generate an address signal. Further, the input address generator 27 supplies the generated address signal to the address input terminals Addr_i of the first buffer memory 22 and the second buffer memory 23 at the same time as the write operation of H level at the time of data writing. AND gate 31 and 3 enable signals
Supply to 3. The AND gate 31 outputs a signal obtained by ANDing the write enable signal and the bank selection signal BSCT to the terminal WE of the first buffer memory 22. Further, the AND gate 33 outputs a signal obtained by ANDing the write enable signal and the inverted signal supplied from the inverter 35 to the terminal WE of the second buffer memory 23.

The write controller 21 shown in FIG. 1 comprises the above-mentioned input address generator 27, input timing generator 28, and AND gates 31 and 33.

Next, the output timing generator 2
9 and the output address generator 30 both operate in synchronization with the supplied output pixel clock OCLK. The output timing generator 29 uses the output pixel clock OCLK to generate a read enable pulse REBL indicating the timing of data reading, and supplies it to the output address generator 30.

Also, the output address generator 30
Incorporates an address counter (not shown) that increments the read address.
Each time the read enable pulse REBL is input, the read address is incremented to generate an address signal. Further, the output address generator 30 supplies the generated address signal to the address input terminals Addr_o of the first buffer memory 22 and the second buffer memory 23 at the same time when the data is read, and at the same time, reads the H level. The enable signal is sent to each AND gate 32,
Supply to 34. One AND gate 34 generates a signal obtained by ANDing the read enable signal and the bank selection signal BSCT and outputs the signal to the terminal RE of the second buffer memory 23, and the other AND gate 32 outputs the read signal. A signal obtained by ANDing the enable signal and the inverted signal supplied from the inverter 35 is output to the terminal RE of the first buffer memory 22.

The frequency of the output pixel clock OCLK is set higher than that of the input pixel clock ICLK in order to increase the frame rate at the time of reading data.

As described above, the 10-bit width combined data read from the data output terminal Dout of the first buffer memory 22 is input to the "0" side terminal of the selector 24A, while the combined data of the second buffer memory 23 is input. Data output terminal D
The 10-bit width combined data read from out is input to the "1" side terminal of the selector 24A. Selector 24
A selects the "0" side terminal or the "1" side terminal according to the signal level of the bank selection signal BSCT being "L" or "H", and the combined data input from the selected terminal is interpolated as shown in FIG. It is output to the unit 25 ₁ .

The read control section 24 shown in FIG. 1 is composed of the output timing generator 29, the output address generator 30, the AND gates 32 and 34, and the selector 24A.

Next, the interpolation unit 25 ₁ shown in FIG. 3 will be described. The 10-bit width combined data input to the interpolator 25 ₁ is separated into 8-bit width pixel data and 2-bit width key signal. The interpolator 25 ₁ has a register group 36 for holding 8-bit pixel data in a 3 × 3 pixel area.
And FI for temporarily storing pixel data of one horizontal line
It is composed of an FO memory 38 and an interpolation / component selection circuit 39.

The register group 36 includes nine registers 37.
A, 37B, 37C, 37D, 37E, 37F, 37
G, 37H, and 37I are connected in multiple stages in series via a FIFO memory 38. Registers 37A to 37I
Each time the output pixel clock OCLK is input, the pixel data input to the data input terminal (D) is taken in, and at the same time, the held pixel data is input from the data output terminal (Q) to the register or FIFO memory 38 of the next stage. Shift to. Such a register group 36 can hold pixel data of an arbitrary 3 × 3 pixel area in one frame or one field. Note that in the example shown in FIG. 3, the register group 36 has nine registers 37A to 37I, but instead of this, by having 25 registers, even if pixel data of a 5 × 5 pixel area is held. Good.

The 8-bit width pixel data output from the data output terminals (Q) of the registers 37A to 37I and the 2-bit width key signal are input to the interpolation / component selection circuit 39. The interpolation / component selection circuit 39 operates in synchronism with the timing signal TI supplied from the output timing generator 29, and uses the pixel data of the input 3 × 3 pixel area to generate a pixel corresponding to the value of the key signal. After the interpolation processing is executed, the color space conversion is executed and the three RGB components are output. In the first embodiment, in order to create the R field of only the R component, the G field of only the G component, and the B field of only the B component by the pixel interpolation processing, the first buffer memory 22 or the second buffer memory 2
The same pixel data from 3 is read three times for each field. In this way, the interpolation / component selection circuit 39 operates as shown in FIG.
The frame sequential data as shown in 2 is output to the EVF 6.

Key value calculation processing and pixel interpolation processing. Next, the key value calculation processing in the key signal calculation circuit 20B and the pixel interpolation processing in the interpolation / component selection circuit 39 will be described in detail. The sampling circuit 20A samples data having a single component per pixel from image data having three components per pixel. afterwards,
Image data having three components per pixel is restored by the pixel interpolation processing of the interpolation / component selection circuit 39, but it is difficult to completely reconstruct the image information lost by sampling, and deterioration of image quality is inevitable. . In particular, there has been a problem that the boundary line in the horizontal pixel direction or the vertical pixel direction is restored in a jagged shape, or the striped pattern composed of vertical lines is erroneously restored to a striped pattern composed of horizontal lines. In the first embodiment, the key signal calculation circuit 20B calculates a key signal having a value corresponding to the correlation state between the pixel of interest and the peripheral pixels of the image data before sampling, and the interpolation unit 25 corresponds to the value of the key signal. By individually performing the pixel interpolation processing described above, it is possible to significantly improve the above-mentioned problems.

Example of Key Value Calculation Process and Pixel Interpolation Process In this example, the key signal calculation circuit 20B includes a register (not shown) that temporarily stores the image data of the 3 × 3 pixel area. FIG. 6 is an explanatory diagram schematically showing the image data 41 in the 3 × 3 pixel area. In FIG. 6, “X”, “A”, “B”, “C”, “D”,
The letter "Z" is attached. In this example, the pixel with "Z" indicates the target pixel of the thinning target that is not sampled, and the pixels of "A", "B", "C", "D",
The pixel data of the pixels with "Z" are D _A ,
Let D _B , D _C , D _D , and D _Z.

The key signal calculation circuit 20B determines the difference value Δ concerning the luminance component between the target pixel to be thinned and the peripheral pixels.
₁ and Δ ₂ are calculated according to the following equations (1) and (2).

[0047]

[Equation 1]

In the above equations (1) and (2), ABS (x) is
This is a symbol for obtaining the absolute value of the numerical value x. The difference value Δ ₁ indicates the correlation state between the pixel of interest and the peripheral pixels in the horizontal direction,
The difference value Δ ₂ indicates the correlation state between the pixel of interest and the peripheral pixels in the vertical direction. In this example, the smaller the difference values Δ ₁ and Δ ₂ , the higher the correlation. Further, when the sampling circuit 20A samples a single component according to the component array 40 shown in FIG. 5, the U component or the V component is sampled in the pixel of interest, and the vertical
The Y component is sampled in the peripheral pixels adjacent in the horizontal direction. Therefore, the key signal calculation circuit 20B calculates the difference values Δ ₁ and Δ ₂ regarding the Y component when the U component or the V component is sampled in the pixel of interest.

[0049] Then, the key signal calculating circuit 20B is both the difference value delta _1, to determine the magnitude of delta _2, the value of delta ₁ is equal to or less than delta ₂ values (Δ ₁ ≦ Δ ₂₎ If, it outputs a key signal having a value of "0", on the other hand, when the value of delta ₁ is determined to be greater than the value of _{Δ 2 (Δ 1> Δ 2} ) has a value of "1" Output the key signal. Therefore, in this example, only the lower 1 bit of the 2-bit wide key signal is used.

On the other hand, the interpolation / component selection circuit 39 regards the pixel data output from the center register 37E of the register group 36 shown in FIG. 3 as the data of the pixel of interest, and outputs it from the registers 37B, 37D, 37F, 37H. The pixel interpolation processing is executed by regarding the pixel data to be processed as the data of the peripheral pixels. When the value of the key signal corresponding to the pixel of interest is “0”, the interpolation / component selection circuit 39 uses the average value of the data of the peripheral pixels adjacent in the vertical direction as the interpolation data, while the value of the key signal is “0”. In the case of "1", the average value of the data of the peripheral pixels adjacent in the horizontal direction is calculated as the interpolation data.

As described above, in this example, since the information on the correlation state between the target pixel of the image data before sampling and the peripheral pixels is included in the key signal and the pixel interpolation processing corresponding to the value of the key signal is individually performed, It is possible to generate and output frame sequential data in which image quality deterioration due to sampling is suppressed.

Example of key value calculation processing and pixel interpolation processing Similar to the case of the above example 1, the key signal calculation circuit 20B includes a register (not shown) that temporarily stores the image data 41 of the 3 × 3 pixel area shown in FIG. Key signal calculating circuit 20B is between the target pixel and the peripheral pixels thinned out, the difference value delta _U relating to the luminance component, delta _D, delta _R, following equation delta _L (3) is calculated according to (6). However, the following equation (3)
In (6), V _K represents the value of the key signal corresponding to each equation.

[0053]

[Equation 2]

In the above equations (3) to (6), the difference values Δ _U and Δ _D indicate the correlation state with the neighboring pixels vertically and vertically adjacent to the pixel of interest, and the difference value Δ _R ，
Δ _L represents the correlation state between the pixel of interest and the neighboring pixels that are adjacent on the left and right sides in the horizontal direction. In this example, the smaller the difference value, the higher the correlation state.

Next, the key signal calculation circuit 20B selects the one having the minimum value from the difference values Δ _U , Δ _D , Δ _R , and Δ _L. The value of the key signal, when selecting a difference value delta _U is "0", "1" if you select the difference value delta _D is the difference value delta _R
If you select is set to "2", if you select the difference value delta _L is "3".

On the other hand, the interpolation / component selection circuit 39 regards the pixel data output from the register 37E at the center of the register group 36 shown in FIG. 3 as the data of the pixel of interest, and registers 37B, 37D, 37F, 37H
The pixel data output from is regarded as the data of the peripheral pixels, and the pixel interpolation processing is executed. Interpolation / component selection circuit 39
When the value of the key signal is "0", the pixel data output from the register 37B vertically adjacent to the register 37E is used as interpolation data, and when the value of the key signal is "1", The register 37 adjacent vertically downward
When the pixel data output from H is used as interpolation data and the value of the key signal is “2”, the register 37 on the right in the horizontal direction
The pixel data output from F is used as interpolation data, and when the value of the key signal is "3", the register 37 on the left side in the horizontal direction
The pixel data output from D is output as interpolation data. As described above, also in this example, it is possible to generate and output frame sequential data in which image quality deterioration due to sampling is suppressed.

2. Example of key value calculation processing and pixel interpolation processing As in the case of Examples 1 and 2 above, the key signal calculation circuit 20B
Includes a register (not shown) for temporarily storing the image data 41 of the 3 × 3 pixel area shown in FIG. Further, in this example, since a 3-bit key signal is output as described later, an 8-bit width image signal output from the sampling circuit 20A and a 3-bit width key output from the key signal calculation circuit 20B. Combined data having a 11-bit width that is combined with the signal is output. Also, the first buffer
The memory 22 and the second buffer memory 23 are each 1
It has a storage capacity for storing 1-bit width combined data.

The key signal calculation circuit 20B executes a spatial filtering process on the luminance component of the input image data (YUV data). Therefore, the key signal calculation circuit 20B causes the vertical line in the vertical pixel direction, the horizontal line in the horizontal pixel direction, the oblique line, the boundary line in the vertical pixel direction (vertical edge), the boundary line in the horizontal pixel direction (horizontal edge), and A spatial filter of 3 × 3 pixels is provided to detect each diagonal boundary line (oblique edge). As shown in FIG. 7, the spatial filter (weighting mask) 42 has a coefficient value A (i, j) corresponding to each pixel data in the 3 × 3 pixel area on a one-to-one basis.
(I, j are integers from 0 to 2) and each coefficient value A (i, j
It has a function of performing a product-sum operation of weighting (multiplying) j and adding it to corresponding pixel data.
8 to 15 are diagrams illustrating various types of spatial filters. FIG. 8 shows a spatial filter 4 having coefficient values for vertical line detection.
2A, FIG. 9 shows a spatial filter 42B having a coefficient value for horizontal line detection, FIG. 10 shows a spatial filter 42C having a coefficient value for oblique line detection on the lower right, and FIG.
Spatial filter 42 having coefficient values for detecting oblique lines rising to the right
12 shows D, FIG. 12 shows a spatial filter 42E having coefficient values for vertical edge detection, FIG. 13 shows a spatial filter 42F having coefficient values for horizontal edge detection, and FIG. FIG. 15 shows a spatial filter 42G having a coefficient value for edge detection, and FIG. 15 shows a spatial filter 42H having a coefficient value for detecting a diagonal edge rising to the right.

Also, these spatial filters 42A to 42H.
It is determined whether or not the sum-of-products calculation value output from exceeds a predetermined threshold value. When the sum of products operation value exceeds the threshold value, a key signal having a predetermined value is output. The value of the key signal in this example is “0” when the vertical line is detected by the spatial filter 42A (FIG. 8), “1” when the horizontal line is detected by the spatial filter 42B (FIG. 9), and the spatial filter 42C. In Fig. 10, the case where a downward sloping diagonal line is detected is "2", and the spatial filter 4 is
When a diagonal line rising to the right is detected in 2D (Fig. 11), "3" is detected, when a vertical edge is detected by the spatial filter 42E (Fig. 12), "4" is detected, and a horizontal edge is detected by the spatial filter 42F (Fig. 13). If you did, the spatial filter 42G
"6" is set when a downward-sloping diagonal edge is detected in (Fig. 14), and "7" is set when a spatially-sloping diagonal edge is detected by the spatial filter 42H (Fig. 15).

On the other hand, the interpolator 25 needs to have a register group for holding pixel data of 5 × 5 pixels, instead of having a register group 36 for holding pixel data of 3 × 3 pixels shown in FIG. FIG. 15 is a diagram schematically showing the image data 43 of the 5 × 5 pixel area held in the register group included in the interpolation unit 25. In FIG. 15, “X”, “A”, “B”, “C”, “D”, “E”, corresponding to each pixel.
"F", "G", "H", "I", "J", "K",
The letter "L" is attached. Pixels with "Z"
It is a pixel of interest for pixel interpolation. Also, "A" to "L"
The pixel data of each pixel marked with is respectively ID _{A to} I
_Let be represented by D _L.

The 11-bit wide combined data input to the interpolator 25 is separated into 8-bit wide pixel data and 3-bit wide key signal. The interpolation / component selection circuit 39, according to the value “0” to “7” of the input 3-bit key signal,
Interpolation data D according to the following equations (7) to (14), respectively.
Output _Z. However, in the following equations (7) to (14), V _K is
The value of the key signal corresponding to each expression is shown.

[0062]

[Equation 3]

However, the function Medi of the above equations (11) and (12)
_{an (X 1, X 2,} X 3, X 4) , when sorted arguments X ₁ to X ₄ in ascending order, to calculate numeric median come to the center. That is, the number of small numbers than the center value among the numerical X ₁ to X _4, and a number of numeric value greater than the median equal. For example, Median (1, 2, 3, 4) = 2.5.

As described above, in this example, the features such as vertical lines and diagonal lines appearing in the image data before sampling are detected as the correlation state, and the value of the key signal is set according to each feature. It is possible to accurately restore the characteristics of the image data before sampling, and it is possible to generate and output frame sequential data with little deterioration in image quality.

3. Example of key value calculation processing and pixel interpolation processing In this example, as in Example 3 above, the key signal calculation circuit 20B
A register (not shown) for temporarily storing the image data 41 in the 3 × 3 pixel area shown in FIG. 6 is provided, and a key signal having a 3-bit width is output. Therefore, 11-bit wide combined data obtained by combining the 8-bit wide image signal output from the sampling circuit 20A and the 3-bit wide key signal output from the key signal calculation circuit 20B is output.
Further, each of the first buffer memory 22 and the second buffer memory 23 has a storage capacity for storing combined data having an 11-bit width.

The key signal calculation circuit 20B calculates average data <V>, <H>, <O ₁ >, <O ₂ >, <O ₃ >, <O ₄ regarding the luminance components of the peripheral pixels for the target pixel to be thinned out.
> And <O ₅ > are calculated according to the following equations (15) to (21). In addition, in the following equation, the value V _{K of the} key signal corresponding to each equation
Also shows.

[0067]

[Equation 4]

The key signal calculation circuit 20B selects the average data having the value closest to the pixel data D _Z of the pixel of interest from the average data, and the key signal having the value V _K corresponding to the selected average data. Is output.

On the other hand, the interpolating section 25, as in the above-mentioned example 3,
A register group for holding the image data 43 of the 5 × 5 pixel area shown in FIG. 15 is provided. The interpolating / component selecting circuit 39 of the interpolating unit 25 respectively calculates the following formulas (22) to (6) in accordance with the values “0” to “6” of the input 3-bit key signal.
The interpolation data ID _Z is calculated according to (28).

[0070]

[Equation 5]

4. Example of key value calculation processing and pixel interpolation processing In this example, similar to Examples 4 and 5, the key signal calculation circuit 20B is used.
Is provided with a register (not shown) for temporarily storing the image data 41 of the 3 × 3 pixel area shown in FIG. 6, and outputs a key signal having a 3-bit width. Therefore, the first buffer memory 22 and the second buffer memory 23 are respectively
It has a storage capacity for storing combined data having an 11-bit width.

The key signal calculation circuit 20B first determines the image of interest.
Difference value D between the pixel and the average value of surrounding pixels _YIs expressed by the following equation (29)
According to the calculation, and store it in a 9-bit register (not shown).
Pay.

[0073]

[Equation 6]

Next, the reproduction range of the difference value D _Y is limited to -16 or more and 15 or less. That is, the difference value D _Y is 15
When it exceeds (D _Y > 15), the value V _{K of the} key signal is changed to V _K =
When set to +3 and the difference value D _Y is less than −16 (D _Y <−
16) sets the value V _{K of the} key signal to V _K = -4. When the difference value D _Y is 16 or more and 15 or less (−16 ≦
D _Y ≦ 15) shifts the 9-bit key signal to the right by 2 bits, and then converts the 5-bit key signal after the right shift to 3-bit data in 2's complement representation. Table 1 below
The difference value D _Y in decimal notation, the value V _K of the key signal in decimal notation, and the two's complement representation of the value V _K of this key signal are shown in FIG.

[0075]

[Table 1]

In this way, the key signal calculation circuit 20B
The difference value D in pixel units for the degree component _YAfter calculating
As shown in 1, the difference value D_Y3 corresponding to each numerical range of
Bit value V_KCalculate and output the key signal with.

On the other hand, the interpolation section 25 is provided with a register group for holding the image data 43 of the 5 × 5 pixel area shown in FIG. 15 as in the case of Example 4 above. Since a 3-bit width key signal is input to the interpolation / component selection circuit 39 of the interpolation unit 25, the interpolation / component selection circuit 39 shifts the key signal left by 2 bits to expand it to a 5-bit value, and then Extend to an 8-bit value V _K 'in 2's complement form. For example, the value V _{K of the} key signal is “011” in binary (“+3” in decimal)
In the case of, the 5-bit value obtained by shifting the key signal to the left by 2 bits is “01100” in binary, and the 8-bit value V _K 'which is the bit extension of this 5-bit value is “00001” in binary.
100 ". Further, when the value V _{K of the} key signal is binary “110” (decimal “−2”), the 5-bit value obtained by shifting the key signal left by 2 bits is binary “110”.
00 ”, and the 8-bit value V _K ′ obtained by bit-expanding the 5-bit value becomes a binary number“ 11111000 ”.

The interpolation / component selection circuit 39 uses such 8
Using the bit value V _K 'and the pixel data stored in the register group, the interpolation data ID _Z is calculated for each luminance component according to the following expression (30).

[0079]

[Equation 7]

The above equation (30) makes it possible to accurately reproduce the pixel data before sampling.

The examples 1 to 5 of the key value calculation process and the pixel interpolation process have been described above. In the above Examples 1 to 5, the calculation method of the key signal and the interpolation data was described only for the luminance component (Y data), but the color difference components (U data, V data).
For, the known pixel interpolation method may be applied. Further, in the above Examples 4 and 5, the 3-bit key signal is used, but it is also possible to use the 4-bit or more key signal.

Embodiment 2. Next, a second embodiment of the present invention will be described. 17 and 18 show the data conversion circuit 5 ₂ according to the second embodiment of the present invention. FIG. 17
And FIG. 18 are continuous with each other through a one-dot chain line according to the positional relationship shown in FIG. Data conversion circuit 5 ₂ according to the second embodiment, the data writing and reading unit 2 shown in FIG. 17
6 ₂ and the interpolation unit 25 ₂ shown in FIG. It should be noted that, in FIGS. 17 and 18, the circuits denoted by the same reference numerals as those shown in FIGS. 2 and 3 have substantially the same configuration and function as those described above, and detailed description thereof will be omitted.

The sampling key signal calculation unit 20 ₂ of the data writing / reading unit 26 ₂ has a key signal calculation circuit 20 B for calculating a key signal and input data per pixel, as in the first embodiment. And a sampling circuit 20A for converting into data having a single component. In the second embodiment, the sampling circuit 20A has 8-bit Y data, 8-bit data obtained by combining the high-order 6 bits of 8-bit U data and the key signal, and high-order 6 bits of 8-bit V data. 8-bit data obtained by combining the bit and the key signal is input.

The key signal calculation circuit 20B may output a 3-bit key signal instead of outputting a 2-bit key signal. In such a case, 2 bits out of 3 bits of the key signal are combined with the upper bits of the color difference component (U data or V data), and the remaining 1 bit of the key signal is combined with the upper bits of the luminance component (Y data). In other words, 2 bits out of 3 bits of the key signal are stored in some bits of the color difference component, and the remaining 1 bit of the key signal is stored in some bits of the luminance component. The sampling circuit 20A needs to sample and output the 8-bit combined data of each color component including the key signal, and the first buffer memory 22 and the second buffer memory 23 need to store the 8-bit combined data. .

The first buffer memory 22 and the second buffer memory 23 have a storage capacity for storing combined data of 320 × 240 × 8 bits. Other configurations and functions of the data writing and reading unit 26 _2, the above-described embodiments 1
It is almost the same as that.

On the other hand, the interpolation unit 25 ₂ shown in FIG.
A register group 36 for storing 8-bit combined data of a 3-pixel area, FIFO memories 38A and 38B, and an interpolation / component selection circuit 39 are provided. The 8-bit width combined data output from the register group 36 is separated into 6-bit width pixel data and 2-bit width key signal and input to the interpolation / component selection circuit 39. Interpolation / component selection circuit 39
In the same manner as in the first embodiment, performs pixel interpolation processing individually according to the value V _{K of the} key signal, and outputs 8-bit wide field sequential data to the EVF 6.

As described above, the sampling / key signal calculating unit 20 ₂ of the _second embodiment includes the key signal in the lower 2 bits of the color difference components (U data, V data) which have less influence on human visual sensitivity. Therefore, the first buffer memory 2
2 and the storage capacity of the combined data stored in the second buffer memory 23 can be reduced. Therefore, the memory capacity can be reduced, the circuit scale can be suppressed small, and a low power consumption and low cost data conversion circuit can be realized.

The first and second embodiments of the present invention have been described above. Although the data conversion circuits according to the first and second embodiments are applied to the EVF 6 of the digital camera, the data conversion circuit according to the present invention does not need to be limited to the digital camera. The present invention can be applied to any interface that requires conversion from dot-sequential data to frame-sequential data and frame rate conversion.

[0089]

As described above, according to the data conversion circuit of the first aspect of the present invention, the input image data having a plurality of components per pixel is sampled into the image data having a single component per pixel and buffered. -Since it is stored in the memory, the storage capacity of the buffer memory can be small. Therefore, the circuit scale can be reduced and the cost can be reduced.
Further, although the amount of information of the input image data is reduced by the sampling unit, information on the correlation state between the pixel of interest of the image data before sampling and peripheral pixels is included in the key signal, and the pixel corresponding to the value of this key signal Since the interpolation processing is performed individually, it becomes possible to generate and output the interpolation data in which the image quality deterioration due to sampling is suppressed.

According to the second aspect, since the image data output from the sampling section and the key signal are combined and stored in the buffer memory, the storage capacity can be saved. Therefore, it is possible to reduce the circuit scale and power consumption.

According to the third aspect, the storage capacity required for the buffer memory can be reduced, so that the circuit can be downsized and the power consumption can be reduced.

According to the fourth aspect, the image data is alternately stored in the first buffer memory and the second buffer memory in frame units or field units, and the data is alternately output from these buffer memories. It is possible to display a moving image without a color shift phenomenon or a position shift phenomenon on a display device driven in a frame sequential manner.

According to the fifth aspect, it is possible to reduce the color shift phenomenon and output high quality frame sequential data to display a moving image.

According to the sixth aspect, it is possible to greatly reduce the position shift phenomenon and output high quality interpolation data to display a moving image.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an overall configuration of a digital camera incorporating a data conversion circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data writing / reading unit of the data conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an interpolation unit of the data conversion circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a mutual positional relationship between FIGS. 2 and 3;

FIG. 5 is an explanatory diagram showing a component array of data output by the sampling circuit of the data conversion circuit according to the first embodiment.

FIG. 6 shows 3 × of image data input to a key signal calculation circuit.
It is explanatory drawing which shows a 3 pixel area | region.

FIG. 7 is a diagram illustrating a spatial filter that performs a spatial filtering process.

FIG. 8 is a diagram illustrating a spatial filter having coefficient values for vertical line detection.

FIG. 9 is a diagram illustrating a spatial filter having coefficient values for horizontal line detection.

FIG. 10 is a diagram exemplifying a spatial filter having a coefficient value for diagonally downward-sloping detection.

FIG. 11 is a diagram exemplifying a spatial filter having a coefficient value for detecting a diagonal line rising to the right.

FIG. 12 is a diagram illustrating a spatial filter having coefficient values for vertical edge detection.

FIG. 13 is a diagram illustrating a spatial filter having coefficient values for horizontal edge detection.

FIG. 14 is a diagram exemplifying a spatial filter having a coefficient value for detecting a diagonal edge falling to the right.

FIG. 15 is a diagram exemplifying a spatial filter having a coefficient value for detecting an oblique edge rising to the right.

FIG. 16 is a diagram simply showing pixel data of 5 × 5 pixels.

FIG. 17 is a diagram showing a data writing / reading unit of the data conversion circuit according to the second embodiment of the present invention.

FIG. 18 is a diagram showing an interpolation unit of the data conversion circuit according to the second embodiment of the present invention.

19 is a diagram showing a mutual positional relationship between FIG. 17 and FIG.

FIG. 20 is a block diagram showing a schematic configuration of a conventional digital camera.

FIG. 21 is an explanatory diagram showing image data in an R, G, B dot-sequential format.

FIG. 22 is an explanatory diagram showing image data in an R, G, B frame-sequential format.

FIG. 23 is a schematic diagram for explaining a positional shift phenomenon.

FIG. 24 is a schematic diagram showing a data conversion circuit having a buffer memory for two frames.

[Explanation of symbols]

1 digital camera 4 Analog signal processor 5 Data conversion circuit 6 EVF 8 Image processing unit 9 main memory 10 bus 11 CPU 12 Display signal processor 13 LCD device 20 Sampling key signal calculator 21 Write Control Unit 22 First buffer memory 23 Second buffer memory 25 Interpolator 26 Data writing / reading section

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/14 H04N 1/40 D 5C079 9/07 1/46 ZF term (reference) 5B057 BA11 CA01 CA08 CA16 CB08 CB16 CE17 CH11 DA17 5C021 PA38 PA79 XB07 XB16 5C065 AA01 BB15 CC02 CC03 CC09 DD02 DD17 FF02 GG13 GG18 GG30 GG34 5C066 CA01 EC01 GA01 GA02 GA05 GA08 GA22 PP22 KR190804190822 NA10

Claims (6)

[Claims] 1. A sampling unit for sampling and outputting input image data having a plurality of components per pixel into image data having a single component per pixel, and a correlation state between a pixel of interest of the input image data and peripheral pixels. A key signal calculation unit that calculates a key signal having a corresponding value, and a write control unit that controls to store the image data output from the sampling unit and the key signal in a buffer memory in frame units or field units. Read control means for controlling the image data and the key signal stored in the buffer memory to be read in frame units or field units, and the image data read by the read control means. Pixel interpolation processing for interpolating a plurality of components per pixel individually according to the value of the key signal Line, and the data converting circuit comprising: a, an interpolation unit for outputting interpolated data subjected to pixel interpolation processing on the display device. 2. The data conversion circuit according to claim 1, wherein the write control unit stores combined data obtained by combining the image data output from the sampling unit and the key signal in the buffer memory. The data conversion circuit, wherein the interpolation section executes the pixel interpolation processing on the image data obtained by separating the combined data read from the buffer memory by the read control means. 3. The data conversion circuit according to claim 1, wherein the write control means stores in the buffer memory data in which the key signal is included in the lower bits of the image data output from the sampling section. A data conversion circuit, wherein the interpolation section extracts the image data and the key signal from the data read from the buffer memory by the read control means and executes the pixel interpolation processing. 4. The data conversion circuit according to claim 1, wherein the buffer memory includes a first buffer memory and a second buffer memory, and the write control means. For transferring the image data and the key signal to the first buffer memory and the second buffer memory.
The reading control means controls the memory and the memory so as to alternately store the data in a frame unit or a field unit, and in a period in which data is written in any one of the first buffer memory and the second buffer memory. , The data stored in the other memory is controlled to be read out in frame units or field units, and the interpolation unit extracts the components from the image data in a dot-sequential format in which the components are arranged in pixel units. A data conversion circuit that generates the interpolated data in a frame-sequential format arranged in frame units or field units. 5. The data conversion circuit according to claim 4, wherein the interpolation section generates the interpolation data in a frame sequential format at a frame rate different from a frame rate of the input image data. 6. The data conversion circuit according to claim 1, wherein the buffer memory includes a first buffer memory and a second buffer memory, and the write control means. The image data output from the sampling unit and the key signal,
The memory and the second buffer memory are controlled so as to be alternately stored in frame units or field units, and the read control means is one of the first buffer memory and the second buffer memory. During the period in which the data is written to the other memory, the data stored in the other memory is controlled to be read out in a frame unit or a field unit, and the interpolating unit performs the pixel interpolation at a frame rate different from the frame rate of the input image data. A data conversion circuit that executes processing and outputs the interpolation data.