JP2003110120A - Electrostatic surge protection element - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To reduce static electricity when the capacitance of an electrostatic surge protection element is large.
To semiconductor devices where the surge protection element is connected to the input side
Can meet the demands for faster input signals and higher frequencies.
There is a problem that can not be. SOLUTION: n⁺Main surface (surface) of the silicon substrate 11
N) on the side)⁻The mold layer 12 is provided by epitaxial growth.
The anode electrode 13 is electrically connected to the other main surface (back side).
Are provided in contact with each other. n⁻Select the surface layer of the mold layer 12
Alternatively, a p-type region 14 is formed, and a surface layer of the p-type region 14 is formed.
To the first n⁺A mold region 15 is formed, and
This 1n⁺Discontinuous area surrounding mold region 15
Region, n ⁻From the surface layer of the mold layer 12 to the surface layer of the p-type region 14
1n across⁺The second n⁺Mold area 1
8 are formed. And the 1n⁺Of the mold region 15
A cathode electrode 17 is provided on the surface in electrical contact.
You.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to electrostatic discharge (Elec
trostatic Discharge: Hereinafter, it relates to an electrostatic surge protection element that protects a semiconductor device from ESD).

[0002]

2. Description of the Related Art ESD is an important factor that causes damage or damage to a semiconductor device and affects the reliability of the semiconductor device. Conventionally, in order to protect a semiconductor device from ESD,
For example, as shown in FIG. 3, a method is known in which a constant voltage diode (zener diode) 2 designed to operate at a predetermined voltage or higher is provided on the input side of a semiconductor device 1. A general constant voltage diode used as an electrostatic surge protection element will be described with reference to FIG. A high concentration p type p ⁺ type guard ring region 4 is selectively formed by ion implantation or diffusion of boron as an impurity in the surface layer of one main surface (front surface side) of the high concentration n type n ⁺ type silicon substrate 3. Then, the p ⁺ type region 5 is formed surrounded by the guard ring region 4, and the silicon oxide film 6 is formed on the surface of the silicon substrate 3. An anode electrode 7 made of a metal connected to the A terminal is provided in electrical contact with the surface of the p ⁺ type region 5 through the opening of the silicon oxide film 6. Further, a cathode electrode 8 made of a metal connected to the K terminal is provided in electrical contact with the surface of the other main surface (back surface side) of the silicon substrate 3. With the above configuration, a single PN junction J1 is formed in series between the anode electrode 7 and the cathode electrode 8 by the guard ring region 4, the p ⁺ type region 5 and the n ⁺ type silicon substrate 3. And this PN
The junction J1 has a parasitic capacitance C1 proportional to the junction area.

[0003]

By the way, in order to meet the demands for high speed and high frequency of the input signal to the semiconductor device,
It is necessary to reduce the parasitic capacitance C1 of the constant voltage diode, but if the parasitic capacitance C1 is reduced by reducing the junction area of the PN junction J1 that is in a proportional relationship, the ESD withstand value that is in a trade-off relationship with the junction area is reduced. There is a problem of going down. The present invention has been made in view of the above problems, and an object thereof is to provide an electrostatic surge protection element in which parasitic capacitance is reduced without reducing the junction area.

[0004]

In a device for protecting electrostatic surges according to the present invention, a low concentration n-type layer is epitaxially grown on one main surface, and an anode electrode is electrically contacted on the other main surface. A high-concentration n-type semiconductor substrate, a p-type region selectively formed on the surface layer of the low-concentration n-type layer, and a p-type region selectively formed on the surface layer of the p-type region. High-concentration first n provided with a cathode electrode in electrical contact therewith
And a high-concentration second n-type region formed simultaneously with the high-concentration first n-type region over the surface layer of the low-concentration n-type layer and the surface layer of the p-type region. .

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION A bidirectional diode as an electrostatic surge protection element according to an embodiment of the present invention will be described below with reference to FIG. One main surface n which is a low concentration n-type on (the surface side) of the n ⁺ -type silicon substrate 11 is a high concentration n-type ^- -type layer 12 is provided by epitaxial growth, on the other main surface (back side) An anode electrode 13 made of metal and connected to the A terminal is provided in electrical contact. A p-type region 14 of p-type having a higher concentration than that of the n ⁻ -type layer 12 is selectively formed in the surface layer of the n ⁻ -type layer 12 by ion implantation or diffusion of boron as an impurity.
4n, the first n ⁺ type region 15 is selectively formed by ion implantation or diffusion of phosphorus or arsenic as an impurity, and further, in the circumferentially discontinuous region surrounding the first n ⁺ type region 15, n is formed. ^{− From} the surface layer of the mold layer 12 to the p-type region 1
The second n at the same time as the first n ⁺ type region 15 across the fourth surface layer.
^{The +} type region 18 is formed, and the silicon oxide film 16 is formed on the surface of the n ⁻ type layer 12 on which the ⁺ type region 18 is formed.
A cathode electrode 17 made of a metal connected to the K terminal is provided in electrical contact with the surface of the first n ⁺ type region 15 through the opening of the silicon oxide film 16.

With the above structure, the p-type region 14 and the first n ⁺ -type region 15 are provided between the cathode electrode 17 and the anode electrode 13.
A reverse-connection PN junction J2 composed of 2 and a forward-connection PN junction J3 composed of the p-type region 14 and the n ⁻ -type layer 12.
Two PN junctions J2 and J3 are connected in series, and
^The second n extending from the surface layer of the n ⁻ type layer 12 to the surface layer of the p type region 14 in a circumferentially discontinuous region surrounding the ⁺ type region 15.
By forming the ⁺ type region 18, the PN junction J4 of the forward connection composed of the p type region 14 and the second n ⁺ type region 18 is formed.
Are connected in parallel to the PN junction J3.

The voltage-electricity of the bidirectional diode having the above structure
The current characteristics are as shown in Fig. 2 when the A terminal is set to ground potential.
When a positive voltage is applied to the K terminal side, a positive voltage is applied, and a negative voltage is applied.
The positive voltage is applied to the K terminal side when the voltage is applied in the-direction.
If it does, the breakdown voltage slightly higher than the breakdown voltage of the PN junction J2.
Voltage V_BO1(Phase to Vz of constant voltage diode
A breakdown occurs, and then the transistor
The breakdown voltage decreases sharply due to the effect,
It becomes a closet waveform. Also, a negative voltage was applied to the K terminal side.
In this case, since the PN junction J4 is formed, the PN junction
It does not become higher than the breakdown voltage of J4, and is a little less than the PN junction J4.
High, that is, breakover voltage V _BO1Almost equal to
New breakover voltage V_BO2Breaks down
And then breakdown voltage V_BO2Current I_BOBut
After the current flows, the breakdown voltage decreases sharply due to the transistor effect.
It becomes a little negative resistance waveform. like this
The breakover voltage V_BO1And breakover voltage
V_BO2And can be approximately equal. By this
If the semiconductor device 1 is a MOSIC, if a break
Over voltage V_BO2> V_BO1Then, the gate oxidation of the input section
Membrane withstand voltage is V_BO2If it is smaller, the semiconductor device 1 is negative.
There is a risk of damage due to excessive voltage input.
Voltage V_BO2= V_BO1Because of the negative voltage over-input
Can also be protected against.

With the above configuration, the parasitic capacitances C3 and C4 of the PN junctions J3 and J4 are connected in parallel, and the capacitance Cp when these are connected in parallel is expressed by the equation (1). Furthermore, the capacitance Cp and the PN junction J2 are connected. The parasitic capacitance C2 is connected in series, and the capacitance Cw when connected in series is expressed by the equation (2). Cp = C3 + C4 ... (1) Cw = C2 × Cp / (C2 + Cp) ... (2)

Next, regarding the capacitance when the applied voltage = 0 V, the capacitance C of the PN junction J1 of the constant voltage diode described above is used.
Compare with 1. First, assuming that the junction area of the PN junction J2 is equal to the junction area of the PN junction J1 and the n-type impurity concentration of the first n ⁺ type region 15 is substantially equal to that of the n ⁺ type silicon substrate 3, the P side of the PN junction J2 is assumed. Since the p-type impurity concentration of a certain p-type region 14 is lower than that of the guard ring region 4 and the p ⁺ -type region 5 on the P side of the PN junction J1, the PN junction J
The spread of the depletion layer 2 is larger than that of the PN junction J1, and the parasitic capacitance C2 is smaller than C1. Further, when the junction area of the PN junction J2 is made larger than the junction area of the PN junction J1 in order to make the ESD tolerance larger than that of the constant voltage diode, the parasitic capacitance C2 becomes larger than that when the junction areas are equal.
Considering the above relationship, for example, it is assumed that C2 is designed so as to satisfy the expression (3). C2≈C1 ... (3)

Next, since the junction area of the PN junction J3 is larger than that of the PN junction J2, the parasitic capacitance C3
Is larger than when the junction area is equal to the junction area of the PN junction J2. However, since the n ⁻ type layer 12 on the N side of the PN junction J3 is formed by epitaxial growth,
The n-type impurity concentration of the n ⁻ -type layer 12 can be made lower than that of the first n ⁺ -type region 15 on the N side of the PN junction J2 by, for example, one digit or more. Therefore, the spread of the depletion layer of the PN junction J3 can be reduced. It can be made larger than the PN junction J2, and the parasitic capacitance C3 can be made half or less of the parasitic capacitance C2≈C1. From the above, for example, it is assumed that C3 is designed so as to satisfy the expression (4). C3≈C1 / 2 ... (4)

Next, in the PN junction J4, the p-type impurity concentration on the P-side and the n-type impurity concentration on the N-side are determined by the PN junction J2.
Same as, but the junction area of PN junction J4 is PN junction J
It can be designed to be much smaller than that of 2, so the parasitic capacitance C4
Is almost negligible with respect to the parasitic capacitance C2.
From the above, it is assumed that C4 is represented by the equation (5). C4≈0 ... (5)

From the above, when the expressions (4) and (5) are substituted into the expression (1), the expression (6) is obtained. Cp≈C1 / 2 (6) Further, by substituting the equations (3) and (6) into the equation (2), it is represented by the equation (7), and the capacitance is about one-third of that of the constant voltage diode. Can be reduced to Cw≈C1 × (C1 / 2) / (C1 + C1 / 2) = C1 / 3 (7)

Next, the operation when this bidirectional diode is used as an electrostatic surge protection element of the semiconductor device 1 in place of the constant voltage diode 2 shown in FIG. 3 will be described.

First, when the input signal of the semiconductor device 1 is supplied to the K terminal at the breakover voltage V _BO1 or less with the A terminal as the ground potential, the bidirectional diode is connected to the PN junction J.
2 is applied in the reverse direction, and the depletion layer spreads to the p-type region 14 side, so that the parasitic capacitance Cw becomes lower than when the applied voltage is 0 V, and the input signal of the semiconductor device 1 protected from ESD is increased in speed and high frequency. Can meet the demand for

Next, the A terminal is set to the ground potential and the K terminal is connected to the E terminal.
When an SD voltage is applied, the bidirectional diode will
As shown in FIG. 4, after the breakdown is once caused by the breakover voltage V _BO1 , the current due to the ESD flows in a state where the breakdown voltage becomes low due to the negative resistance waveform due to the transistor effect. ESD breakdown in a PN junction is generally caused by local thermal breakdown due to breakdown voltage × breakdown current. Therefore, as shown in FIG. 2, when the breakover voltage V _BO1 of the bidirectional diode is set to be the same as Vz of the constant voltage diode, the bidirectional diode has a breakdown voltage due to the negative resistance waveform, so that the thermal breakdown is reduced. It is possible to increase the breakdown current value as the ESD withstand level up to the value of the constant voltage diode, and to increase the ESD withstand value that can absorb the ESD voltage in the bidirectional diode. In the above embodiment, the second n ⁺ type region 18 has been described as being formed in a circumferentially discontinuous region surrounding the first n ⁺ type region 15, but it may be formed in a ring shape. Good.

[0016]

According to the electrostatic surge protection device of the present invention, the reverse connection PN junction J2 consisting of the p-type region and the high-concentration n-type region is provided between the cathode electrode and the anode electrode, and the p-type region and the low-resistance region. By forming a configuration in which two PN junctions, which are the forward connection PN junction J3 formed of the concentration n-type layer, are connected in series, the parasitic capacitances C2 and C3 are also connected in series, and the sum Cw of the capacitances is constant. It can be made smaller than the parasitic capacitance C1 of the PN junction J1 of the voltage diode, and the breakdown voltage-current waveform of this element becomes a negative resistance waveform, and the ESD withstand capability becomes higher than that of the constant voltage diode.
By using this electrostatic surge protection element, ESD
It is possible to meet the demand for higher speed and higher frequency of the input signal of the semiconductor device protected from the above. In addition, in the circumferentially discontinuous region surrounding the high-concentration first n-type region, the high-concentration first n-type region and the high-concentration second n-type region are spread from the surface layer of the low-concentration n-type layer to the surface layer of the p-type region. Since the region is formed, the breakover voltage V _BO can be made substantially equal to each other bidirectionally with almost no increase in capacitance, and a semiconductor device protected from ESD after being protected against over-input of a negative voltage. It is possible to meet the demand for high speed and high frequency of the input signal.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a bidirectional diode according to an embodiment of the present invention.

FIG. 2 is a voltage-current characteristic diagram of the bidirectional diode shown in FIG.

FIG. 3 is a circuit diagram using a conventional electrostatic surge protection element.

FIG. 4 is a sectional view of a main part of a constant voltage diode.

[Explanation of symbols]

11 n ⁺ type silicon substrate 12 n ⁻ type layer 13 anode electrode 14 p type region 15 first n ⁺ type region 16 silicon oxide film 17 cathode electrode 18 second n ⁺ type region

Claims (2)

[Claims] 1. A high-concentration n-type semiconductor substrate in which a low-concentration n-type layer is epitaxially grown on one main surface, and an anode electrode is provided in electrical contact on the other main surface, and a low-concentration n-type semiconductor substrate. A p-type region selectively formed on the surface layer of the n-type layer, and a high-concentration p-type region selectively formed on the surface layer of the p-type region, in which a cathode electrode is provided in electrical contact with the surface. First
An electrostatic surge protection element comprising an n-type region and a high-concentration second n-type region formed at the same time as the high-concentration first n-type region extending from the surface layer of the low-concentration n-type layer to the surface layer of the p-type region. 2. The high concentration second n-type region is the high concentration first n-type region.
The electrostatic surge protection device according to claim 1, wherein the device is formed in a circumferentially discontinuous region surrounding the n-type region.