JP2003110111A - Semiconductor device simulation method and semiconductor element - Google Patents

Abstract

(57) Abstract: In a semiconductor device using a polycrystalline semiconductor for an active layer, a polycrystalline semiconductor device having an optimized structure is obtained. SOLUTION: In a polycrystalline silicon thin film transistor in which a carrier transport mechanism of a crystal grain boundary is particularly dominant for transistor characteristics, a carrier flow density passing through a crystal grain boundary in an active layer is reduced by a free carrier at a crystal boundary. The calculation is performed in consideration of the scattering effect, and the parameters governing the device characteristics are determined based on the calculation. Preferably, the Thermic Ionic Emission (Thermiconic)
Emission) effect is considered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a polycrystalline thin film transistor using a polycrystalline semiconductor in its active layer.

[0002]

2. Description of the Related Art A polycrystalline thin film transistor is a semiconductor element using a polycrystalline semiconductor in an active layer, and is used to realize a light and thin display device represented by a liquid crystal display or an electroluminescence display, and a device such as a scanner. Widely used as a device.

Generally, prior to the manufacture of a semiconductor element, a device simulation is performed in which the device characteristics are predicted using the structure of the device and the physical properties of materials used as parameters, and the device operation is analyzed. The final device structure and manufacturing conditions are determined.

Therefore, even if it is possible to predict the device characteristics in the development stage with high accuracy even for a polycrystalline thin film transistor, it is expected that it can be a useful tool for optimizing the device structure. No effective device simulation method has been proposed for a crystalline thin film transistor, and as a result, there has been a problem that it is difficult to determine the structure and manufacturing conditions of a polycrystalline thin film transistor having desired device characteristics.

[0005]

DISCLOSURE OF THE INVENTION The inventor of the present invention has made a detailed study on the problems in applying the conventional device simulation method to a polycrystalline thin film transistor, and as a result, determined the device structure of the polycrystalline thin film transistor. In order to determine the device structure, etc., the carrier transport phenomenon in the crystal should be handled accurately in consideration of the carrier scattering phenomenon at the grain boundary that exists at high density in the active layer of polycrystalline semiconductor. It turned out to be extremely important.

Therefore, an object of the present invention is to calculate the carrier flow density flowing in the active layer based on a device simulation that accurately handles the carrier scattering effect at the crystal grain boundaries in the active layer, and to calculate the device based on this value. It is to provide a polycrystalline thin film transistor designed by determining parameters.

[0007]

In order to achieve the above object, a device simulation method for a polycrystalline semiconductor device according to the present invention is a device simulation method for a polycrystalline semiconductor device using a polycrystalline semiconductor in an active layer. It is characterized in that the scattering effect of carriers in the field is taken into consideration.

With such a structure, in order to obtain a semiconductor element having an optimized device structure in a laser crystallized polycrystalline silicon thin film transistor in which a carrier transport mechanism of a crystal grain boundary is particularly dominant for transistor characteristics. Can be simulated.

Preferably, the thermoionic emission effect at the crystal grain boundary is taken into consideration.

Preferably, the carrier current density J _t passing through the crystal grain boundary is represented by the following equation.

J _t = (1-c / 2) v (n ₁ -n ₂ ) / 4 (1-c / 2) v / 4 = A ^* T ² / (qN _e ) J _t : Carrier flow density c : Ratio of carrier flow trapped in grain boundaries v: Average electron thermal velocity n ₁ : Carrier density on one side of grain boundary n ₂ : Carrier density on other side of grain boundary A ^* : Effective Richardson constant T: Absolute Temperature q: Elementary charge N _e : Effective state density Preferably, the polycrystalline semiconductor element is a polycrystalline silicon thin film transistor, which is a thin film transistor using polycrystalline silicon for an active layer.

Preferably, the polycrystalline semiconductor element is a laser-crystallized polycrystalline silicon thin film transistor in which polycrystalline silicon is used for an active layer and polycrystalline silicon is crystallized by a laser crystallization process. And

In the semiconductor device of the present invention, the carrier flow density (J _t ) is calculated by the following equation in consideration of the scattering effect of free carriers at the crystal grain boundaries in a semiconductor device using a polycrystalline semiconductor in the active layer. Then, based on this, the parameters that govern the device characteristics are determined and designed.

[0014] _{J t = (1-c /} 2) · v · (n 1 -n 2)
/ 4 c: ratio of carrier flow trapped in crystal grain boundary v: average electron thermal velocity n ₁ : carrier density on one side of crystal grain boundary n ₂ : carrier density on other side of crystal grain boundary Preferably, the above semiconductor device Is a polycrystalline silicon thin film transistor using polycrystalline silicon in the active layer, and more preferably, a polycrystalline silicon thin film transistor manufactured by performing polycrystallization of the active layer by a laser crystallization process. As a result, a semiconductor element having an optimized device structure can be obtained in a laser-crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of grain boundaries is particularly dominant for transistor characteristics.

[0015]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device of the present invention will be described in detail below with reference to the drawings. (Carrier Flow Density at Crystal Grain Boundary) FIG. 4 is a diagram showing a structure of a polycrystalline silicon thin film transistor configured by using polycrystalline silicon for the active layer.

In the polycrystalline silicon thin film transistor shown in FIG. 4, first, a polycrystalline silicon film is formed on a substrate 16 by a CVD method, and a gate is formed on the polycrystalline silicon film by a silicon oxide film grown by a thermal oxidation method. The insulating film 17 is formed. Then, the gate electrode 18 is formed on the gate oxide film, and the polycrystalline silicon film under the gate electrode 18 is operated as a gate region. Further, the polycrystalline silicon film regions that sandwich the gate region from the left and right act as a source region 14 and a drain region 15 to operate as a polycrystalline thin film transistor. In FIG. 4, a straight line that obliquely penetrates through the polycrystalline silicon film from the substrate 16 toward the gate insulating film 17 is a crystal grain boundary 13 formed by silicon crystals having different crystal orientations that form the polycrystalline silicon film. Is.

The characteristic of the polycrystalline thin film transistor as compared with the single crystal thin film transistor is that since the semiconductor film forming the active layer of the transistor is composed of polycrystal, crystal grains having different crystal orientations in the active layer. Exists,
As a result, there is a crystal grain boundary 13 between each crystal grain.

In general, it is known that the crystal grain boundaries act as trap centers for carriers, and carrier traps are present at a high density near the crystal grain boundaries. Once the carriers are trapped by the trap, so-called "potential barrier" is formed in which the electric charge is locally accumulated by the amount of the electric charge of the trapped carrier (for example, M.K.
imura et al. : J. Appl. Phys.
89 (2001) 596). Then, when a potential barrier is formed at the crystal grain boundary by capturing carriers,
Free carriers having lower thermal excitation energy than this potential barrier cannot pass through the grain boundaries.

On the other hand, not all free carriers having a thermal excitation energy higher than this potential barrier can freely pass through the crystal grain boundary, and such free carriers are also called "Thermionic Emissio".
It is known to undergo scattering by "n" (eg,
S. M. Sze: Physics of Semico
ndector Devices, 2nd Editi
on (John Wiley & Sons, New Yo
rk, 1981)).

As described above, the transport phenomenon of free carriers in the vicinity of crystal grain boundaries in a polycrystalline semiconductor that essentially contains crystal grain boundaries at a high density is based solely on the statistical distribution of thermal energy of the free carriers. It is not sufficient to analyze, and it is necessary to fully consider the carrier traps and potential barriers existing at the grain boundaries, and the carrier scattering phenomenon due to thermionic emission.

Therefore, in the design of the semiconductor device of the present invention, the carrier transport phenomenon is dealt with in consideration of the carrier scattering effect at the crystal grain boundaries, which was ignored in the conventional device design stage. More specifically,
Thermionic Emissi at grain boundaries
It is handled in consideration of the on effect.

Expressing this handling by a mathematical expression, the carrier flow density (J _t ) passing through the crystal grain boundary is given by J _t = (1-c / 2) v (n ₁ -n ₂ ) / 4 To be Here, c is the rate at which the carrier flow is trapped in the crystal grain boundaries, v is the average thermal velocity of electrons, and n ₁ and n ₂ are the carrier densities on one side and the other side of the crystal grain boundaries.

In addition, the above relational expression is converted into the effective Richard.
Using the son constant A ^* and the effective density of states N _e , J _t = (based on the relational expression of (1-c / 2) · v / 4 = A ^* · T ² / (q · N _e ). _{^{n 1 -n 2) · a *}} · T 2 / (q · n e) and may be expressed. Here, T is absolute temperature and q is elementary charge.

These equations are basically based on the band structure theory of semiconductor materials, but the final result is that the carrier flow density (J _t ) is the difference (n) between the carrier densities on both sides of the grain boundary. _It is extremely simple and proportional to ₁₋ n ₂ ).

Here, the effective Richardson constant A
^* Is a constant that depends on the quality of the crystal grain boundary, and is large when the crystal orientations are aligned or when adjacent crystal grains are normally connected, and the carrier flow density J _{t in} that case has a large value. On the other hand, when the crystal orientations are not uniform or when an oxide film exists at the crystal grain boundaries, the effective Richards
The on constant A ^* is small and the carrier flow density J _t is a small value. Note that the effective Richardson constant A ^* of carefully produced high-quality polycrystalline silicon is 110 A /
It is known to be cm ² / K ² .

1 and 2 show the potential distribution (FIG. 1) and the vicinity of the grain boundaries in the vicinity of the grain boundaries, with and without the consideration of the Thermionic Emission effect based on the above theoretical consideration. It is a result of comparing the free carrier density distributions (Fig. 2) of. In any case, it is assumed that the crystal grain boundary exists at the position of 0 nm, and the relative distance from the crystal grain boundary is plotted on the horizontal axis.

According to FIG. 1, Thermionic E
When the simulation is performed in consideration of the mission effect, the relative position from the crystal grain boundary tends to decrease from the negative side to the positive side, and the potential value tends to decrease, especially in the vicinity of the crystal grain boundary position. There is a potential drop.

On the other hand, thermionic E
When the mission effect is not considered, the relative value from the crystal grain boundary tends to decrease in potential value from the negative side to the positive side, but the maximum value of the potential value appears at the crystal grain boundary position. This means that a potential barrier exists at the grain boundary position.

That is, in the carrier transport phenomenon, T
In consideration of the hermionic emission effect, the resistance at the crystal grain boundary caused by the thermionic emission effect becomes dominant for carrier transport, so that a potential drop occurs at the crystal grain boundary and the potential barrier disappears. , The
When the rmionic emission effect is not taken into consideration, it appears as a qualitative difference that the resistance at the crystal grain boundary due to the potential barrier formed at the crystal grain boundary becomes dominant for carrier transport.

This qualitative difference has a very important meaning in the design of a polycrystalline semiconductor device which essentially contains a high density of crystal grain boundaries.

Further, reflecting the difference in the potential distribution, there is a large difference in the simulation result of the free carrier density distribution between the case where the Thermionic Emission effect is taken into consideration and the case where it is not taken into consideration. The result is shown in FIG.

Thermionic Emission
Considering the effect, the free carrier density distribution becomes asymmetric on both sides of the crystal grain boundary in order to generate the carrier flow density passing through the crystal grain boundary, and a sharp drop in the free carrier density is observed at the crystal grain boundary. . On the other hand, Th
When the ermionic emission effect is not taken into consideration, the free carrier density shows a symmetrical distribution across the grain boundaries, and at the same time shows a gradual drop in the grain boundaries. In addition to such a qualitative difference, a large difference is observed in the carrier flow density value itself near the crystal grain boundary.

In this way, the Thermionic Em
There is a big difference between the simulation result of the potential distribution and the simulation result of the free carrier density distribution when the effect is considered and when it is not considered.
The carrier transport mechanism in a semiconductor device including a high density of crystal grain boundaries can be correctly expressed only by considering the ermonic emission effect, and a highly accurate device simulation of a polycrystalline semiconductor device becomes possible. (Design Procedure of Semiconductor Element of the Present Invention) Next, the procedure for optimizing the device parameters of the semiconductor element to be designed by the above-described device simulation method will be described below.

FIG. 5 is a block diagram showing a device simulator for simulating the device characteristics of the semiconductor device of the present invention.

The device simulator 31 includes the control means 3
2, input means 33, calculation means 34, output means 35
The control means 32 is a means for controlling the entire device simulator 31.

The input means 33 includes a simulation condition input means 36 for inputting a simulation condition such as a gate voltage to be applied, a structure / shape of a semiconductor element, a grain size of a polycrystalline crystal which operates as an active layer, and the like. Device structure input means 3 for inputting crystallinity parameters
7, the calculation means 34 includes a carrier flow density calculation means 38 for calculating the density of the carrier flow flowing in the active layer based on the above-mentioned theory, and the result and the kind of species input by the input means 33. Device characteristic calculation means 3 for calculating desired device characteristics based on the conditions
It is composed of 9.

FIG. 6 shows a processing procedure when the device simulator 31 executes a device simulation.

First, the simulation data such as the gate voltage condition of the semiconductor element is input by the simulation condition input means 36 of the input means 33 (S46).

Data concerning the device structure such as the structure and shape of the semiconductor element is also input to the device structure input means 37.
Is input from (S47). Here, the device structure data is, for example, the gate oxide film thickness, the source / drain spacing, the crystallinity of the active layer, the contact hole shape, the wiring shape, the dopant concentration, etc., and can be freely set according to the device to be designed. It can be set. The device structure data may be directly input by a user of the device simulator 31, or may be data input by a process simulator provided separately from the device simulator 31. Is also good.

The carrier flow density calculation means 38 receives the device structure data from the device structure input means 37 and calculates the carrier flow density based on the above relational expression.

Then, the device characteristic calculating means 39 receives the simulation data and the calculated carrier flow density value and calculates device characteristics such as CV characteristics (S49), and the result is output by the output means 35. To be done.

The user of the device simulator 31 repeats the procedure shown in FIG. 6 while comparing the output device characteristics with the design characteristics, and thereby the gate oxide film thickness, the source / drain distance, and the crystal of the active layer. The device structure such that the desired characteristics can be obtained by optimizing the device parameters such as characteristics, contact hole shape, wiring shape, and dopant concentration. (Polycrystalline Thin Film Transistor Considering Crystal Grain Boundary) Next, a manufacturing process of a thin film transistor of the present invention having a device structure determined by the above device simulation will be described with reference to the drawings.

FIG. 3 is a diagram showing a manufacturing process of the polycrystalline thin film transistor of the present invention. In this embodiment, a case where a silicon thin film is formed as a semiconductor layer for forming a transistor on an insulating substrate such as glass will be described as an example. The polycrystalline silicon thin film transistor of this example is a laser crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of crystal grain boundaries is particularly dominant for transistor characteristics.

First, a silane-based reactive gas is used as a silicon atom supply source on the insulating substrate 1, for example, low pressure CVD using disilane (Si ₂ H ₆ ) gas.
(LPCVD) method or plasma enhancement CVD (PECV) using, for example, monosilane (SiH ₄ ) gas
The amorphous silicon film 2 is formed by the method D). Here, the silicon film 2 is formed so that the film thickness thereof is a film thickness calculated in advance as an optimum film thickness by the device simulation described above.

Subsequently, the formed amorphous silicon film 2 is recrystallized by supplying energy necessary for crystallization of amorphous silicon atoms from the outside to form a polycrystalline silicon film 2. (Fig. 3
(A)). Here, the crystallinity such as the grain size and crystal orientation of the polycrystal is set in advance so that various characteristics such as the required carrier mobility can be obtained by the above device simulation. Further, in the recrystallization method, an optimum method and conditions are selected in order to realize such crystallinity. For example, as shown in FIG. 3A, a laser crystal for light irradiation using an excimer laser or the like is used. A chemical treatment method or a method of performing solid phase growth by performing heat treatment in a heat treatment furnace is selected.

The polycrystalline silicon film 2 thus formed is subjected to desired patterning by using a photolithography technique, and further a dielectric film 3 to be used later as a gate oxide film is formed. It This dielectric film is, for example, a silicon oxide film (SiO _x ) formed by a thermal CVD method, and is deposited on the entire surface of the substrate (FIG. 3).
(B)).

Next, impurity doping is performed on the active layer, but an ion implantation method is adopted which enables easy and accurate doping level control with high precision. The type of element to be doped is determined by the design of the thin film transistor, but in the case of the present embodiment, the case of an n-type thin film transistor is shown, and the group III impurity boron (B) that acts as an acceptor in the silicon crystal is shown. ) Is injected (FIG. 3 (b)). The doping amount to be ion-implanted is set to a value calculated in advance by simulation.

Following the doping process into the active layer, a thin film for forming the gate electrode 4 is formed. After depositing a thin film of metal or polysilicon selected as a gate electrode material on the entire surface of the substrate by a CVD method or a sputtering method, patterning is performed by photolithography so as to obtain a desired gate electrode shape (FIG. 3).
(C)).

Further, in order to make the conductivity type of the source region 5 and the drain region 6 n ⁺ type, for example, phosphorus (P) is ion-implanted (FIG. 3C). In this step, the already patterned gate electrode 4 is used as a mask to implant phosphorus (P) in a self-aligned manner. That is, there is no phosphorus implantation into the polycrystalline silicon film region immediately below the gate electrode, and the state in which boron ions are implanted in the step of FIG. 3B is maintained.

After the implantation of boron into the active layer region and the implantation of phosphorus into the source region 5 and the drain region 6, the crystal lattice state disturbed by these ion implantations is restored, and boron and phosphorus are used as dopants to generate an electrical charge. Processing for activating the image is performed.

Various methods are known as the method for activating the above-mentioned dopants. However, if a thermal activation method for holding the substrate at a high temperature for a long time is selected, the dopant activation can be executed with a simple apparatus. There is an advantage that a thin film transistor can be manufactured at low cost. Further, the dopant activation is not limited to the above thermal activation method, and may be, for example, a laser activation method. When the dopant activation is performed by the laser activation method, the same laser light source as the laser used in the crystallization process of the amorphous silicon thin film shown in FIG. 3A may be used. A laser light source having another different wavelength may be provided and used.

Subsequent to the activation of the dopant, an interlayer insulating film 7 for electrically insulating the individual transistors formed on the substrate from each other is formed (FIG. 3D), and further,
The dielectric film 3 and the interlayer insulating film 7 formed on the source region 5 and the drain region 6 are removed by photolithography to open contact holes, and then thin films for the source electrode 8 and the drain electrode 9 are deposited. After that, the source electrode 8 and the drain electrode 9 are patterned. In this way, a polycrystalline thin film transistor is completed (FIG.
(D)).

In the above-mentioned embodiment, an example in which the ion implantation method with mass spectrometry of the dopant is selected as the doping method for the active layer is shown, but the doping method is not limited to this. That is, another doping method may be used in which doping is performed without mass spectrometry of the dopant. In particular, when adopting the ion doping method without mass spectrometry, structural defects such as dislocations existing at the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to the ion doping, and electrical charges such as fixed electric charges. There is an advantage that it is possible to reduce the physical defects. On the other hand, when the ion implantation method accompanied by mass spectrometry is adopted, structural defects such as dislocations or fixed charges induced in the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to excessive ion bombardment are used. It is possible to suppress electrical defects such as. Therefore, an optimum method may be appropriately selected to obtain desired characteristics of the thin film transistor.

Further, the doping of the active layer does not have to be performed after the step of polycrystallizing the amorphous silicon layer, and may be performed simultaneously with the film formation of the amorphous silicon. For example, in the case of performing doping by an ion doping method, an amorphous silicon film is formed by using a gas containing a silicon element, which is a base material of a transistor, and a gas containing a dopant element at the same time, so as to contain impurities serving as a dopant. An amorphous silicon film is obtained.

It is needless to say that the impurity doping process for the active layer region, the source region and the drain region may be set in any manufacturing process order as long as the doping of those layers is realized. The active layer region need not be doped.

In this embodiment, the device simulation method of the present invention is applied to the polycrystalline silicon thin film transistor using polycrystalline silicon for the active layer.
It can also be applied to a polycrystalline semiconductor device using other polycrystal such as GaAs in the active layer.

[0057]

As described above, according to the present invention,
It is possible to obtain a semiconductor element having an optimized device structure in a polycrystalline silicon thin film transistor in which the carrier transport mechanism of crystal grain boundaries is particularly dominant for transistor characteristics.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a polycrystalline silicon thin film transistor.

FIG. 2 is a Thermionic Emissi.
It is the figure which compared the potential distribution in the vicinity of a grain boundary in the case of considering the on effect and in the case of not considering the effect.

FIG. 3 is a Thermionic Emissi.
FIG. 3 is a diagram comparing free carrier density distributions near a crystal grain boundary in the case where the on effect is considered and in the case where the effect is not considered.

FIG. 4 is a diagram illustrating a manufacturing process of a polycrystalline silicon thin film transistor.

FIG. 5 is a block diagram of a device simulator for manufacturing a semiconductor device of the present invention.

FIG. 6 is a flowchart for explaining the operation of the device simulator for manufacturing the semiconductor device of the present invention.

[Explanation of symbols]

13 grain boundaries 14 Source area 15 drain region 16 substrates 17 Gate insulating film 18 Gate electrode

Claims (8)

[Claims] 1. A device simulation method for a polycrystalline semiconductor device, which uses a polycrystalline semiconductor for an active layer, wherein a scattering effect of carriers at a grain boundary is taken into consideration. . 2. The device simulation method according to claim 1, wherein the thermo-ionic emission in the crystal grain boundary is taken into consideration. 3. The device simulation method according to claim 2, wherein the carrier flow density passing through the crystal grain boundary is represented by the following formula. _{J t = (1-c /} 2) v (n 1 -n 2) / 4 (1-c / 2) v / 4 = A * T 2 / (qN e) J t: carrier flow density c: carrier flow Are trapped in the crystal grain boundaries v: Average electron thermal velocity n ₁ : Carrier density on one side of the crystal grain boundary n ₂ : Carrier density on the other side of the crystal grain boundary A ^* : Effective Richardson constant T: Absolute temperature q: Elementary charge N _e : Effective density of states 4. The device simulation method according to claim 1, wherein the polycrystal semiconductor element is a polycrystal silicon thin film transistor which is a thin film transistor using polycrystal silicon for an active layer. A device simulation method for a polycrystalline semiconductor device, which is characterized. 5. The device simulation method according to claim 1, wherein the polycrystalline semiconductor element uses polycrystalline silicon for an active layer, and a polycrystalline silicon crystal is formed by a laser crystallization process. A method for simulating a polycrystalline semiconductor element, which is a laser-crystallized polycrystalline silicon thin film transistor, which is characterized by: 6. A semiconductor device using a polycrystalline semiconductor in an active layer, comprising a carrier flow density (J) passing through a crystal grain boundary in the active layer.
The _{t) J t = (1-} c / 2) · v · (n 1 -n 2) / 4 c: ratio carrier flow are trapped in the crystal grain boundaries v: electron mean thermal velocity n _1: crystal grain boundary Carrier density n ₂ on one side of: a semiconductor element designed by calculating the carrier density on the other side of the crystal grain boundary, and determining device parameters based on the calculated carrier flow density. 7. The semiconductor element according to claim 6, wherein the semiconductor element is a polycrystalline thin film transistor using polycrystalline silicon for an active layer. 8. The semiconductor device according to claim 6, wherein the semiconductor device is a polycrystalline thin film transistor manufactured by performing polycrystallization of an active layer by a laser crystallization process.