JP2003109960A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a wiring trench can be filled with Cu of huge grains. SOLUTION: A Cu film 8 of 100 nm thick is deposited on TaN 7 by sputtering, and a Cu film 9 of 500 nm thick is formed thereon by electrolytic plating. Subsequently, an RF bias is applied onto a substrate and the growing surface is irradiated with argon ions, thus forming a Cu layer 10 of 700 nm thick thicker than the total thickness of the Cu films 8 and 9 by sputtering. When it is heat-treated, a huge grain Cu film 11 is obtained and trench wiring 12 is obtained by shaping it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device in which copper (Cu) wiring and groove wiring are formed on a semiconductor substrate.

[0002]

2. Description of the Related Art LSI (large scale in)
Cu has attracted attention as an LSI wiring material for miniaturization and speedup of integration (large-scale integrated circuit). However, when Cu is used for an LSI wiring, it is difficult to form a wiring by dry etching. Therefore, a so-called damascene wiring is currently formed in which a wiring groove is formed in advance, Cu is embedded in the wiring groove, and Cu is left in the wiring groove portion. It is becoming mainstream. However, with the miniaturization of LSI, the wiring groove becomes narrower and narrower, and it becomes difficult to embed Cu in the wiring groove by sputtering.

Therefore, the electrolytic plating method is currently used. One example of this electrolytic plating method is Japanese Patent Laid-Open No. 63-1642.
No. 41 publication. This uses electrolytic plating to fill the contact holes with Cu. Note that another example of this type of device is disclosed in Japanese Patent Laid-Open No. 3-6819.
No. 0 and JP-A-3-263896.

[0004]

However, there is a problem that the Cu film formed by the electrolytic plating method has a small grain and the Cu groove wiring formed by using the Cu film has a weak electromigration resistance. Here, electromigration refers to a phenomenon in which atoms move during energization to partially thicken or thin the wiring. In order to improve the electromigration resistance, it is necessary to increase the grain size so that no grain boundary remains in the wiring.

On the other hand, by using the RF-DC coupled bias sputtering method, a DC bias of a certain value or more is applied to the substrate,
A film is formed by hitting the sputter growth surface with argon ions. At that time, a film in the (111) direction, which is the densest surface, is formed, the distance between Cu atoms is reduced, and stress energy is accumulated inside the film. Then, when heat treatment is performed, the stress energy is released, and the crystal orientation of the Cu film becomes Cu (11
There is a report that the thermal stability of Cu (200) is changed from 1) and a huge grain growth of several 100 μm or more occurs at the same time in the film. Electrochem. So
c. , Vol. 139. March 1992 pp.
922-927 "ElectricalProper"
ties of Giant-Grain Cope
r Thin Films Formed by a
Low Kinetic Energy Participation
le Process. (Hereinafter referred to as Document 1).

After forming a Cu film by ordinary sputtering, C is applied while applying a DC bias of a certain value or more to the substrate.
u is formed in two steps. After that, by performing heat treatment, stress energy is transferred from the layer formed while applying a DC bias to the layer formed by normal sputtering, and the crystal orientation change in the entire film is similar to that in the above-mentioned reference 1. And the report that grain growth occurs, Journal o
f Materials Chemistry and
Physics 99 (1995) pp. 1-10
"Formation of giant-grai
n computerinterconnects by
a low-energy ion bombardm
ent process for high-speed
d ULSIs. (Hereinafter referred to as Document 2).

As described above, when the film is formed by sputtering while irradiating with ions, it is possible to form a Cu film having a huge grain of several 100 μm. However, no matter which sputtering method is used, there is a disadvantage in filling the wiring groove as compared with the plating method. That is, no matter which sputtering method is used,
It is difficult to embed Cu in the wiring groove.

An object of the present invention is to provide a semiconductor device in which Cu can be embedded in the wiring groove and the grain is large.

[0009]

In order to solve the above problems, a semiconductor device according to the present invention comprises an insulating film having a wiring groove formed on a semiconductor substrate, and a barrier layer formed on the bottom and side surfaces of the wiring groove. And a copper wiring layer embedded in the wiring groove and having a larger grain than a copper film formed by an electroplating method.

According to the present invention, the heat treatment causes a change in crystal orientation and a huge grain growth in the second copper wiring layer,
At the same time, huge grain growth also occurs in the first copper wiring layer.
As a result, a single crystal conductive film wiring having no grain boundary in the wiring is formed, so that the resistance of the wiring can be reduced and the electromigration resistance can be improved.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 to 5 are sectional views showing the manufacturing process of the first embodiment, and FIGS. 10 to 14 are sectional views showing the manufacturing process of the second embodiment.

First, the first embodiment will be described. The first embodiment shows a case where Cu is embedded in the wiring groove. Referring to FIG. 1, the figure shows a silicon substrate 1.
A semiconductor element forming surface 2 is formed on the semiconductor element forming surface 2, an insulating film 3 is formed on the semiconductor element forming surface 2, and a stopper film 4 is formed on the insulating film 3.
Is formed, the interlayer insulating film 5 is formed on the stopper film 4, and the wiring groove 6 is formed in the interlayer insulating film 5.

Next, referring to FIG. 2, a barrier layer 7 represented by Ta, TaN (Ta; tantalum, N; nitrogen) is formed on the upper surface of the interlayer insulating film 5 and the bottom and side surfaces of the wiring groove 6. A Cu seed layer 8 is formed on the barrier layer 7, and an electrolytically plated Cu film 9 having a (111) orientation is formed on the Cu seed layer 8. This Cu seed layer 8 and electrolytic plating Cu
The total film thickness with the film 9 is t1. 2 to 5, the silicon substrate 1 and the semiconductor element formation surface 2 are omitted for convenience.

Next, referring to FIG. 3, an RF (high frequency) bias or a DC (direct current) bias is applied to the silicon substrate 1 to irradiate the sputter growth surface with argon ions while Cu (bias sputter) having a film thickness t2. A Cu layer) 10 is formed. The film thickness t2 is set to be larger than t1 (t2> t1).

Next, referring to FIG. 4, heat treatment is performed in an argon (Ar) or nitrogen atmosphere for crystal control. At this time, the crystal orientation changes to Cu (200),
Cu film 1 having a huge grain of several 100 μm at the same time
1 is formed. Next, with reference to FIG. 5, Cu groove wiring 12 is formed by removing Cu other than the wiring portion by mechanical chemical polishing (CMP).

The novel part of the first embodiment is that RF is applied to the silicon substrate 1 after the Cu9 film is formed by electrolytic plating (see FIG. 2) and before the crystal control heat treatment is performed (see FIG. 4). Alternatively, a DC bias is applied to form a Cu10 film having a film thickness equal to or larger than the plating film thickness while irradiating the sputter growth surface with argon ions (see FIG. 3).

Next, a second embodiment will be described. The second embodiment shows a case where Cu is embedded in the via hole. The through hole is a hole that penetrates the entire multilayer substrate, while the via hole is a hole formed between specific layers in the multilayer substrate. 10 to 14, the same components as those in FIGS. 1 to 5 are designated by the same reference numerals, and the description thereof will be omitted. 11 to FIG.
In FIG. 1, the description of the silicon substrate 1 and the semiconductor element formation surface 2 is omitted for convenience.

Referring to FIG. 10, a semiconductor element forming surface 2 is formed on a silicon substrate 1, an insulating film 3 is formed on the semiconductor element forming surface 2, and an interlayer insulating film 5 is formed on the insulating film 3. It shows up to where the via hole 21 is formed in the interlayer insulating film 5 and the first metal wiring 22 is formed on the bottom surface of the via hole 21. Next, referring to FIG. 11, a barrier layer 7 represented by Ta and TaN is formed on the upper surface of the interlayer insulating film 5 and the bottom and side surfaces of the wiring groove 6, and a Cu seed layer 8 is formed on the barrier layer 7. Thus, the electrolytically plated Cu film 9 having the (111) orientation is formed on the Cu seed layer 8. The total film thickness of the Cu seed layer 8 and the electrolytically plated Cu film 9 is t5.

Next, referring to FIG. 12, the silicon substrate 1
An RF (high frequency) bias or a DC (direct current) bias is applied to, and a Cu (bias sputtered Cu layer) 10 having a film thickness t6 is formed while irradiating the sputter growth surface with argon ions. The film thickness t6 is set to be larger than t5 (t6> t5). Next, referring to FIG. 13, heat treatment is performed in an argon (Ar) or nitrogen atmosphere for crystal control. At this time, the crystal orientation is Cu
Instead of (200), the Cu film 11 having a huge grain of several 100 μm is simultaneously formed. Next, referring to FIG. 14, the Cu film 11 is processed by dry etching to form C
The u wiring 23 is formed.

The new portion of the second embodiment is similar to that of the first embodiment in that Cu9 is formed by electrolytic plating (see FIG. 11) and then heat treatment for crystal control is performed (see FIG. 13). ), RF or DC bias is applied to the silicon substrate 1 to form Cu10 having a film thickness equal to or larger than the plating film thickness while irradiating the sputter growth surface with argon ions (see FIG. 12).

[0021]

EXAMPLES Next, examples will be described. First, the first
An example will be described. The first example is a first example corresponding to the first exemplary embodiment. For the description, FIGS. 1 to 5 used in the description of the first embodiment will be referred to. Furthermore, FIG.
5 and FIG. 15 and 16 are flowcharts showing the manufacturing process of the first embodiment.

First, as shown in FIG. 1, a silicon substrate 1
The semiconductor element forming surface 2 is formed on the upper surface (S1), the insulating film 3 is formed on the semiconductor element forming surface 2, the stopper film 4 is formed on the insulating film 3, and the interlayer insulating film 5 is formed on the stopper film 4. The wiring groove 6 is formed in the interlayer insulating film 5 (S2) (S3).

Next, as shown in FIG. 2, TaN (thickness: 15 nm as an example) 7 as a barrier metal was deposited on the upper surface of the interlayer insulating film 5 and the bottom and side surfaces of the wiring groove 6 by the sputtering method (S4). After that, as a seed layer before plating, for example, a Cu film 8 having a thickness of 100 nm is continuously formed by sputtering (S5). Next, a Cu film 9 having a thickness of 500 nm is formed by electrolytic plating (S6).
At this time, the crystal orientation of the Cu film of the seed layer 8 and the plating layer 9 was Cu (111). Next, as shown in FIG. 3, copper oxide on the surface of the plated Cu 9 is sputtered and reduced by Ar / H 2 plasma at room temperature in the cleaning chamber (S7).

Next, an RF or DC bias is applied to the silicon substrate 1 in the Cu sputtering chamber without exposing it to the atmosphere, and the growth surface is irradiated with argon ions to form a film by sputtering (S8). As a result, the bias sputtered Cu layer 10 is formed on the plated Cu 9. At this time, the ion energy (plasma potential, that is, self-bias) of argon was 80 eV. The film thickness (t2) was 700 nm thicker than the total film thickness (t1) of the electrolytically plated Cu 9 and the Cu seed layer 8. That is, t2
> T1. The silicon substrate 1 was set at -5 ° C in order to prevent a temperature rise due to plasma irradiation during film formation.

Next, as shown in FIG. 4, heat treatment was performed at a temperature of 400 ° C. for 30 minutes in an argon atmosphere. At this time, the crystal orientation changed from Cu (111) to Cu (200), and at the same time, the Cu film 11 having a huge grain of several 100 μm was successfully formed (S9). Next, as shown in FIG. 5, Cu other than the wiring portion was removed by mechanical chemical polishing (CMP) to form Cu groove wiring 12 (S1).
0). The electromigration withstand voltage of the groove wiring thus manufactured was one digit longer than that in the case of heat-treating ordinary Cu plating.

Next, the second embodiment will be described. Second
The example is a second example with respect to the first embodiment. For the explanation, FIGS. 6 to 9 and FIGS.
Refer to. 6 to 9 are sectional views showing the manufacturing process of the second embodiment, and FIGS. 15 to 17 are flowcharts showing the manufacturing process of the second embodiment. 6 to 9, the same components as those in FIGS. 1 to 5 are designated by the same reference numerals and the description thereof will be omitted. Further, in FIG. 6 to FIG. 9, for convenience, the description of the silicon substrate 1 and the semiconductor element formation surface 2 is omitted.

In the first embodiment, the case where the wiring groove is filled by using the electrolytic plating Cu9 has been described, but as described in this embodiment, instead of the electrolytic plating Cu9, the plasma CVD is used to form the Cu film. May be. in this case,
The seed layer 8 need not be formed by sputtering.

From the place where the semiconductor element forming surface 2 is formed on the silicon substrate 1 (S1), a TaN film is formed (S1).
4) Up to this point, the description is omitted because it is similar to the first embodiment. With reference to FIG. 6, after TaN7 is deposited as a barrier metal (S4), a 500 nm Cu film 31 is deposited on TaN7 by plasma CVD and embedded in the wiring trench 6 (S11). . Cu film 3 at this time
The crystal orientation of No. 1 was Cu (111).

As in the first embodiment, the copper oxide on the surface of the Cu film (plasma CVDCu) 31 is sputtered and reduced by Ar / H2 plasma at room temperature in the cleaning chamber as shown in FIG. 7 (S12). . Then, without exposing to the atmosphere, RF or DC bias is applied to the silicon substrate 1 in the Cu sputtering chamber, and the growth surface is irradiated with argon ions to form a film by sputtering (S).
8). As a result, the bias sputtered Cu layer 10 is formed on the plasma CVD Cu 31. At this time, the ion energy (plasma potential, that is, self-bias) of argon was 80 eV. Further, the film thickness (t4) is larger than the film thickness (t3) of the plasma CVD Cu31 70.
A 0 nm film was formed. That is, t4> t3.
The silicon substrate 1 was set at -5 ° C in order to prevent a temperature rise due to plasma irradiation during film formation.

Next, as shown in FIG. 8, heat treatment was performed at a temperature of 400 ° C. for 30 minutes in an argon atmosphere. At this time, the crystal orientation changed from Cu (111) to Cu (200), and at the same time, the Cu film 32 having a huge grain of several 100 μm was successfully formed (S9). Next, as shown in FIG. 9, Cu other than the wiring portion was removed by mechanical chemical polishing (CMP) to form a Cu groove wiring 33 (S1).
0). The electromigration withstand voltage of the groove wiring thus manufactured was one digit longer than that in the case of heat-treating ordinary Cu plating.

Next, a third embodiment will be described. Third
The example is an example corresponding to the second embodiment. For the description, refer to FIG. 10 to FIG. 14, FIG. 15, FIG. 16, FIG. 18, and FIG. 10 to 14 are sectional views showing the manufacturing process of the third embodiment, and FIGS. 15, 16, 18, and 19 are flowcharts showing the manufacturing process of the third embodiment.

In the first and second embodiments, the groove wiring Cu12,
Although the case of using 33 is shown, the present invention can be applied to the case of using wiring formed by normal dry etching. As shown in FIG. 10, first, the silicon substrate 1
A semiconductor element forming surface 2 is formed on the surface (S1), an insulating film 3 is formed on the semiconductor element forming surface 2, an interlayer insulating film 5 is formed on the insulating film 3 (S2), and a via hole is formed in the interlayer insulating film 5. 21 is formed (S21). Next, beer hole 2
The first metal wiring 22 is formed on the bottom surface of No. 1 (S22).
Then, similarly to the first and second embodiments, the barrier metal film (TaN) 7, the Cu seed film 8 and the Cu plating film 9 are sequentially formed.

First, as shown in FIG. 11, TaN (15 nm thick as an example) is deposited as a barrier metal on the upper surface of the interlayer insulating film 5 and the bottom and side surfaces of the wiring groove 6 by the sputtering method (S4). As a seed layer before plating, for example, a Cu film 8 having a thickness of 100 nm is continuously sputter-deposited (S5). Next, a Cu film 9 having a thickness of 500 nm is formed by electrolytic plating (S6).
At this time, the crystal orientation of the Cu film of the seed layer 8 and the plating layer 9 was Cu (111).

Then, as in the first and second embodiments, R
C while applying F or DC bias to the silicon substrate 1.
The u film 10 is formed. As shown in FIG. 12, the copper oxide on the surface of the plated Cu 9 is sputtered and reduced by Ar / H 2 plasma at room temperature in the cleaning chamber (S
7). Next, an RF bias is applied to the silicon substrate 1 in the Cu sputtering chamber without exposing it to the atmosphere, and sputtering growth is performed while irradiating the growth surface with argon ions (S8). As a result, the bias sputtered Cu layer 10 is formed on the plated Cu 9. At this time, the ion energy (plasma potential, that is, self-bias) of argon was 80 eV. The film thickness (t6) was 300 nm thicker than the total film thickness (t5) of the electrolytically plated Cu 9 and the Cu seed layer 8. That is, t6> t5. The silicon substrate 1 was set at -5 ° C in order to prevent a temperature rise due to plasma irradiation during film formation.

Next, as shown in FIG. 13, heat treatment was performed at a temperature of 400 ° C. for 30 minutes in an argon atmosphere. At this time, the crystal orientation changed from Cu (111) to Cu (200), and at the same time, the Cu film 11 having a huge grain of several 100 μm was successfully formed (S9). Next, as a reflection preventing film in the photolithography process, TiN having a thickness of 50 nm
A film 41 is formed on the Cu film 11 (S23), and then T
A plasma nitride film 42 is formed on the iN film 41 (S2
4).

After that, through a photolithography process,
After the plasma nitride film 42 is etched by a mixed gas containing C4F8, Ar and O2 (S25), the photoresist is ashed and removed by using O2 plasma and a resist stripping solution. Next, SiCl4, Ar, N2, NH
The Cu film 11 is dry-etched using 3 mixed gas, and the huge grain Cu wiring 23 is formed (S2).
6). Thus, the single crystal Cu wiring was successfully formed. The Cu wiring thus obtained was higher than the ordinary plated Cu wire by one digit in electromigration resistance.

That is, according to the present invention, the same phenomenon as the phenomenon described in Document 2 that the crystal orientation change and the giant grain growth occur in the bias sputter layer according to the present invention, and the giant grain growth also occurs in the electrolytic plating layer at the same time. Happens. In this way, a single crystal Cu wiring having no grain boundary can be formed in the wiring and the groove wiring, so that the resistance of the wiring can be reduced and the electromigration resistance can be improved.

Although TaN was used as the metal material of the barrier metal layer in this embodiment, Ta may be used instead of TiN.
It may be N, Mo, Nb, W, or a nitride of those materials. Further, plasma CVD is used as an interlayer film material for the groove wiring portion.
An oxide was used, but HSQ (Hydrogen Sil
sesquioxane) film, organic SOG, amorphous carbon materials, and fluorine additives of these materials.

[0039]

According to the semiconductor device of the present invention, an insulating film formed on a semiconductor substrate and having a wiring groove, a barrier layer formed on the bottom surface and side surfaces of the wiring groove, and an electric film embedded in the wiring groove. Since it includes a copper wiring layer having a larger grain than the copper film formed by the plating method, Cu is formed in the wiring groove.
Can be embedded and the grain can be increased.

Specifically, the heat treatment causes a change in crystal orientation and giant grain growth in the second copper wiring layer, and at the same time, giant grain growth also occurs in the first copper wiring layer. As a result, a single crystal conductive film wiring having no grain boundary in the wiring is formed, so that the resistance of the wiring can be reduced and the electromigration resistance can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment.

FIG. 2 is a cross-sectional view showing a manufacturing process of the first embodiment.

FIG. 3 is a cross-sectional view showing a manufacturing process of the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 12 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 14 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 15 is a flowchart showing a manufacturing process of the first embodiment.

FIG. 16 is a flowchart showing a manufacturing process of the first embodiment.

FIG. 17 is a flowchart showing a manufacturing process of the second embodiment.

FIG. 18 is a flowchart showing a manufacturing process of the third embodiment.

FIG. 19 is a flowchart showing a manufacturing process of the third embodiment.

[Explanation of symbols]

1 Silicon substrate 2 Semiconductor element formation surface 3 insulating film 4 Stopper film 5 Interlayer insulation film 6 wiring groove 7 TaN 8, 9, 10, 31 Cu film 11,32 Giant grain Cu film 12,33 groove wiring 21 beer hall 22 First metal wiring 23 Cu wiring

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH11 HH17 HH19 HH20 HH21                       HH32 HH33 JJ01 JJ11 JJ17                       JJ19 JJ20 JJ21 JJ32 JJ33                       KK07 LL06 LL08 MM01 MM05                       MM08 MM12 MM13 NN03 NN06                       NN07 PP12 PP15 PP17 PP27                       PP33 QQ03 QQ08 QQ11 QQ25                       QQ28 QQ30 QQ37 QQ48 QQ73                       QQ94 RR01 RR06 RR11 RR24                       RR25 SS15 XX01 XX05 XX10

Claims (6)

[Claims] 1. An insulating film having a wiring groove formed on a semiconductor substrate, a barrier layer formed on a bottom surface and a side surface of the wiring groove, and a copper film embedded in the wiring groove and formed by an electroplating method. And a copper wiring layer having a larger grain than the above. 2. An insulating film having a wiring groove formed on a semiconductor substrate, a barrier layer formed on a bottom surface and a side surface of the wiring groove, and a crystal orientation Cu (20) embedded in the wiring groove.
0) The copper wiring layer which is 0), The semiconductor device characterized by the above-mentioned. 3. A step of forming a first copper wiring layer on the insulating film so as to fill the wiring trench with the copper wiring layer, and a bias is applied to the semiconductor substrate after this step. A step of forming a second copper wiring layer on the first copper wiring layer by sputtering while irradiating the film-forming surface with argon ions; and, following this step, heat treatment for crystal control in an argon or nitrogen atmosphere The semiconductor device according to claim 1, wherein the semiconductor device is produced through steps. 4. The semiconductor device according to claim 3, wherein the first copper wiring layer comprises a copper seed layer and a copper layer formed by electrolytic plating. 5. The semiconductor device according to claim 3, wherein the first copper wiring layer is a copper layer formed by plasma CVD. 6. The semiconductor device according to claim 1, wherein a metal wiring is formed on a bottom surface of the wiring groove of the insulating film.