JP2003109380A - Storage device, storage method, and storage device access method - Google Patents

Abstract

(57) [Summary] A storage device, a storage method, and a storage device capable of realizing simultaneous access to a planar area without requiring a plurality of accesses or a temporary memory. Provide access methods. A fixed area including data of 8 × 8 size is one.
The memory block group 11 in which the data of the six data groups is stored is independent of the row decoder 1102,
A first memory block 110, a second memory block 111, a third memory block 112, and a fourth memory block 113 including 112, 1122, and 1132;
Each of the memory blocks 110 to 113 has four word lines WL00 to 03, WL10 to 13, WL20 to which memory cells MC storing 64 data in the fixed area are connected.
, And WL30 to 33, and 64 data in one fixed area are stored in the memory cell MC connected to the same word line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, a storage method, and a storage device access method for storing image data for which data needs to be read out in a planar form instead of a single point or line form.

[0002]

2. Description of the Related Art A memory device typified by a DRAM is usually configured to access stored data point by point. However, due to its structure, line-by-line access can be easily realized, and high-speed page mode, serial access, etc. are realized by utilizing this property.

FIG. 16 is a block diagram showing a basic configuration example of a storage device (memory device). The memory device 1 is
As shown in FIG. 16, it has a memory cell array 2, a row decoder 3, a column decoder 4, and a sense amplifier 5.

In the memory cell array 2, the word lines WL connected to the row decoder 3 and the column lines (bit lines) BL connected to the column decoder 4 via the sense amplifier 5 are arranged at the intersections of these words. A memory cell MC holding data connected to the line and the bit line is arranged. Here, for the sake of explanation, the memory cells MC (1, A) to MC
(9, O) are arranged in a matrix of 9 × 15, and have 9 word lines (WL1 to WL9) and 15 bit lines (BLA).
˜BLO). Now, FIG.
When trying to access the cell MC (2, G) indicated by the black circle, the actual operation is as follows.

In the memory device 1, the row decoder 2 receives the row address RADR of "2" and the column decoder 4 receives the column address CADR of "G". Row address R
The ARD is interpreted by the column decoder 2, the second word line WL2 is selected, and 15 memory cells MC (2,1) to MC (2, connected to this word line WL2 are selected.
O) is activated and data is read. The read data is propagated through 15 bit lines BLA to BLO, is input to the sense amplifier 5, and is determined as data.

On the other hand, the column address CARD is interpreted by the row decoder 4, and the data corresponding to "G" is selected from the above 15 data and output. In this way, the black circled memory cells MC (2, G) in the figure are selected and output.

Attention should be paid to the column address CAD.
Until it is selected according to R, all 15 data corresponding to the row address “2” are amplified and determined by the sense amplifier 5, and this property is utilized to sequentially access the column address in serial. Access is a fast page mode in which random access is performed. Also, if necessary, it is possible in principle to output the 15 data at the same time.

Usually, in a memory device for handling an image, one line forming a screen is made to correspond to the above-mentioned row address.
That is, a memory device that handles images stores data as if the images were drawn on the memory.

[0009]

However, in applications such as image processing, it is often necessary to read data in a plane rather than a single point or line.
In such a case, in the memory device as described above,
The line data can be easily retrieved, but to read a planar area that spans multiple lines, while accumulating the read line data in a temporary memory, It was necessary to access the data multiple times and prepare the necessary data before processing. This not only increases the processing time but also physically increases the circuit scale by installing a temporary memory. This problem will be discussed in more detail by taking motion vector evaluation using a variable search range as an example.

In motion picture processing, motion-compensated inter-frame prediction is a basic compression method.
It is necessary to find the "motion vector". Among the motion vector calculation methods, the full search block matching method (Ful
l Search Block Matching M
method) is the most common method. In this method, as shown in FIG. 17, one screen of a moving image is (N × N)
It is divided into blocks consisting of pixels, and the previous frame image in the range shifted from the same coordinates by p pixels in both vertical and horizontal directions with respect to each reference block REFBLK (X) of the current screen is set as the search range SRCRGN, The motion vector v is determined by comparing with all the candidate blocks (Y). This comparison operation is performed by the following method.

Now let x be a pixel in the reference block.
_{Let i, j be} a pixel in the candidate block as y _{i, j} .
If p is the maximum search range in the vertical / horizontal direction and variables m and n are the positions of the candidate blocks in the search range, the sum of absolute differences D shown by the following equation is the minimum. The position (m, n) of such a candidate block means the motion vector v.

[0012]

[Equation 1]

[0013]

[Equation 2]

The full-search block matching method has high accuracy among the methods for obtaining motion vectors and is a general method, but has a drawback that the scale of calculation becomes extremely large. This is because in the actual calculation, it is necessary to perform (2p) ² times of comparison calculation for each pixel in the frame. For example, 1 frame is 72
Taking a standard television (hereinafter referred to as Standard TV) consisting of 0 × 576 pixels as an example, in the case of p = 8 and N = 16, 100 million is completed by the processing of one frame. The difference calculation needs to be performed more than once, and the calculation for summing the differences is required the same number of times. Of course, if the value of the search range p increases,
The number of calculations increases in proportion to the square.

On the other hand, in the actual motion vector evaluation, the search range means the maximum motion that can be evaluated. That is, it is theoretically impossible to evaluate a motion having a size larger than the search range. Therefore, in order to evaluate a large motion (fast motion), it is necessary to obtain a motion vector using a large search range, and it becomes necessary to perform a huge amount of calculation. For the same reason, when evaluating a small motion (slow motion), a very small search range is sufficient, and even if a large search range is evaluated, most of the calculation is useless.

From the above discussion, it can be seen that it is necessary to select an appropriate search range according to the motion in order to perform the motion vector calculation without waste. In the conventional method of storing one line forming the screen at the row address of the memory, the read operation for the search range is performed as follows.
For example, as shown in FIG. 18A, when there are a search range A for 5 lines and a search range B for 7 lines, first, access to the search range A is performed as shown in FIG. 18B. Five lines are extracted by five times of memory access, and necessary portions are extracted as shown in FIG. Then, when the search range is changed from A to B, the number of row addresses to be read is changed in order to access the search range B, and as shown in FIG. A line is extracted, and a necessary portion is extracted as shown in FIG.

As described above, according to the conventional method of storing one line forming a screen at the row address of the memory, in order to read out the search range, one row is first added to the necessary number of row addresses. It is necessary to access one pixel, extract a necessary pixel, and repeat the operation of calculating the sum of absolute differences between the extracted pixel values. Then, in order to change the search range, the number of row addresses to be read must be changed, and as a result, the number of accesses changes depending on the frame to be processed, and the operation of the memory becomes extremely complicated.

The present invention has been made in view of the above circumstances, and an object thereof is to realize simultaneous access to a planar area without requiring a plurality of accesses or a temporary memory. A storage device, a storage method, and an access method of the storage device are provided.

[0019]

In order to achieve the above object, a first aspect of the present invention is to divide a unit rectangular area containing a plurality of data into a predetermined number of rectangular areas that are continuously adjacent to each other. A storage device for storing data of a desired area from a data group arranged in a matrix that can be divided into a plurality of data blocks as one associated data block area, and a unit included in at least the data block that can be divided. The memory block has a plurality of memory blocks corresponding to a predetermined number of rectangular areas, and each of the memory blocks has a plurality of memory cells, the number of rows corresponding to the number of the data block areas, and the data in the unit rectangular area. The number of rows in the memory array section for activating the memory array section arranged in a matrix with the number of columns corresponding to the number and a plurality of memory cells arranged in the same row. A plurality of row lines of a corresponding number and a plurality of columns of a number corresponding to the number of data in the unit rectangular area for exchanging data with the activated memory cells in a plurality of memory cells arranged in the same column Line, and a row decoder that activates one of the plurality of row lines in response to a selection signal.

According to a first aspect, a plurality of data in each unit rectangular area included in the one data block area are connected to a predetermined one row line of a memory block different for each unit rectangular area. Stored in the memory cell.

According to the first aspect, the data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), the plurality of memories are Each block is associated with a value of x, a number corresponding to the value of y is given to each of the plurality of row lines of each of the memory blocks, and a plurality of data of each of the unit rectangular areas has a value of the value of x. Are stored in a plurality of memory cells connected to the row line of the number corresponding to the above-mentioned value of y in the memory block corresponding to the above.

In the first aspect, the selection signal is
The value of y is specified in the row decoder.

In the first aspect, the two-dimensionally arranged data group is moving image data.

According to a second aspect of the present invention, a unit rectangular area containing a plurality of data can be divided, and a predetermined number of continuously adjoining rectangular areas are divided into a plurality of associated data block areas. A storage device for storing data in a desired area from a data group arranged in a matrix to obtain a plurality of memories corresponding to at least a predetermined number of unit rectangular areas included in the data block that can be divided. Each of the memory blocks has a plurality of memory cells arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area. A memory array section,
A plurality of row lines corresponding to the number of rows of the memory array section for activating a plurality of memory cells arranged in the same row and a plurality of memory cells arranged in the same column are activated. A plurality of column lines corresponding to the number of data in the unit rectangular area for exchanging data with the memory cells and one row line among the plurality of row lines in response to the first selection signal are activated. A plurality of data in each unit rectangular area included in the one data block area,
Each of the unit rectangular areas is stored in a plurality of memory cells connected to a predetermined one row line of a different memory block, and further, a plurality of the first selection signals are generated based on access area information, and corresponding An access area determination circuit for outputting to a row decoder of the memory block, an output selector for selecting and outputting data read to a plurality of column lines of the plurality of memory blocks according to a second selection signal, and the access And a select data determination circuit that generates a signal indicating selection target data to be selected and output based on the area information and outputs the signal as the second selection signal to the output selector.

According to a second aspect, the unit rectangular area is divided into a plurality of internal blocks, and the select data determination circuit generates a signal indicating an internal block to be selected based on access area information, It outputs to the output selector as a second selection signal, and the output selector has a plurality of internal block selectors corresponding to each memory block, selects an internal block according to the second selection signal, and outputs desired data. Output.

According to a second aspect, the data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), the plurality of memories are Each block is associated with a value of x, a number corresponding to the value of y is given to each of the plurality of row lines of each of the memory blocks, and a plurality of data of each of the unit rectangular areas has a value of the value of x. Are stored in a plurality of memory cells connected to the row line of the number corresponding to the above-mentioned value of y in the memory block corresponding to the above.

Further, according to a second aspect, the access area judgment circuit specifies the value of y to each row decoder by the first selection signal.

In the second aspect, the data group arranged in the two-dimensional form is moving image data.

A third aspect of the present invention is that it can be divided into unit rectangular areas containing a plurality of data, and a predetermined number of continuously adjoining rectangular areas are divided into a plurality of associated data block areas. A storage method for storing data in a desired area from a data group arranged in a matrix in at least a plurality of memory blocks corresponding to a predetermined number of unit rectangular areas included in the data block that can be partitioned. In each of the memory blocks, a plurality of memory cells are arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area. Data in each unit rectangular area included in the data block area of
The data is stored in a plurality of memory cells arranged in a predetermined one row of different memory blocks for each unit rectangular area.

In the third aspect, the data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y),
Each of the plurality of memory blocks is associated with a value of x, each of the plurality of rows of each of the memory blocks is given a number corresponding to the value of y, and the plurality of data of each unit rectangular area are The data is stored in a plurality of memory cells arranged in the row of the number corresponding to the value of y in the memory block associated according to the value of x.

In the third aspect, the data group arranged in the two-dimensional form is moving image data.

According to a fourth aspect of the present invention, a unit rectangular area containing a plurality of data can be divided, and a predetermined number of continuously adjoining rectangular areas are divided into a plurality of associated data block areas. A storage device for storing data in a desired area from a data group arranged in a matrix to obtain a plurality of memories corresponding to at least a predetermined number of unit rectangular areas included in the data block that can be divided. Each of the memory blocks has a plurality of memory cells arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area. A memory array section,
A plurality of row lines corresponding to the number of rows of the memory array section for activating a plurality of memory cells arranged in the same row and a plurality of memory cells arranged in the same column are activated. A plurality of column lines corresponding to the number of data in the unit rectangular area for exchanging data with the memory cells and one row line among the plurality of row lines in response to the first selection signal are activated. A plurality of data in each unit rectangular area included in the one data block area,
A method of accessing a storage device stored in a plurality of memory cells connected to a predetermined one row line of a different memory block for each unit rectangular area, wherein a plurality of the first plurality of memory cells are accessed based on access area information. A selection signal is generated and supplied to a row decoder of a corresponding memory block, a signal indicating selection target data to be selected and output based on the access area information is generated as a second selection signal, and the plurality of memories are selected. The data read out to the plurality of column lines of the block
The selected signal is output according to the selection signal of.

According to a fourth aspect, the unit rectangular area is divided into a plurality of internal blocks, and a signal indicating an internal block to be selected is generated as the second selection signal based on access area information, and the second selection signal is generated. The internal block is selected according to the selection signal 2 and the desired data is output.

According to a fourth aspect, the data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), the plurality of memories are Each block is associated with a value of x, a number corresponding to the value of y is assigned to each of the rows of each of the memory blocks, and a plurality of data of each unit rectangular area is assigned to the value of x. The data is stored in the plurality of memory cells arranged in the row of the number corresponding to the value of y in the corresponding memory block.

Further, in a fourth aspect, the value of y is designated to each row decoder by the first selection signal.

According to the fourth aspect, the data group arranged in the two-dimensional form is moving image data.

According to the present invention, for example, the data block areas are arranged in a matrix, and when addressing the unit rectangular area of each data block in the form of (x, y),
Each of the plurality of memory blocks is associated with the value of x, and each of the plurality of row lines of each memory block is given a number corresponding to the value of y. Then, the plurality of data of each unit rectangular area are stored in the plurality of memory cells connected to the row line of the number corresponding to the value of y of the memory block corresponding to the value of x. The access area information input to such a storage device is supplied to the access area determination circuit and the select data determination circuit. In the access area determination circuit, read area determination is performed based on the access area information, and a first selection signal for selecting an independent row line is generated for each memory block based on the row determination result. Is output to the row decoder of. Further, in the select data determination circuit, column determination is performed from the supplied access area information, and a second selection signal for selecting the selection target data (column) corresponding to the address is output to the generated output selector.

The row decoder of each memory block receiving the first selection signal accesses the corresponding row in each memory block. That is, the corresponding row line of each memory block is activated. As a result, a plurality of memory cells and data corresponding to the number of data in the unit rectangular area connected to each row line of each memory block are read out to a plurality of column lines corresponding to the number of data in the unit rectangular area. And output to the output selector. In the output selector,
For example, a plurality of read data are sent to the sense amplifier, and the data is amplified and confirmed. Then, as described above, the select data determination circuit previously sends the selection target data as the second selection signal to the output selector, and the output is selected in accordance with the selection target data. As described above, access to the planar area is realized.

As described above, according to the present invention, it is possible to read a predetermined minimum unit rectangular area from a given position from a given two-dimensionally arranged data group. Further, by increasing the number of unit rectangular areas included in the data block area, the area n ² (n = 1, 2, 3, ...) Of the unit rectangular area at any position can be read from any position. You can Further, by further increasing the number of unit rectangular areas included in the data block area, surface access to an arbitrary shape can be realized.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a first embodiment of a memory device (storage device) according to the present invention. This memory device 1
0 is a square area having a predetermined size as a surface access to an arbitrary location, and has a configuration capable of realizing simultaneous access to the planar area under the condition of an arbitrary location. Hereinafter, the configuration and function of the memory device 10 will be sequentially described with reference to the drawings.

The memory device 10 is, as shown in FIG.
Memory block group 11, access area input circuit 12, access area determination circuit 13, select data determination circuit 1
4 and an output selector 15.

The memory block group 11 includes a plurality (four in this embodiment) of first memory blocks 110 (BLK0), second memory blocks 111 (BLK1), and third memory blocks 112 each having an independent row decoder.
(BLK2) and the fourth memory block 113 (BL
K3) is arranged in parallel with the output selector 15.

The first memory block 110 includes a memory array section 1101 in which memory cells MC are arranged in a 4 × 64 matrix, a row decoder 1102, and a row decoder 1.
Four word lines WL00 to WL03 connected to 102
Is connected to the output selector 15 and is connected to the memory array unit 11
01 bit lines BL00 to B arranged so as to intersect the word lines WL00 to WL03 at right angles.
It has L063. Each memory cell MC is formed of, for example, a DRAM including an n-channel MOS (NMOS) transistor and a capacitor, and has a word line WL00.
˜WL03 and bit lines BL00 to BL063, the gates of the NMOS transistors are connected to the corresponding word lines, and the storage nodes are connected to the corresponding bit lines via the NMOS transistors.

The second memory block 111 includes a memory array section 1111 in which memory cells MC are arranged in a 4 × 64 matrix, a row decoder 1112, and a row decoder 1.
Four word lines WL10 to WL13 connected to 112
Is connected to the output selector 15 and is connected to the memory array unit 11
In FIG. 11, 64 bit lines BL10 to B arranged so as to intersect the word lines WL10 to WL13 at right angles.
It has L163. Each memory cell MC is composed of, for example, a DRAM including an NMOS transistor and a capacitor, and is arranged at the intersections of the word lines WL10 to WL13 and the bit lines BL10 to BL163 to form an NMOS.
The gate of the transistor is connected to the corresponding word line,
The storage node is connected to the corresponding bit line via the NMOS transistor.

The third memory block 112 includes a memory array section 1121 in which memory cells MC are arranged in a 4 × 64 matrix, a row decoder 1122, and a row decoder 1.
Four word lines WL20 to WL23 connected to 122
Is connected to the output selector 15 and is connected to the memory array unit 11
In FIG. 21, 64 bit lines BL20 to BL arranged so as to intersect the word lines WL20 to WL23 at right angles.
It has L263. Each memory cell MC is composed of, for example, a DRAM including an NMOS transistor and a capacitor, and is arranged at the intersection of the word lines WL20 to WL23 and the bit lines BL20 to BL263, and the NMOS
The gate of the transistor is connected to the corresponding word line,
The storage node is connected to the corresponding bit line via the NMOS transistor.

The fourth memory block 113 includes a memory array section 1131 in which memory cells MC are arranged in a 4 × 64 matrix, a row decoder 1132, and a row decoder 1.
Four word lines WL30 to WL33 connected to 132
Is connected to the output selector 15 and is connected to the memory array unit 11
In FIG. 31, 64 bit lines BL30 to B arranged so as to intersect the word lines WL30 to WL33 at right angles.
It has L363. Each memory cell MC is composed of, for example, a DRAM including an NMOS transistor and a capacitor, and is arranged at the intersection of the word lines WL30 to WL33 and the bit lines BL30 to BL363.
The gate of the transistor is connected to the corresponding word line,
The storage node is connected to the corresponding bit line via the NMOS transistor.

Next, these memory blocks 110-1
The data stored in and read from the storage device 13 will be described with reference to FIG.

Here, for simplification, description will be made using a virtual memory having 16 fixed areas of 8 × 8 size.

This virtual memory MRY1 is a unit rectangular area (hereinafter, fixed area) FXRGN containing a plurality of data.
And a predetermined number of continuously adjoining rectangular areas can be divided into a plurality of data block areas DTBLK which are associated with each other.

One fixed area FXRGN includes 64 pieces of data (data 0 to 63), and the 64 pieces of data are connected to the same word line (row line) of each memory block 110 to 113. It is stored (arranged) in the MC. Correspondingly, in the memory device 10 according to the first embodiment shown in FIG. 1, the 16 word lines WL to which the memory cells MC storing 64 pieces of data in the fixed area are connected.
00-03, WL10-13, WL20-23, WL3
It has a memory block group 11 composed of 0 to 33.

Then, 64 pieces of data of each fixed area FXRGN are divided and arranged by the following method. That is,
When the fixed area FXRGN is specified in the form of (x, y) as shown in FIG. 2, the area where x is 0 is the memory block 110.
Then, the region where x is 1 is arranged in the memory block 111, the region where x is 2 is arranged in the memory block 112, the region where x is 3 is arranged in the memory block 113, and so on. Specifically, the data in the areas A, B, and C in FIG. 2 are divided and arranged as follows.

The 64 pieces of data in the fixed area (0, 0) in the area A are the word lines WL00 of the first memory block 110.
Are stored in the 64 memory cells MC connected to. A
The 64 pieces of data in the fixed area (1, 0) of the area are connected to the word line WL10 of the second memory block 111.
It is stored in the four memory cells MC. The 64 pieces of data in the fixed area (2, 0) of the area A are stored in the third memory block 1
It is stored in 64 memory cells MC connected to 12 word lines WL20. 6 of fixed area (3,0) of area A
The four pieces of data are stored in the 64 memory cells MC connected to the word line WL30 of the fourth memory block 113.

The 64 pieces of data in the fixed area (0, 2) of the area B are the word lines WL02 of the first memory block 110.
Are stored in the 64 memory cells MC connected to. B
The 64 pieces of data in the fixed area (1, 2) of the area are connected to the word line WL12 of the second memory block 111.
It is stored in the four memory cells MC. The 64 pieces of data in the fixed area (2, 0) of the B area are stored in the third memory block 1
It is stored in 64 memory cells MC connected to 12 word lines WL20. 6 of fixed area (3,0) of area B
The four pieces of data are stored in the 64 memory cells MC connected to the word line WL30 of the fourth memory block 113.

The 64 pieces of data in the fixed area (0, 3) of the area C is the word line WL03 of the first memory block 110.
Are stored in the 64 memory cells MC connected to. C
The 64 pieces of data in the fixed area (1, 3) of the area are connected to the word line WL13 of the second memory block 111.
It is stored in the four memory cells MC. The 64 pieces of data in the fixed area (2, 3) of the area C is stored in the third memory block 1
It is stored in 64 memory cells MC connected to 12 word lines WL23. 6 of fixed area (3, 3) of area C
The four pieces of data are stored in the 64 memory cells MC connected to the word line WL33 of the fourth memory block 113.

Each of the memory blocks 110 to 113 according to the first embodiment has the independent row decoders 1102, 1112, 1122 and 1132 as described above, and the selection signals S130 to S130 of the access area determination circuit 13.
By 133, an independent word line (row line) can be selected for each block. That is, of the (x, y) that specifies the area, y can be accessed in any combination. By implementing a memory having such a structure, a fixed-size square area (8 × in this example) at an arbitrary position is realized.
8 sizes) can be accessed.

FIG. 3 is a diagram for explaining an access mode for data stored in each memory block. Although FIG. 3 is written on the assumption that the area C will be accessed, the same method can be used to access other locations.

For example, when it is desired to access the area A shown in FIG. 3, four first to fourth memory blocks 110 to 1 are used.
From 13, (0,0) (1,0) (2,0) (3,0)
It is only necessary to read the data of the four fixed areas, select only the portion corresponding to the area A, and output it.

Specifically, the row decoder 1102 of the first memory block 110 selects the word line WL00 to activate the memory cells, and the bit lines BL00 to BL063.
64 pieces of data in the fixed area (0, 0) are read out and output to the column decoder 151 of the output selector 15. Similarly, the row decoder 1112 of the second memory block 111 selects the word line WL10 to activate the memory cells, and the bit lines BL10 to BL163 have fixed areas (1,
64 data of 0) are read out and output to the column decoder 152 of the output selector 15. Third memory block 11
The word line WL20 is selected by the second row decoder 1122 to activate the memory cells, and the bit lines BL20 to BL2 are activated.
64 pieces of data in the fixed area (2, 0) are read out to 63 and output to the column decoder 153 of the output selector 15.
The word line WL30 is selected by the row decoder 1132 of the fourth memory block 113 to activate the memory cells, and the bit lines BL30 to BL363 are fixed to the fixed area (3, 0) of 6 (6).
The four pieces of data are read and output to the column decoder 154 of the output selector 15.

When it is desired to access the B area, the row decoder 1102 of the first memory block 110 selects the word line WL02 to activate the memory cell, and the bit lines BL00 to BL063 have a fixed area (0, 2) of 64. Column decoder 15 of the output selector 15
Output to 1. Similarly, the row decoder 1112 of the second memory block 111 selects the word line WL12 to activate the memory cell, read 64 pieces of data in the fixed area (1, 2) to the bit lines BL10 to BL163, and output the selector 15 Output to the column decoder 152. The word line WL20 is selected by the row decoder 1122 of the third memory block 112 to activate the memory cell, and the bit line B20
The column decoder 153 of the output selector 15 reads 64 pieces of data in the fixed area (2, 0) in L20 to BL263.
Output to. Row decoder 1 of fourth memory block 113
The word line WL30 is selected by 132 to activate the memory cell, 64 pieces of data in the fixed area (3, 0) are read to the bit lines BL30 to BL363, and output to the column decoder 154 of the output selector 15.

When it is desired to access the area C, the row decoder 1102 of the first memory block 110 selects the word line WL03 to activate the memory cell, and the bit lines BL00 to BL063 have the fixed area (0, 3) of 64. Column decoder 15 of the output selector 15
Output to 1. Similarly, the row decoder 1112 of the second memory block 111 selects the word line WL13 to activate the memory cell, reads 64 pieces of data in the fixed area (1, 3) to the bit lines BL10 to BL163, and outputs the data to the output selector 15 Output to the column decoder 152. The word line WL23 is selected by the row decoder 1122 of the third memory block 112 to activate the memory cell, and the bit line B23
The column decoder 153 of the output selector 15 reads 64 pieces of data in the fixed area (2, 3) in L20 to BL263.
Output to. Row decoder 1 of fourth memory block 113
The word line WL33 is selected by 132 to activate the memory cell, and 64 pieces of data in the fixed region (3, 3) are read to the bit lines BL30 to BL363 and output to the column decoder 154 of the output selector 15.

The access area input circuit 12 inputs information on an area (read area) to be accessed to each of the memory blocks 110 to 113 of the memory block group 11,
It is supplied to the access area determination circuit 13 and the select data determination circuit 14.

FIG. 4 is a diagram for explaining the configurations and functions of access area determination circuit 13, select data determination circuit 14, and output selector 15. Note that in FIG. 4, each memory block 110 is illustrated for simplification of the drawing.
-113 memory array units 1101, 1111 and 112
1, 1131 are shown as a 4 × 4 matrix.

The access area determination circuit 13 determines a read area from the access area information supplied from the access area input circuit 12, specifically, a row determination unit 131 performs row determination as shown in FIG. A row block determination circuit 132 performs a row block determination based on the determination result, and a first selection signal S13 for selecting an independent word line (row line) for each of the memory blocks 110 to 113.
0 to S133 are output to the row decoders 1102, 1112, 1122, 1132 of each memory block 110-113.

As shown in FIG. 3, the select data determination circuit 14 performs column determination by the column determination unit 141 from the access area information supplied from the access area input circuit 12, and corresponds to each of the memories 110 to 113. A second selection signal S14 for selecting the column decoder provided and the column corresponding to the address (selection target data) is output to the output selector 15.

Output selector 15 has sense amplifier 150 and column decoders 151-154 provided corresponding to memory blocks 110-113, as shown in FIGS. ~ 11
3, bits BL00 to BL063, BL10
BL163, BL20 to BL263, BL30 to BL3
The data read out by 63 is amplified and confirmed by the sense amplifier 150, and the column decoders 151 to 154 are selected according to the selection signal S14 by the selection data judgment circuit 14 to select and output 64 data at a time.

Next, the operation of the above configuration will be described with reference to FIG. Note that, although FIG. 3 is written on the assumption that the area C is accessed as described above, the same method can be used to access another location.

First, the access area information input to the memory device 10 is input to the access area input circuit 12 and supplied to the access area determination circuit 13 and the select data determination circuit 14. In the access area determination circuit 13, read area determination is performed from the access area information supplied from the access area input circuit 12, and an independent word line (row line) is provided for each of the memory blocks 110 to 113 based on the row determination result. Selection signal S130 for selecting
To S133 are generated, and each memory block 110 to 11 is generated.
3 row decoders 1102, 1112, 1122, 113
2 is output. In addition, the select data determination circuit 14 performs column determination from the access area information supplied from the access area input circuit 12, and each of the memories 110 to 11 is determined.
And a second selection signal S for selecting a column decoder provided corresponding to 3 and selection target data (column) corresponding to the address.
14 is output to the generated output selector 15.

The row decoder 110 of each of the memory blocks 110 to 113 receiving the first selection signals S130 to S133.
2, 1112, 1122, and 1132, the corresponding rows in 110 to 113 in each memory block are accessed. In the example of FIG. 3, the C area is input as the access area, and the row decoders 1102, 1112, 1122, 1132 of the memory blocks 110 to 113 are marked with "
3 ”is transmitted. That is, here, the word line WL03 of the memory block 110 and the memory block 111 are transmitted.
The word line WL13, the word line WL23 of the memory block 112, and the word line WL33 of the memory block 113 are activated. Thereby, the word line WL03
The data of the 64 memory cells MC connected to the bit lines BL00 to 063 are read to the bit lines BL00 to 063, and the data of the 64 memory cells MC connected to the word line WL13 are read to the bit lines BL10 to 163. The data of the 64 memory cells MC connected to the line WL23 is the bit line B.
The data of the 64 memory cells MC read to L20 to 263 and connected to the word line WL33 is the bit line BL.
30 to 363. Bit lines BL00 to 06
3, BL10-163, BL20-263, and BL
The 64 × 4 = 256 data read out from 30 to 363 are sent to the sense amplifier 150 of the output selector 15, and the data is amplified and confirmed.

FIG. 3 shows this state as a data arrangement on the screen. In the figure, labels such as (0,3) and (1,3) correspond to the row lines in the fixed area, that is, the memory block. , Small squares labeled 0 to 63 in the respective fixed areas correspond to the respective data. The output data is sent to the column decoders 151 to 154 provided corresponding to each block. Each column decoder 15
Data to be selected, which has been determined from the access area information by the select data determination circuit 14, has been sent to 1 to 154 in advance, and the output is selected accordingly. That is, from the fixed area (0, 3) through the column decoder 151, each data of 46, 47, 54, 55, 62, 63, and from (1, 3) through the column decoder 152, 40 to 40.
Each data of 45, 48-53, 56-61, (2, 3)
From the column decoder 153 to 6,7,14,15,
Each data of 22, 23, 30, 31, 38, 39,
From (3,3) through the column decoder 154, 0-5,8
.., 13, 16 to 21, 24 to 29, and 32 to 37 are selected and output. As described above, 8 × 8 =
Access to 64 planar areas is realized.

As described above, according to the first embodiment, a memory block in which data of a given data group in which 16 fixed areas including 64 data of 8 × 8 size exist is stored. Group 11 and memory block group 11
Are independent row decoders 1102, 1112,
First memory block 11 with 1122, 1132
0, second memory block 111, third memory block 1
12 and a fourth memory block 113, and each of the memory blocks 110 to 113 has four word lines WL00 to 03 and WL10 to 13 connected to a memory cell MC in which 64 pieces of data in a fixed area are stored. , WL20-2
Each of the data has three WLs 30 to 33, and 64 pieces of data in one fixed area are stored (arranged) in the memory cells MC connected to the same word line, and the fixed area is designated in the form of (x, y). If x is 0, the area where x is 0 is
In order to access, the area where x is 1 is located in the memory block 111, the area where x is 2 is located in the memory block 112, the area where x is 3 is located in the memory block 113, and so on. Since y (0 to 3) corresponding to the address is specified and the selection of the word line is switched so that data can be extracted at any position, it requires multiple accesses and temporary memory. However, there is an advantage that it is possible to realize simultaneous access to the planar area.

In the above description, as the access to the memory block group 11, the read operation has been described on the assumption that the data is already arranged (stored) according to the predetermined condition, but the write operation is performed according to the predetermined condition. It goes without saying that it can be done.

Second Embodiment FIG. 5 is a diagram for explaining a second embodiment of a memory device (storage device) according to the present invention.

The difference between the second embodiment and the first embodiment described above is that the planar access is realized by a slightly different method, and hierarchical access is enabled.
In the second embodiment, the data in each fixed area is divided into four internal blocks (0 to 15). Internal block selectors 155 to 158 are arranged at the input stages of the column decoders 151 to 154. In the second embodiment, the internal block selectors 155-15
8, the selection target internal block determined from the access area information by the select data determination circuit 14 (not shown) is sent, and the internal block is selected accordingly. Other configurations are similar to those of the above-described first embodiment.

Next, the operation of the memory device 10A according to the second embodiment will be described with reference to FIGS. In addition, although FIG. 5 is written on the assumption that the area C is accessed, the same method can be used to access other locations.

First, the access area information input to the memory device 10 is input to the access area input circuit 12 and supplied to the access area determination circuit 13 and the select data determination circuit 14. In the access area determination circuit 13, read area determination is performed from the access area information supplied from the access area input circuit 12, and an independent word line (row line) is provided for each of the memory blocks 110 to 113 based on the row determination result. Selection signal S130 for selecting
To S133 are generated, and each memory block 110 to 11 is generated.
3 row decoders 1102, 1112, 1122, 113
2 is output. In addition, the select data determination circuit 14 performs column determination from the access area information supplied from the access area input circuit 12, and each of the memories 110 to 11 is determined.
And a second selection signal S for selecting a column decoder provided corresponding to 3 and selection target data (column) corresponding to the address.
14 is output to the generated output selector 15.

The row decoder 110 of each of the memory blocks 110 to 113 receiving the first selection signals S130 to S133.
2, 1112, 1122, and 1132, the corresponding rows in 110 to 113 in each memory block are accessed. In the example of FIG. 3, the C area is input as the access area, and the row decoders 1102, 1112, 1122, 1132 of the memory blocks 110 to 113 are marked with "
3 ”is transmitted. That is, here, the word line WL03 of the memory block 110 and the memory block 111 are transmitted.
The word line WL13, the word line WL23 of the memory block 112, and the word line WL33 of the memory block 113 are activated. Thereby, the word line WL03
The data of the 64 memory cells MC connected to the bit lines BL00 to 063 are read to the bit lines BL00 to 063, and the data of the 64 memory cells MC connected to the word line WL13 are read to the bit lines BL10 to 163. The data of the 64 memory cells MC connected to the line WL23 is the bit line B.
The data of the 64 memory cells MC read to L20 to 263 and connected to the word line WL33 is the bit line BL.
30 to 363. Bit lines BL00 to 06
3, BL10-163, BL20-263, and BL
The 64 × 4 = 256 data read out from 30 to 363 are sent to the sense amplifier 150 of the output selector 15, and the data is amplified and confirmed.

The 64 pieces of data in each fixed area are defined as a set of 4 pieces. FIG. 5 shows the situation as data on the screen, but as shown in FIG. 5, the data in each fixed area is divided into four internal blocks (0 to 15). And
The output data is first sent to the internal block selectors 155 to 158 for each block. An internal block to be selected, which is determined from the access area information in the select data determination circuit 14, is sent to the selected internal block, and the internal block is selected accordingly. That is, internal blocks 11 and 15 from the fixed area (0, 3), internal blocks 8 to 10 and 12 to 14 from the fixed area (1, 3),
From the fixed area (2, 3), internal blocks 3, 7, 11,
From the fixed area (3, 3), internal blocks 0-2, 4-
6, 8-10 are selected.

At this point, all the data in the selected internal block can be output, and in that case, a rough shape of a set of four data is output instead of an individual data unit. Become. The selected internal block is further sent to the column decoders 151 to 154 as an output selector for each block. These column decoders 151
To 154, the selection target data determined from the access area information in the select data determination circuit 14 is sent, and the data is selected and output accordingly. In the case of this example, the output data is the same as the case of FIG. That is, from the fixed area (0, 3) through the column decoder 151, each data of 46, 47, 54, 55, 62, 63, and from (1, 3) through the column decoder 152, 40 to 45, 48 to 53, 56. Each data of ~ 61,
From (2,3) through the column decoder 153 6,7,1
From each data of 4, 15, 22, 23, 30, 31, 38, 39, (3, 3) through the column decoder 154, 0 to
Data of 5, 8 to 13, 16 to 21, 24 to 29, and 32 to 37 are selected and output. As described above, the surface access to any place is performed.

According to the second embodiment, the above-mentioned first embodiment is used.
It is possible to obtain the same effect as that of the embodiment.

Third Embodiment FIG. 6 is a diagram for explaining a third embodiment of the present invention. In the third embodiment, surface access of any size is realized.

Surface Access of Arbitrary Size A surface access of an arbitrary size will be described. Basically, it is an extension of surface access to any place in the second embodiment described above. In the first and second embodiments, four fixed areas that are consecutively adjacent to each other are set as one data block area DTBLK, but in the third embodiment, FIG.
As shown in, the number of fixed areas (unit rectangular areas) FXRGN included in the data block area DTBLK, that is, the number of divisions of the data block area DTBLK is 4 to 9
By increasing the number to 1, it is possible to access the surface four times as large as the fixed area at any position. Similarly, with 16 divisions, it is 9 times the fixed area, and with 25 divisions, it is 1 of the fixed area.
Six times, the fixed area n ² (n = 1, 2, 3, ...) Can be read from any position.

Fourth Embodiment FIG. 7 is a diagram for explaining a fourth embodiment of the present invention. In the fourth embodiment, surface access to an arbitrary shape is realized.

Surface Access to Arbitrary Shape A surface access to an arbitrary shape will be described. Basically, it is an extension of the arbitrarily-sized face access of the third embodiment described above. As shown in FIG. 7, a fixed area (unit rectangular area) FXR included in the data block area DTBLK
By further increasing the number of GNs, that is, the number of divisions of the data block area DTBLK, a surface area of almost any shape can be read from any position within the range of the fixed area corresponding to the number of divisions. Similarly, increasing the number of divisions enables surface access to a larger portion.

Fifth Embodiment The fifth embodiment is an example in which the storage device according to the present invention is applied to moving image processing, and is an example of application to motion vector evaluation by a variable search range. In the fifth embodiment,
The advantages of applying the present invention to the motion vector calculation by the variable search range will be described, and then specific memory configurations and functions will be sequentially described with reference to the drawings.

Motion Vector Evaluation by Variable Search Range As described above, in motion picture processing, motion compensation inter-frame prediction is a basic compression method, and in order to do so, it is necessary to obtain a “motion vector”. . Among the motion vector calculation methods, the full search block matching method (F
ull Search Block Matching
Method) is the most common method. This method divides one screen of a moving image into blocks each consisting of (N × N) pixels, and shifts from the same coordinates to p pixels in both vertical and horizontal directions with respect to each reference block (X) of the current screen. The motion vector V is determined by comparing the previous frame image in the selected range as the search range and comparing all the candidate blocks (Y) in the search range. The full-search block matching method is a general method with high accuracy among the methods for obtaining motion vectors, but has a drawback that the calculation scale becomes extremely large. On the other hand, in the actual motion vector evaluation, the search range means the maximum motion that can be evaluated. That is, in principle, it is impossible to evaluate the motion larger than the search range. Therefore, in order to evaluate a large motion (fast motion), it is necessary to obtain a motion vector using a large search range,
It is necessary to perform a huge amount of calculation. From the above discussion, in order to perform motion vector calculation without waste, it is necessary to select an appropriate search range according to the motion. By applying the present invention, the motion vector calculation based on this variable search range can be easily executed.

FIGS. 8 and 9 are views for explaining the fifth embodiment of the present invention, and FIG. 8 is for explaining an example of reading the eye variable search range from the previous frame according to the present invention. FIG. 9 and FIG. 9 are flowcharts for explaining the motion vector calculation operation by the variable search range according to the present invention.

First, in the first motion vector calculation, the maximum possible search range is selected (ST1 in FIG. 9, for example, area A in FIG. 8). This pixel data extraction can be realized by a single memory access due to the features of the present invention. From the motion vector result obtained as a result, a search range for the next motion vector calculation is set (ST1 in FIG. 9).
For example, if the motion (2, 2) was obtained in the previous motion vector calculation, the search range is set to ± 4 in the next motion vector calculation. Then, the reference block is selected (ST2), and the pixel data in the reduced search range is read out based on the above setting (ST3). Even at this time, data can be taken out by one memory access due to the feature of the present invention. Motion vector calculation is performed using the read data (ST4).

The search range is set again using the result obtained by the second motion vector calculation (ST5, ST6).
For example, when the movement (2, 2) is obtained again, the search range remains unchanged at ± 4, and when it becomes small as (1, 1), it moves to ± 2, or the maximum search range. Value (4
In the case of 4), the movement that minimizes the actual sum of absolute differences may be outside the search range, so the search range is expanded to ± 8 and set. By repeatedly performing the above processing (ST2 to ST7), it is possible to eliminate waste of calculation and efficiently perform calculation when calculating a motion vector.

Variable Area Extraction In the above-described motion vector calculation, it was assumed that the calculation was performed on all the pixels included in the reference block. However, in reality, for the purpose of reducing the amount of calculation,
Instead of all pixels, as shown in FIGS.
Pixels may be thinned out, or a special shape such as a cross shape, a cross shape, or a triangle shape may be used. Such a case can be easily realized by applying the “access to an arbitrary shape” according to the fourth embodiment described above.

FIG. 11 is a diagram showing an example of the structure of a memory assuming a standard (Standard) TV according to the fifth embodiment. In addition, standard (Stand
As shown in FIG. 11A, one frame of ard) TV is composed of 720 × 576 pixels.

The memory 20 shown in FIG. 11 shows an example configured under the following conditions. 1). The minimum area is a 2 × 2 4-pixel area. The area is composed of 64 pixels, and a 4-pixel block is realized in the internal area 2). The maximum search range is ± 24 memory blocks divided into 81 3). The pixel value is 8 bits, and the constituent pixel value is expanded on the word line, and 512 bits are stored (arranged) in 512 memory cells MC connected to one word line.

In the memory 20 of this configuration example, FIG.
As shown in (A), first, a screen of 720 × 576 pixels is divided into 80 72 × 72 word blocks WDBLK. The word block WDBLK corresponds to a word line inside the memory, which will be described later. Further, each word block WDBLK is divided into a fixed region FXRGN of 8 × 8 pixels corresponding to 81 memory blocks, as shown in FIG. 11B. Further, as shown in FIG. 11C, data of 64 pixels × 8 bits is stored in each fixed area FXRGN.

A specific memory configuration for realizing such a configuration will be described with reference to FIG.

FIG. 12 is a block diagram showing the fifth embodiment of the memory device (storage device) according to the present invention.

The memory device 10C of FIG. 12 is different from the memory device 10 of FIG. 1 in that the number of memory blocks in the memory block group 11C is increased from 4 to 81, and the selection signal (select data) of the access area determination circuit 13C is used. Is input to the select data determination circuit 14. Other configurations and functions are basically the memory device 10 of FIG. 1 except for the memory array unit of the memory blocks 110C to 1180C.
Is the same as.

As shown in FIG. 12B, the memory block 110 is connected to a memory array section 1101C in which memory cells MC are arranged in an 80 × 512 matrix, a row decoder 1102C, and a row decoder 1102C. Eighty word lines WL00 to WL079 and 512 bit lines BL00 to BL05 connected to the output selector 15C and arranged to intersect the word lines WL00 to WL079 at right angles in the memory array section 1101C.
Have twelve. Each memory cell MC is, for example, NM
The word lines WL00 to WL079 and the bit lines B are configured by a DRAM including an OS transistor and a capacitor.
Located at the intersection with L00 to BL0512,
The gate of the transistor is connected to the corresponding word line,
The storage node is connected to the corresponding bit line via the NMOS transistor.

Similarly, the memory block 1179 is shown in FIG.
As shown in (B), a memory array unit 11791C in which memory cells MC are arranged in a matrix of 80 × 512
, A row decoder 11792C, and a row decoder 11792
80 word lines WL790 to WL79 connected to C
79 and the output selector 15C, and word lines WL790 to WL79 in the memory array unit 11791C.
It has 512 bit lines BL790 to BL79512 arranged so as to intersect with 79 at right angles. Each memory cell MC is composed of, for example, a DRAM including an NMOS transistor and a capacitor, and has a word line WL.
790 to WL7979 and bit lines 790 to BL7951
The gate of the NMOS transistor is connected to the corresponding word line, and the storage node is NMO.
It is connected to the corresponding bit line through the S transistor.

As described above, the memory device 10C has the configuration shown in FIG.
As shown in FIG. 2 (A), the whole is divided into 81 memory blocks 110C to 1180C. This number of 81 corresponds to the number of fixed areas FXRGN in FIG. 11 (B). Individual memory blocks 110C-11
The 80C is a memory composed of 80 word lines to which memory cells each having 64 × 8 = 512 bits are connected. The number 80 corresponds to the word block WDBLK in FIG. Further, the 512-bit data on the word line is divided into 8 × 4 × 4 × 16 internal areas per bit and stored, as shown in FIG.

In order to control such a structure, the address control system determines which word line in each memory block needs to be read from the input access area data, as shown in FIG. , A function of generating the address (row line address generating circuit 133, column line address generating circuit 142) and a function of deciding which data is selected from the data on the read word line are required. These functions are basically the same as in the case of FIG.

Next, an execution example of the full search block matching method by the above memory device will be described with reference to FIGS.
5 will be described.

FIG. 14 is an explanatory diagram of data that needs to be read when the full search block matching method is executed. FIG. 15 is a diagram showing the relationship between the area and the coordinates when the full search block matching method is executed.

To execute the full search block matching method, as described above, as shown in FIG. 14, it is necessary to read the reference block REFBLK of the current screen and the pixel data of the search range SRCRGN of the previous frame screen.

First, from the current frame, a reference block REFBLK of size 8 × 8 = 64 is transferred from the previous frame.
Consider extraction of a search area corresponding to the maximum search range ± 24. The simplest example is that the data of 64 pixels expanded on one word line in the memory coincides with the reference area as it is, and the search area is also 7 shown in FIG.
This is the case where it fits inside the 9 × 79 word block WDBLK. One example in this case is access to the area A in FIG.

For example, as the reference block REFBLK, as shown in FIG. 14B, (24, 24)-(3
When 1,1, 31) is selected, the search area when the search range is ± 24 is (0,0)-(55,55). When this is read as an actual memory access, the reference block REFBLK becomes the memory block 1130 in FIG.
Corresponding to the word line WL300. Also, the search area is
The memory block 11x (x = 0-6, 9-1 in FIG. 11)
5, 18-24, 27-33 ... 54-59).

Next, the reference area corresponds to one word line and the search area extends over a plurality of word blocks. An example of this case is access to the area B in FIG.

As the reference block REFBLK, (6
4,64)-(71,71), the search area when the search range is ± 24 is (40,40)-(1
03, 103). When this is read as an actual memory access, the reference block corresponds to the word line WL80, 0 of the memory block 1180 in FIG.

The search area is the memory block 11x (x = 50-53, 59-62, 68-71, memory block 11x of FIG. 12).
77-80) word line WLx, 0, memory block 1
1y (y = 45-47, 54-56, 63-65, 72
-74) word line WLy, 1, memory block 11z
(Z = 5-8, 14-17, 23-26) word line Q
Lz, 10, memory block 11w (w = 0-2, 9-
11, 18-20) corresponding to the word lines WLw, 11.

Further, consider the case where the reference block REFBLK straddles a plurality of word lines. An example of this case is access to the area C in FIG.

As the reference block REFBLK, (17
1,28)-(178,35), the search area when the search range is ± 24 is (146,4)-
(202, 59).

When this is read as an actual memory access, the reference block is the memory block 1130 in FIG.
From the word lines WL30, 2 of the pixels 40-47 and 56
-63, the word line WL31 of the memory block 1131,
2 to pixels 32-39 and 48-55, word line WL39 of memory block 1139, 2 to pixels 8-15 and 24-31, word line W of memory block 1140
This can be realized by reading the pixels 0-7 and 16-23 from L40,2. The extraction from the word line is realized by selecting the data read from the selected word line in bit line units.

Further, the reading of the search area is performed by the memory block 11x (x = 0-7, 9-16, 18-2) of FIG.
5, 27-34 ... 63-70) from the word lines WLx, 2 by extracting the same bit lines as in the reference block REFBLK. For these "extractions", it is necessary to convert the coordinate value indicating the access area into a word line address or a bit line address on the memory. This can be realized by using, for example, a relational table between coordinate values and word line addresses or the following simple relational expression.

First, each word block WDBLK is shown in FIG.
As shown in Fig. 5 (A), the "coordinates" are shaken and this is (X,
Y). Fixed area FX in each word block
Similarly, the "coordinates" shown in FIG. 15 (B) are also given to the RGN, and these are designated as (x, y). The "coordinate value" defined in this way is the coordinate value (ξ,
η) has the following relationship.

[0113]

[Equation 3]

[0114]

[Equation 4]

[0115]

[Equation 5]

[0116]

[Equation 6]

What has been described above is the search range ± 24.
However, the search range can be freely changed by changing the number of selected word lines. Further, the extraction of the variable region can be realized by applying a necessary filter when selecting the bit line.

[0118]

As described above, according to the present invention,
Without the need for multiple accesses or temporary memory,
It is possible to realize simultaneous access to the planar area.

By increasing the number of unit rectangular areas included in the data block area, n ² (n = 1, 2, 3, ...) Of the unit rectangular area at any position is read from any position. be able to. Further, by further increasing the number of unit rectangular areas included in the data block area, surface access to an arbitrary shape can be realized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of a memory device (storage device) according to the present invention.

FIG. 2 is a diagram for explaining data stored and read in each memory block according to the present invention,
It is a figure which shows the virtual memory in which 16 fixed areas of 8x8 size exist.

FIG. 3 is a diagram for explaining an access mode for data stored in each memory block according to the present invention.

FIG. 4 is a diagram for explaining configurations and functions of an access area determination circuit, a select data determination circuit, and an output selector according to the present invention.

FIG. 5 is a diagram for explaining a second embodiment of a memory device (storage device) according to the present invention.

FIG. 6 is a diagram for explaining a third embodiment of the present invention.

FIG. 7 is a diagram for explaining the fourth embodiment of the present invention.

FIG. 8 is a diagram for explaining the fifth embodiment of the present invention, and is a diagram for explaining an example of reading an eye variable search range from a previous frame according to the present invention.

FIG. 9 is a diagram for explaining the fifth embodiment of the present invention, and is a flowchart for explaining a motion vector calculation operation according to a variable search range according to the present invention.

FIG. 10 is a diagram for explaining the fifth embodiment of the present invention, for explaining a case where not all pixels are thinned out or a special shape such as a cross shape is used in motion vector calculation. FIG.

FIG. 11 shows a standard (St) according to the fifth embodiment.
It is a figure which shows the structural example of the memory which assumed the and-and-TV.

FIG. 12 is a fifth memory device (memory device) according to the present invention.
It is a block diagram showing an embodiment of.

13 is an explanatory diagram of functions that the address control system of FIG. 12 should have.

FIG. 14 is an explanatory diagram of data that needs to be read when the full search block matching method is executed.

FIG. 15 is a diagram showing a relationship between regions and coordinates when the full search block matching method is executed.

FIG. 16 is a block diagram showing a basic configuration example of a storage device (memory device).

FIG. 17 is a diagram for explaining a full search block matching method.

FIG. 18 is a diagram for explaining a read operation for a search range in a method of storing one line forming a screen at a row address of a memory.

[Explanation of symbols]

10, 10A to 10C ... Memory device, 11, 11C ... Memory block group, 110 ... First memory block, 110
1 ... Memory array section, 1102 ... Row decoder, 111 ...
Second memory block 1111 ... Memory array unit, 11
12 ... Row decoder, 112 ... Third memory block, 11
21 ... Memory array section, 1122 ... Row decoder, 113
... fourth memory block, 1131 ... memory array section, 1
132 ... Row decoder, 12 ... Access area input circuit, 1
3, 13C ... Access area determination circuit, 14, 14C ... Select data determination circuit, 15, 15C ... Output selector,
150 ... Sense amplifier, 151-154 ... Column decoder,
155 to 158 ... Internal block selector, 110C to 1
180C ... Memory block, MRY1 to MRY5 ... Virtual memory, FXRGN ... Fixed area (unit rectangular area), D
TBLK ... Data block.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/34 354B F term (reference) 5B015 HH01 HH03 JJ21 KB44 5B060 AC13 GA11 5M024 AA49 AA50 AA90 BB07 DD62 DD63 JJ30 KK24 PP01 PP10

Claims (24)

[Claims] 1. A matrix can be divided into unit rectangular areas containing a plurality of data, and a predetermined number of continuously adjacent rectangular areas can be divided into a plurality of blocks as one associated data block area. A storage device for storing data of a desired area from a data group, comprising at least a plurality of memory blocks corresponding to a predetermined number of unit rectangular areas included in the partitionable data block, Each memory block has a memory array section in which a plurality of memory cells are arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area, and the same row. A plurality of row lines corresponding to the number of rows in the memory array section for activating a plurality of memory cells arranged in a memory array, and a plurality of memories arranged in the same column. A plurality of column lines for transmitting and receiving data to and from the activated memory cells in the memory cell, corresponding to the number of data in the unit rectangular area, and one row line among the plurality of row lines according to a selection signal. And a row decoder for activating the memory. 2. A plurality of data in each unit rectangular area included in the one data block area is stored in a plurality of memory cells connected to a predetermined one row line of a memory block different for each unit rectangular area. The storage device according to claim 1, which is stored. 3. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks has a value of x. And a plurality of row lines of each memory block are respectively assigned with numbers corresponding to the value of y, and a plurality of data of each unit rectangular area are associated with each other according to the value of x. The data is stored in a plurality of memory cells connected to the row line having a number corresponding to the value of y in the memory block. The storage device according to claim 1. 4. The storage device according to claim 3, wherein the selection signal specifies the value of y to a row decoder. 5. The storage device according to claim 1, wherein the two-dimensionally arranged data group is moving image data. 6. A matrix can be divided into unit rectangular areas containing a plurality of data, and a predetermined number of adjacent rectangular areas can be divided into a plurality of blocks as one associated data block area. A storage device for storing data of a desired area from a data group, comprising at least a plurality of memory blocks corresponding to a predetermined number of unit rectangular areas included in the partitionable data block, Each memory block has a memory array section in which a plurality of memory cells are arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area, and the same row. A plurality of row lines corresponding to the number of rows in the memory array section for activating a plurality of memory cells arranged in a memory array, and a plurality of memories arranged in the same column. A plurality of column lines for transmitting and receiving data to and from the activated memory cells in the memory unit, corresponding to the number of data in the unit rectangular area, and one of the plurality of row lines corresponding to the first selection signal. And a plurality of data in each unit rectangular area included in the one data block area,
The plurality of first selection signals are stored in a plurality of memory cells connected to a predetermined one row line of a different memory block for each unit rectangular area, and further, a plurality of the first selection signals are generated based on access area information, and corresponding An access area determination circuit for outputting to a row decoder of the memory block; an output selector for selecting and outputting the data read to the plurality of column lines of the plurality of memory blocks according to a second selection signal; A storage device having a select data determination circuit that generates a signal indicating selection target data to be selected and output based on area information and outputs the signal as the second selection signal to the output selector. 7. The unit rectangular area is divided into a plurality of internal blocks, and the select data determination circuit generates a signal indicating an internal block to be selected based on access area information, and outputs the second selection signal. And outputting to the output selector, the output selector having a plurality of internal block selectors corresponding to the respective memory blocks, selecting an internal block according to the second selection signal, and outputting desired data. 6. The storage device according to item 6. 8. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks has a value of x. And a plurality of row lines of each memory block are respectively assigned with numbers corresponding to the value of y, and a plurality of data of each unit rectangular area are associated with each other according to the value of x. 7. The memory device according to claim 6, wherein the memory block is stored in a plurality of memory cells connected to a row line having a number corresponding to the value of y. 9. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks has a value of x. And a plurality of row lines of each memory block are respectively assigned with numbers corresponding to the value of y, and a plurality of data of each unit rectangular area are associated with each other according to the value of x. 8. The storage device according to claim 7, which is stored in a plurality of memory cells connected to a row line having a number corresponding to the value of y of the memory block. 10. The memory device according to claim 8, wherein said access area judgment circuit specifies the value of y to each row decoder by said first selection signal. 11. The storage device according to claim 9, wherein the access area determination circuit specifies the value of y to each row decoder by the first selection signal. 12. The storage device according to claim 6, wherein the two-dimensionally arranged data group is moving image data. 13. The storage device according to claim 7, wherein the two-dimensionally arranged data group is moving image data. 14. A matrix can be divided into unit rectangular areas containing a plurality of data, and a predetermined number of adjacent rectangular areas can be divided into a plurality of blocks as one associated data block area. A storage method for storing data in a desired area from a data group in a plurality of memory blocks at least corresponding to a predetermined number of unit rectangular areas included in the data block that can be divided, In each of the above, a plurality of memory cells are arranged in a matrix with the number of rows corresponding to the number of the data block areas and the number of columns corresponding to the number of data in the unit rectangular area, and are included in the one data block area. A plurality of memory cells arranged in a predetermined row of a memory block that is different for each unit rectangular area. How to store in. 15. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks is assigned a value of x. And a number corresponding to the value of y is given to each of the plurality of rows of each of the memory blocks, and a plurality of data of each of the unit rectangular areas are associated with each other according to the value of x. 15. The storage method according to claim 14, wherein the storage is performed in a plurality of memory cells arranged in a row having a number corresponding to the value of y in the memory block. 16. The storage method according to claim 14, wherein the two-dimensionally arranged data group is moving image data. 17. A matrix can be divided into unit rectangular areas containing a plurality of data, and a predetermined number of adjacent rectangular areas can be divided into a plurality of areas as one associated data block area. A storage device for storing data of a desired area from a data group, comprising at least a plurality of memory blocks corresponding to a predetermined number of unit rectangular areas included in the partitionable data block, Each memory block has a memory array section in which a plurality of memory cells are arranged in a matrix with the number of rows corresponding to the number of data block areas and the number of columns corresponding to the number of data in the unit rectangular area, and the same row. A plurality of row lines for activating a plurality of memory cells arranged in the same row, and a plurality of row lines corresponding to the number of rows in the memory array section, and a plurality of memory cells arranged in the same column A plurality of column lines corresponding to the number of data in the unit rectangular area for transmitting and receiving data to and from the activated memory cells in the cells, and one of the plurality of row lines corresponding to the first selection signal. A plurality of data in each unit rectangular area included in the one data block area is stored in a predetermined one row line of a different memory block for each unit rectangular area. A method of accessing a memory device stored in a plurality of connected memory cells, wherein a plurality of the first selection signals are generated based on access area information and supplied to a row decoder of a corresponding memory block, A signal indicating selection target data to be selected and output based on the access area information is generated as a second selection signal, and the data read out to the plurality of column lines of the plurality of memory blocks is set to the first selection signal. Access method of the memory device having a select output in response to the selection signal. 18. The unit rectangular area is divided into a plurality of internal blocks, and a signal indicating an internal block to be selected is generated as the second selection signal based on access area information, and the second selection signal is generated. 18. The method of accessing a storage device according to claim 17, wherein an internal block is selected in accordance with the above, and desired data is output. 19. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks is assigned a value of x. And a number corresponding to the value of y is given to each of the plurality of rows of each of the memory blocks, and a plurality of data of each of the unit rectangular areas are associated with each other according to the value of x. 18. The method of accessing a storage device according to claim 17, wherein the storage is performed in a plurality of memory cells arranged in a row having a number corresponding to the value of y in the memory block. 20. The data block areas are arranged in a matrix, and when the unit rectangular area of each data block is addressed in the form of (x, y), each of the plurality of memory blocks is assigned a value of x. And a number corresponding to the value of y is given to each of the plurality of rows of each of the memory blocks, and a plurality of data of each of the unit rectangular areas are associated with each other according to the value of x. 19. The access method for a storage device according to claim 18, wherein the storage is performed in a plurality of memory cells arranged in a row having a number corresponding to the value of y in the memory block. 21. The method of accessing a storage device according to claim 19, wherein the value of y is designated to each row decoder by the first selection signal. 22. The access method of a storage device according to claim 20, wherein the access area determination circuit specifies the value of y to each row decoder by the first selection signal. 23. The method for accessing a storage device according to claim 17, wherein the two-dimensionally arranged data group is moving image data. 24. The method of accessing a storage device according to claim 18, wherein the two-dimensionally arranged data group is moving image data.