JP2003188691A - Flip-flop circuit, shift register and scan driving circuit for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit of which bidirectional operation control can be easily performed, a shift register of which bidirectional operation control and bidirectional scan control can be easily performed, and which is suitable for a display device driving circuit for a small and thin device, and a scan driving circuit for a display device. <P>SOLUTION: In this circuit, an input terminal of a flip-flop circuit in master/slave form which is formed by connecting two inverters in a loop shape is connected to a first terminal through a first switch circuit, an output terminal of the flip-flop circuit is connected to a second terminal through a second switch circuit, a third switch circuit is provided between the path from the first switch circuit to the input terminal and the second terminal, and a fourth switch circuit is provided between the path from the output terminal to the second switch circuit and the first terminal. The first and second switch circuits are turned on and the third and fourth switch circuits are turned off, thereby using the first terminal as an input and the second terminal as an output, and the first and the second switch circuits are turned off and the third and the fourth switch circuits are turned on, thereby using the second terminal as an input and the first terminal as an output. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, a shift register, and a scan drive circuit of a display device using the same, and more specifically, so-called bidirectional operation in which input and output can be switched in reverse. And a flip-flop circuit that requires less increase in circuit scale,
The present invention relates to a shift register constituted by this flip-flop circuit, which is easy to control a shift operation in a forward direction and a reverse direction, and which is suitable for a scan drive circuit of a small and thin display device, and a scan drive circuit thereof.

[0002]

2. Description of the Related Art As a flip-flop used in an integrated circuit, a master-slave type D-type flip-flop circuit as shown in FIG. 4 in which inverters are connected in a loop is often used. In the figure, CK is a clock signal, * CK is a clock signal whose phase is inverted, 1
Is a master side latch circuit, and 2 is a slave side latch circuit. Here, the master side latch circuit (master flip-flop) 1 includes two inverters 3
a, 3b and two transmission gates 4a, 4b as analog switches, and the slave side latch circuit (slave flip-flop) 2 has two inverters 3d, 3e and 2 as analog switches.
It is composed of two transmission gates 5a and 5b. When the flip-flop circuit based on these operates as a master or a slave, the transmission gates 4a and 5b and the transmission gates 4b and 5a are turned "ON-OFF" at the timings of opposite phases. In this flip-flop circuit, the terminal 11 is the input side and the terminal 12 is the output side. By the way, in the figure, the symbol "*" is
It means an inverted signal, and hereinafter "*" is used in the same meaning. The applicant has applied for a bidirectional operation flip-flop circuit that can switch the input and output in reverse, which is an improvement of the flip-flop circuit of FIG. 4 (Patent Document 1). FIG. 5 shows the bidirectional operation flip-flop circuit.

[0003]

[Patent Document 1] Japanese Patent Publication No. 6-54860

Reference numerals 6 and 7 are transmission gates similar to the transmission gates 4a and 4b of FIG. 4, respectively, and 8 is a transmission gate added to the output terminal 12 side of the flip-flop circuit of FIG. In this D-flip-flop circuit, an input / output terminal 14 is provided behind the transmission gate 8 instead of the output terminal 12 in FIG. 4, and the input terminal 11 in FIG. In this circuit, flip-flops 9a and 9b are arranged symmetrically with respect to the transmission gate 5a, and have a symmetrical structure as a whole. So flip-flop 9
Either one of a and 9b can be a master flip-flop and the other can be a slave flip-flop, and a bidirectional operation D-flip-flop circuit that switches input and output in reverse. The shift register utilizing this can select the shift direction. The selection is performed by exchanging the master and the slave of the flip-flop (latch circuit) 9a and the flip-flop (latch circuit) 9b forming the shift register.

[0005]

However, when the shift register is configured by the bidirectional operation flip-flop circuit of FIG. 5, it is easy to select and set the shift direction to either one later, but the dynamic direction is dynamic. If a shift register that operates bidirectionally is configured, an operation control circuit that replaces the master and slave flip-flops of the D-flip-flops at each stage of the shift register is required. For LCD display and LED display,
Dynamic inversion scanning is required when the display image is displayed in a mirror. Further, in an organic EL display device or the like, in order to improve display brightness, a panel divided into upper and lower halves is simultaneously scanned in the opposite direction from the top and the bottom in the vertical direction. Therefore, the scan drive circuit of this type of display device requires a bidirectional shift register.

On the other hand, in this type of device, downsizing of the device,
The increase in circuit scale is not desirable because of the demand for thinning. However, when a shift register is formed by using the bidirectional operation flip-flop circuit of FIG. 5 and is used as a bidirectional scanning drive circuit of a display device, transmission gates arranged on both sides of input and output. A circuit for controlling the input / output of the timing of 4a and the transmission gate 8 in accordance with the input / output direction and the clock CK is required for each stage of the shift register, and there is a problem that the circuit scale increases correspondingly. An object of the present invention is to solve the above-mentioned problems of the prior art, and it is easy to perform bidirectional operation control in which the input and output can be switched in reverse and to reduce the increase in circuit scale. To provide a loop circuit. Another object of the present invention is to provide a shift register in which bidirectional operation control is easy. Still another object of the present invention is to provide a scan drive circuit for a display device in which bidirectional operation control is easy.

[0007]

The features of the flip-flop circuit of the first invention for achieving the above object are as follows.
A master-slave type flip-flop circuit having two stages of circuits, each having an input terminal and an output terminal, connected in a loop, in a master-slave type flip-flop circuit, the first terminal connecting the input terminal and the first terminal. A switch circuit, and a second switch circuit connecting the output terminal and the second terminal,
A third switch circuit provided between the second terminal and the path from the first switch circuit to the input terminal; and a path from the output terminal to the second switch circuit and the first A fourth switch circuit provided between the first and second switch circuits and the first and second switch circuits are turned on and the third and fourth switch circuits are turned off. Is an input, the second terminal is an output, and conversely the first and second switch circuits are OF
When set to F and the third and fourth switch circuits are turned on, the second terminal serves as an input and the first terminal serves as an output.

The flip-flop circuit according to the second invention is characterized by the first inverter, the first switch circuit connected to the input side of the first inverter, and the first switch circuit.
A unit circuit having a second inverter connected to the output side of the inverter and a second switch circuit inserted between the output side of the second inverter and the input side of the first inverter. A cascade connection in which this unit circuit is cascade-connected in two stages with the side of the first switch circuit not connected to the first inverter as an input terminal and the output side of the first or second inverter as an output terminal. Circuit,
A third switch circuit that connects the input terminal of the unit circuit in the preceding stage of the subordinate connection circuit to the first terminal, and a third switch circuit that connects the output terminal of the unit circuit in the subsequent stage of the subordinate connection circuit to the second terminal. And a fifth switch circuit inserted between the second terminal and the path from the third switch circuit to the input terminal of the unit circuit at the preceding stage,
A third switch circuit having a sixth switch circuit inserted between the path from the output terminal of the unit circuit in the subsequent stage to the fourth switch circuit and the first terminal, and the third and fourth switch circuits. Is turned on and the fifth and sixth switch circuits are turned off.
When it is turned off, the first terminal becomes an input, and the second terminal
The terminal becomes an output, and conversely the third and fourth switch circuits are turned off and the fifth and sixth switch circuits are turned on.
Then, the second terminal becomes an input and the first terminal becomes an output. Further, a feature of the shift register and the scan drive circuit of the display device of the present invention is that a plurality of flip-flop circuits of the first invention or the second invention are cascade-connected to form a shift register, or this shift register is It is used for a scan drive circuit of a display device.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION As described above, a master circuit for use in an integrated circuit, in which inverters are connected in a loop, is used.
In the slave type flip-flop circuit, its input terminal is connected to the first terminal via the first switch circuit, and its output terminal is connected to the second terminal via the second switch circuit. When the first and second switch circuits (third and fourth switch circuits in the second invention) are turned on, the first terminal serves as an input and the second terminal serves as an output.
It is possible to operate a normal master / slave type flip-flop circuit. On the other hand, first and second switch circuits (third and fourth switch circuits in the second invention)
Is turned off, the input and output terminals of this flip-flop circuit are separated from the first and second terminals, and the third and fourth switch circuits (fifth and sixth switch circuits in the second invention) are turned on. Then, the second terminal is connected to the input of the master flip-flop via the third switch circuit (the fifth switch circuit in the second invention), and the first terminal is connected to the fourth switch circuit (the fourth switch circuit). In the second aspect, it is connected to the output of the slave flip-flop via the sixth switch circuit). This allows the input terminal and the output terminal to be interchanged.

That is, by controlling ON / OFF of the first switch circuit to the fourth switch circuit (the third to sixth switch circuits in the second invention), the input terminal and the output terminal of the flip-flop circuit are controlled. Can be reversed and the first and second terminals can be bidirectional input / output terminals. Control of the input / output direction in this case is performed by turning on / off the first to fourth switch circuits (third to sixth switch circuits in the second invention).
Since OFF is control that is not related to the clock CK, a simple ON / OFF control signal is sufficient. Moreover,
The four switch circuits, their connections, and the wiring amounts for operation do not increase the circuit scale as much as the bidirectional timing control circuit that controls the input / output timing according to the input / output direction and the clock CK. As a result, the bidirectional operation flip-flop circuit that can switch the input and output in the opposite direction turns the switch ON / OF in a form that suppresses the circuit scale.
It can be easily realized by switching F. By configuring a shift register using this bidirectionally operating flip-flop, it is possible to form a shift register that can easily switch the input / output direction. By using this shift register in a drive circuit that performs bidirectional scan control, it is possible to realize a scan drive circuit of a display device in which bidirectional control is easy.

[0011]

1 is a block diagram of a flip-flop circuit of a shift register according to an embodiment of the present invention, FIG.
3 is an explanatory diagram of a shift register of a scan drive circuit of a display device including the flip-flop circuit, and FIG.
FIG. 3 is a block diagram of an embodiment centering on an organic EL display panel of an organic EL display device in which a row line driving circuit is configured by the shift register shown in FIG. 2. In the following description of FIGS. 1 to 3, the same configurations as those in FIGS. 4 and 5 are denoted by the same reference numerals, and the description thereof will be omitted. The flip-flop circuit 10 shown in FIG. 1 includes a master-side latch circuit 1a corresponding to the master-side latch circuit (master flip-flop) 1 shown in FIG. 4 and a latch circuit corresponding to the slave-side latch circuit (slave flip-flop) 2 shown in FIG. 2a and. Input terminal 11 of the flip-flop circuit of FIG.
Input point 11a and input / output terminal (I / O terminal) 1 corresponding to
5, a transmission gate 8a for switching the input / output direction is provided. A transmission gate 8b for switching the input / output direction is provided between the output point 12a corresponding to the output terminal 12 and the I / O terminal 16. Further, I / O terminals 15 and 16 are provided in place of the input terminal 11 and the output terminal 12 of FIG. Input point 1
1a and the I / O terminal 16 are connected by a wiring line 17 via a transmission gate 8c for switching the direction, and the output point 12a and the I / O terminal 15 are connected via a transmission gate 8d for switching the input / output direction. It is connected by 18.

In the flip-flop circuit 10, the inverters 3b and 3d shown in FIG. 4 are NAND gates 31 and 32, respectively.
Has been replaced by. This is because the reset signal RS is received at the terminal 27 so that the flip-flop circuit 10 is reset. Further, in the flip-flop circuit 10, an inverter 21 is inserted between the input point 11a and the transmission gate 4a, and the output point 12a
The inverter 22 is inserted in front of the above, but these are provided for timing adjustment, and are not necessarily provided. The transmission gates 8a to 8d for switching each direction receive the direction switching signal Way output from the controller at the terminal 19 and are ON / OFF controlled by "H" (HIGH level) and "L" (LOW level) of the terminal 19. It The direction switching signal Wa
As for y, an inverted signal * Way is generated via the inverter 20 and added to the inverted input side of each of the transmission gates 8a to 8d. The clock CK is
External clock signal CLK applied to clock terminal 25
Which is an internal signal corresponding to, and an inverted clock * CK is generated by passing it through an inverter 26, and these clocks CK and * CK are added to each transmission gate 4a, 4b, 5a, 5b. Flip-flop circuit 10
Q output (* Q) of the inverter 2 from the back of the transmission gate 5a of the slave side latch circuit 2a.
3 is applied to the terminal 24 and output from this terminal. The Q output of the flip-flop circuit 10 is determined by the direction switching signal Way, and one of the I / O terminals 15 and 16 becomes its input and the other becomes its output, depending on the direction of the data shift.

When the direction switching signal Way input to the terminal 19 is "H", the transmission gates 8a and 8b are turned on and the transmission gates 8c and 8d are turned off. Therefore, the input point 11a is
It is connected to the I / O terminal 15, and this terminal serves as an input. The output point 12a is connected to the I / O terminal 16, and this terminal serves as an output. This is a flip-flop circuit composed of a master side latch circuit 1a and a slave side latch circuit 2a in which the I / O terminal 15 is an input and the I / O terminal 16 is an output. At this time, since the transmission gates 8c and 8d are off, the input point 11
a is not connected to the I / O terminal 16 side. The output point 12a is not connected to the I / O terminal 15 side. On the other hand, the direction switching signal Way input to the terminal 19 is "L".
When, the transmission gates 8a and 8b are O
It becomes FF and the transmission gates 8c and 8d are O
N. Therefore, the input point 11a is connected to the I / O terminal 16 and this terminal serves as an input. Also, the output point 12a
Is connected to the I / O terminal 15, and this terminal serves as an output. This is the same as the above, which is the flip-flop circuit including the master side latch circuit 1a and the slave side latch circuit 2a, but the I / O terminal 16 serves as an input and the I / O terminal 15 serves as an output. So, the input and output are flip-flop circuits with the opposite. At this time, since the transmission gates 8a and 8b are OFF, the input point 11a is not connected to the I / O terminal 15 side. The output point 12a is not connected to the I / O terminal 16 side. As described above, the shift register 30 (see FIG. 2) configured by the flip-flop circuit 10 can switch the input / output direction by the "H" and "L" of the direction switching signal Way input to the terminal 19. it can.

FIG. 2 shows a flip-flop circuit 10 (DF
Shift register 3 in which the Q output and the input of F) are cascade-connected
0 and I / O of the flip-flop circuits 10 at both ends
The terminals 15 and 16 are connected to input / output terminals (I / O terminals) 37 and 38 at both ends of the shift register 30, respectively. Direction switching signal Way of each flip-flop circuit 10
Is connected to the Way terminal 33, and the clock terminal 25 of each flip-flop circuit 10 is connected to the clock terminal 34.
, And the reset signal terminal 27 of each flip-flop circuit 10 is connected to the reset terminal 35. Then, the Q-bar outputs (* Q) 30a to 30n of the respective flip-flop circuits 10 are taken out to the respective row lines of the scanning drive circuit of the display device via the inverter 36. At this time, I / O
The data set in either of the terminals 37 and 38 is data of the number of digits corresponding to the number of lines in which the digit corresponding to the driving line position is "0" and the other digits are "1", for example,
“1110111 ... 11” is the controller 105 in FIG.
To the shift register 30 (the row driver 103 in FIG.
a and the row driver 103b).

In this circuit, the data is shifted in accordance with the external clock CLK input to the clock terminal 34, so that the Q-bar output (* Q) is "" at the bit "0" position in the data string. H "pulse is generated. This becomes an "L" output through the inverter 36, and drives the line at the scanning position among the row lines of the display panel. Then, the above-mentioned data is shifted to the upper digit (right side) or the lower digit (left side) of the shift register 30 according to the clock CK, so that the low-line scanning is performed. At this time, if a signal of "H" is input from the controller 105 to the terminal 19 of the direction switching signal Way,
The transmission gates 8a and 8b are turned on, the transmission gates 8c and 8d are turned off,
Drive scanning is performed from the I / O terminal 37 toward the I / O terminal 38. On the contrary, when the signal “L” is input from the controller 105 to the terminal 19 of the direction switching signal Way,
The transmission gates 8a and 8b are turned off,
The transmission gates 8c and 8d are turned on,
Drive scanning is performed from the I / O terminal 38 toward the I / O terminal 37.

Such a shift register 30 is an organic EL device.
FIG. 3 shows an embodiment used in the shift register of the scan drive circuit of the display device. 3 is an organic EL having a drive circuit for driving a row line using the shift register 30 of FIG.
It is an embodiment centering on an organic EL display panel of a display device. In FIG. 3, reference numeral 100 denotes an organic EL display device for a mobile phone, which has 396 (198 × 2) terminal pins (hereinafter referred to as pins) having 396 column lines and 162 (81 × 2) pins having row lines. It is an organic EL display panel. This panel takes a form in which two upper and lower EL panels 101a and 101b are joined at the central portion. Two column driver ICs (hereinafter, column driver) 102a, 1 are provided on the upper side of this.
02b is provided, and two column drivers 10 are also provided on the lower side.
2c and 102d are provided. Then, 103a and 103 corresponding to the EL display panels 101a and 101b are used as row driver ICs (hereinafter referred to as row drivers).
b is provided. For each driver, 66 pins are internally allocated to each of R, G, and B in one column terminal drive IC for color display, and a total of 6 pins are provided.
The column output is 6 × 3 = 198 pins. In the figure, it is simplified and shown without distinction between R, G, and B. Each column driver 102a, 102b, 102c,
102d and the row drivers 103a and 103b operate by being supplied with power from a power supply (battery) 104 for driving the organic EL display panel. This power supply voltage is normally 12V-
One voltage in the range of about 15V, for example, 15V
Is used.

Row driver 103a and row driver 10
It is assumed that the same driver IC has the I / O terminal 37 as the data input terminal and the I / O terminal 38 as the data output terminal of the shift register 30 of 3b. Where controller 1
The output of the direction switching signal Way output from 05 is sent to the Way terminal 33 of the row driver 103a and further sent to the Way terminal 33 of the row driver 103b via the inverter. As a result, the row driver 103a and the row driver 103b scan in opposite directions. These drivers operate according to a control signal from the controller 105. The column driver side scans each output line as a horizontal direction line, and the row driver side scans each output line as a vertical direction line. The controller 105 is controlled by the arithmetic processing unit (MPU) 106 and operates by receiving electric power from a power source (battery) 107 having a voltage of 3V. Therefore, the power supply 10 for driving the organic EL display panel
4 can be obtained by boosting the voltage from the battery power source 107 using a DC-DC converter.

Here, the row driver 103a scans the EL panel 101a in the vertical direction from the top to the bottom as shown in the drawing, and the row driver 103b controls the EL panel 101a.
The vertical scanning of the panel 101b is performed from bottom to top.
These scanning directions are opposite. The reason is,
This is because the luminance is doubled by vertically scanning the two panels at the same time, and the joint between the two panels can be made inconspicuous by scanning in the opposite directions. In this case, the scanning directions of the row driver 103a and the row driver 103b are opposite, but by using the shift register of FIG. 2, the direction switching signal Way from the controller 105 is used.
Even if the row driver 103a and the row driver 103b are configured by the same driver IC, scanning can be performed in the opposite direction by simply sending the above, and both scanning driving directions can be easily made opposite.

The vertical scanning operation will be described below.
First, from the controller 105, “0111111 ... 1
The digit number data for the number of lines of "1" is supplied to the row driver 103a.
In the shift register 30 of FIG. Also, the digit number data for the number of lines “111111 ... 10” from the controller 105 is transferred to the shift register 30 of the row driver 103b.
Set to. Way terminal 33 of the row driver 103a
Is supplied with a “H” signal from the controller 105,
A "L" signal is applied from the controller 105 to the Way terminal 33 of the row driver 103b via an inverter. As a result, the scanning directions of the row driver 103a and the row driver 103b are reversed. Low driver 10
3a has a digit position of "0" in the first stage, and generates a scan drive signal from top to bottom in the vertical direction of the EL panel 101a according to the clock CLK. Low driver 103b
Generates a scan drive signal from the bottom to the top in the vertical direction of the EL display panel 101b according to the clock CLK when the digit position of the first stage (the last stage in the positive direction) is "0" in the reverse scanning. As a result, the row driver 103a and the row driver 103b can simultaneously perform scanning in opposite directions according to the clock CLK sent from the controller 105 to the clock terminal 34. With such a bidirectional shift register 30, it becomes possible to use the same driver IC as the column driver of the display device, and the direction can be easily switched by the direction switching signal Way. As a result, the control circuit is simple.

As described above, in the embodiment shown in FIG.
Vertical scan row driver 103a and row driver 103
Although a case has been described in which the scanning direction with respect to b is controlled in the opposite direction at the same time, in the case of displaying a display image in a mirror, reverse scanning is required for the same driver in the horizontal direction. Of course, the shift register of FIG. 2 can be used for this horizontal scanning. In such scanning, switching control of the scanning direction can be easily performed by changing the control signal Way between "H" and "L". By the way, in the embodiment of the flip-flop circuit of FIG. 1, one of the inverters of the flip-flop is a NAND gate instead of the inverter in order to provide the reset terminal, but the operation is equivalent to that of the inverter, Of course, it can be treated as. In this specification and claims, such an inverter-operated gate circuit is also included in the inverter.

Further, in the embodiment, the output of the master side latch circuit (master flip-flop) 1a is taken out from the inverter 3a and input to the slave side latch circuit (slave flip-flop) 2a. However, it goes without saying that the output of the master side latch circuit 1a may be taken out from the NAND gate 31 and input to the slave side latch circuit 2a. In this case, the output of the slave side latch circuit 2a is taken out from the inverter 3e. In such a configuration, the * Q output taken out at the terminal 24 is
It can be taken out directly from the transmission gate 5a without going through the inverter 23. It should be noted that the * Q output in the embodiment may be taken out from any position as long as it is a wiring path that can obtain an output that is the inverse of the Q output of the slave side latch circuit 2a. Furthermore, in the embodiment, the transmission gate is used as the switch circuit, but other forms of analog switch or M
Of course, a switch circuit such as an OSFET transistor or a bipolar transistor may be used. In the embodiment, the example of the organic EL display panel is given, but the switching of the scanning direction is performed in the mirror display or the like, and therefore, the present invention can be applied to various display devices.

[0022]

As described above, according to the present invention, the first input terminal of the master-slave type flip-flop circuit in which two inverters are connected in a loop is provided.
Is connected to the first terminal via the switch circuit and the output terminal is connected to the second terminal via the second switch circuit. When the first and second switches are turned on, the first terminal serves as an input and the second terminal serves as an output, so that a normal master-slave flip-flop circuit can be operated. When the 1st and 2nd switches are turned off, the input and output of this flip-flop circuit are separated, and the 3rd and 4th switches are turned on, the second terminal causes the master flip-flop via the third switch. , And the first terminal is connected to the output of the slave flip-flop via the fourth switch. This allows the input terminal and the output terminal to be interchanged. As a result, the bidirectional operation flip-flop circuit can be easily realized by switching the switch ON / OFF while suppressing the circuit scale. By configuring a shift register using this bidirectionally operating flip-flop, it is possible to easily form a shift register capable of bidirectional switching.
By using this shift register in a display device drive circuit in which bidirectional scan control is easy, a scan drive circuit in a display device in which bidirectional control is easy can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a flip-flop circuit of a shift register according to an embodiment of the present invention.
Block diagram of the road,

FIG. 2 is an explanatory diagram of a shift register of a scan drive circuit of a display device including the flip-flop circuit.

FIG. 3 is an organic EL of an organic EL display device in which a row line driving circuit is configured by the shift register shown in FIG.
It is a block diagram of an example centering on a display panel.

FIG. 4 is a block diagram of a flip-flop circuit that constitutes a conventional shift register.

FIG. 5 is a block diagram of a bidirectional operation flip-flop circuit that constitutes a conventional shift register.

[Explanation of symbols]

1, 1a, 2, 2a ... Latch circuit, 3a, 3b, 3c,
3d ... Inverter, 4a, 4b, 5a, 6, 7, 8, 8
a to 8d ... Transmission gate, 10 ... Flip-flop circuit, 11, 12, 13, 14, 19, 24,
26 ... Terminal, 15, 16 ... I / O terminal, 17, 18 ... Wiring line, 25 ... Clock terminal, 20-23 ... Inverter, 30 ... Shift register, 30a-30n ... Q bar output (* Q), 31, 32 ... Input / output terminals, connected to 31, 32. 100 ... Organic EL display panel, 101
a, 101b ... EL panel, 102a, 102b ... Column driver IC, 103a, 103b ... Row driver I
C, 104 ... Power source (battery), 105 ... Controller, 1
06 ... Arithmetic processing unit (MPU), 107 ... Battery power supply.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/70 H04N 5/70 AF term (reference) 5C006 BC03 BC11 BF03 EB04 EB05 FA41 5C058 AA06 AA12 BA02 BA03 BB25 5C080 AA05 AA06 AA10 BB05 DD22 DD28 JJ02 JJ03 5J043 AA05 HH01 HH05 JJ08 JJ10 KK01 KK04

Claims (19)

[Claims] 1. A master-slave type flip-flop circuit comprising two stages of circuits, each having an input terminal and an output terminal, in which two inverters are connected in a loop, wherein the input terminal and the first terminal are A first switch circuit connecting the output terminal and the second terminal, a second switch circuit connecting the output terminal and the second terminal, a path from the first switch circuit to the input terminal, and the second terminal A third switch circuit provided between the output terminal and the second switch circuit, and a fourth switch circuit provided between the first terminal and the path; And the second switch circuit is turned on and the third and fourth switch circuits are turned off, the first switch is turned on.
Becomes an input, the second terminal becomes an output, and conversely, when the first and second switch circuits are turned off and the third and fourth switch circuits are turned on, the second The flip-flop circuit is characterized in that the terminal is an input and the first terminal is an output. 2. A predetermined terminal for receiving one of a HIGH level signal and a LOW level signal, wherein the first and second switch circuits receive the one signal at the predetermined terminal. It is turned on and the third and fourth switch circuits are turned off, and the H terminal is connected to the predetermined terminal.
When the other one of the IGH level and the LOW level is received, the first and second switch circuits are turned off.
The flip-flop circuit according to claim 1, wherein the flip-flop circuit is FF and the third and fourth switch circuits are ON. 3. At least one of the two inverters is a gate circuit that operates as an inverter, and the first to fourth switch circuits are high level and LOW level signals via the predetermined terminals. 3. The flip-flop circuit according to claim 2, which selectively receives any one of the above. 4. A first inverter, a first switch circuit connected to the input side of the first inverter, a second inverter receiving the output of the first inverter, and a second inverter. A unit circuit having a second switch circuit inserted between the output side of the first inverter and the input side of the first inverter, and the unit circuit is connected to the first inverter of the first switch circuit. Not connected to the input terminal and the output side of the first or second inverter as the output terminal, and a subordinate connection circuit in which two stages are connected in cascade, and an input terminal of the unit circuit in the preceding stage of the subordinate connection circuit is the first terminal. A third switch circuit connected to the terminal; a fourth switch circuit connecting the output terminal of the unit circuit in the subsequent stage of the subordinate connection circuit to a second terminal; and the unit in the preceding stage from the third switch circuit. Times A switch circuit inserted between the input terminal and the second terminal, and a path from the output terminal of the unit circuit in the subsequent stage to the fourth switch circuit and the first terminal. And a sixth switch circuit inserted between the first and second switch circuits when the third and fourth switch circuits are turned on and the fifth and sixth switch circuits are turned off. Becomes an input, the second terminal becomes an output, and conversely, the third and fourth switch circuits are turned on.
A flip-flop circuit characterized in that the second terminal serves as an input and the first terminal serves as an output when the fifth and sixth switch circuits are turned on in an FF state. 5. The output side of the first inverter is connected to the second side.
5. The flip-flop according to claim 4, wherein the flip-flop is connected to the input side of the inverter, the unit circuit is a latch circuit, and the cascade connection circuit is a circuit cascade-connected with the output side of the first inverter as an output terminal. circuit. 6. A predetermined terminal for receiving one of a HIGH level signal and a LOW level signal, wherein the third and fourth switch circuits receive the one signal at the predetermined terminal. It is turned on and the fifth and sixth switch circuits are turned off, and the H terminal is connected to the predetermined terminal.
When the other signal of the IGH level and the LOW level is received, the third and fourth switch circuits are turned off.
The flip-flop circuit according to claim 5, wherein the flip-flop circuit is FF and the fifth and sixth switch circuits are ON. 7. At least one of the first and second inverters is a gate circuit that operates as an inverter, and the third to sixth switch circuits are high level and high level via the predetermined terminals. 7. The flip-flop circuit according to claim 6, wherein any one of the LOW level signals is selectively received. 8. A plurality of the flip-flop circuits according to claim 1, wherein the second terminals of the plurality of flip-flop circuits are connected to the first terminal of the next-stage flip-flop circuit. A plurality of the flip-flop circuits are connected in cascade, and the first and second switch circuits of each of the flip-flop circuits are turned on, and the third and fourth switch circuits are turned off, so that the first terminal is turned on. The second terminal is used as an input and the output is used, and conversely, the first and second switch circuits are turned off, and the third and fourth
The shift register is characterized in that the second terminal is input and the first terminal is output by turning on the switch circuit. 9. A predetermined terminal for receiving one of a HIGH level signal and a LOW level signal, wherein the first and second switch circuits receive the one signal at the predetermined terminal. It is turned on and the third and fourth switch circuits are turned off, and the H terminal is connected to the predetermined terminal.
When the other one of the IGH level and the LOW level is received, the first and second switch circuits are turned off.
9. The shift register according to claim 8, wherein the shift register is FF and the third and fourth switch circuits are ON. 10. At least one of the two inverters is a gate circuit that operates as an inverter, and the first to fourth switch circuits are high level and LOW level signals via the predetermined terminals. 10. The shift register according to claim 9, which selectively receives any one of the above. 11. A plurality of the flip-flop circuits according to claim 4, wherein the second terminals of the plurality of flip-flop circuits are connected to the first terminal of the next-stage flip-flop circuit. A plurality of the flip-flop circuits are connected in cascade, and the third and fourth switch circuits of each of the flip-flop circuits are turned on, and the fifth and sixth switch circuits are turned off, so that the first terminal is turned on. The second terminal is used as an input for output, and conversely, the third and fourth switch circuits are turned off, and the fifth and sixth switch circuits are turned on, whereby the second terminal is used as an input. A shift register having a terminal 1 as an output. 12. The shift register according to claim 11, wherein the unit circuit is a latch circuit, and the series circuit is a circuit connected in cascade with an output side of the first inverter as an output terminal. 13. A predetermined terminal for receiving one of a HIGH level signal and a LOW level signal, wherein the first terminal receives the one signal at the predetermined terminal.
And the second switch circuit is turned on, and the third and fourth switch circuits are turned on.
Switch circuit is turned off, the first and second switch circuits are turned off and the third and fourth switch circuits are turned off when the predetermined terminal receives the other signal of the HIGH level and the LOW level. Switch circuit is ON
13. The shift register according to claim 12, wherein: 14. At least one of the two inverters is a gate circuit that operates as an inverter, and the first to fourth switch circuits are high-level and LOW-level signals via the predetermined terminals. 14. The shift register according to claim 13, which selectively receives any one of the above. 15. A shift register according to claim 8, comprising:
A scan drive circuit of a display device, wherein an output of the flip-flop circuit of the shift register is used as a drive signal of a vertical scan line or a horizontal scan line of a display panel. 16. A signal that is inverted with respect to a signal output to the second terminal of the flip-flop circuit is output from each of the plurality of flip-flop circuits, and this output is used as a drive signal for the scan line. The scan drive circuit of the display device according to claim 15. 17. A shift register according to claim 11, wherein an output of the flip-flop circuit connected in cascade of the shift register is used as a drive signal for a vertical scanning line or a horizontal scanning line of a display panel. A scan drive circuit of a display device which is characteristic. 18. A signal that inverts a signal output to the second terminal of the flip-flop circuit is output from each of the plurality of flip-flop circuits, and this output is used as a drive signal for the scanning line. The scan drive circuit of the display device according to claim 17. 19. The scan drive circuit for a display device according to claim 18, wherein the unit circuit is a latch circuit, and the series circuit is a circuit connected in cascade with the output side of the first inverter as an output terminal.