JP2003188568A - Electronic component mounting structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component packaging structure which uses no special structure or special material but is capable of suppressing a thermal stress applied to solder bumps due to the heat generated when an electronic component is used, and which can be easily manufactured at a low cost. <P>SOLUTION: In the electronic component packaging structure, an LSI chip 1 and an alumina substrate 2 to mount the LSI chip 1 on are installed, and the LSI chip 1 and the alumina substrate 2 are connected to each other by means of a plurality of solder bumps 3. The LSI chip 1 is provided with a temperature detecting means 4 and a Peltier element 7, while the alumina substrate is provided with a temperature detecting means 5 and a Peltier element 8. The temperature detecting means 4 and 5 and the Peltier elements 7 and 8 are connected to a temperature controlling means 6 which controls the Peltier elements 7 and 8 based on output signals from the temperature detecting means 4 and 5 to reduce a difference in thermal expansion between the LSI chip 1 and the alumina substrate 2. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for electronic parts, which has a plurality of electronic parts and is connected to each other by solder bumps, and more particularly to an electronic part in which fatigue damage of the solder bumps is prevented. Regarding the mounting structure of.

[0002]

2. Description of the Related Art When connecting electronic parts having connecting terminals, a large number of connecting terminals can be connected at once by using solder bumps. Therefore, this connection method using solder bumps is suitable for connection between electronic components having a large number of connection terminals. For example, when connecting a bare chip having several hundreds of connection terminals to a substrate or the like, a connection method using this solder bump is widely adopted. The bare chip is a bare integrated circuit chip that is not enclosed in a package.

However, LSI (large scale inte
grated circuit: large-scale integrated circuit) In a mounting structure in which a bare chip such as a chip and a board on which the bare chip is mounted are connected by solder bumps, there is a problem that disconnection of the connection portion frequently occurs during the period of use. . The cause of this disconnection is that the coefficient of thermal expansion of the LSI chip and the coefficient of thermal expansion of the substrate on which it is mounted differ from each other.
The LSI chip generates heat as it operates. This heat causes the LSI chip and the substrate to expand. However, generally, the thermal expansion coefficient of the LSI chip and the thermal expansion coefficient of the substrate are different from each other. Therefore, the length of thermal expansion of the LSI chip and the length of thermal expansion of the substrate are different from each other.
As a result, thermal stress is applied to the solder bumps that connect the LSI chip and the substrate. This thermal stress is generated when the LSI chip is in operation, and disappears when the LSI chip is at rest. Therefore, the thermal stress is repeatedly applied to the solder bumps. The thermal stress repeatedly applied causes the solder bumps to fatigue and eventually break. As a result, disconnection occurs at the connection between the LSI chip and the substrate,
The connection reliability of the mounting structure is reduced.

An example of the technique for preventing the disconnection of the connecting portion as described above is "N. Matsui, S. Sasaki, T. Osaki" V.L.S.I.Chip Interconnection Technology Youthing Stacked
Solder Bumps "Proceeding I E
E-E 37th Electronic Components Conference pp. 573-578 19
May 1987 (N.Matsui, S.Sasaki, T.Ohsaki "VLSI Chi
p Interconnection Technology Using StackedSolder B
umps, "Proc. IEEE 37th Electronic Component Conf.,
pp. 573-578, May 1987) "(hereinafter referred to as conventional document 1). It is described in this technique that the stress applied to each solder bump can be reduced by stacking the solder bumps in a plurality of layers.

Further, in Japanese Patent Laid-Open No. Sho 63-002865 (hereinafter referred to as “Reference 2”), when a ceramic material and a metal material are joined, an insert material and a brazing material are provided between the ceramic material and the metal material. Alternatively, a solder material (hereinafter collectively referred to as an insert material) is inserted, and the ceramic material and the metal material are joined by heating the insert material, and the ceramic material and the metal material are joined together in a cooling process after joining or after cooling to room temperature. By heating, the joined body of the ceramic material and the metal material is ½ of the melting point of the insert material.
A technique is disclosed in which the temperature is maintained in a temperature range of ⅓ to ⅓ for a predetermined time and then cooled to room temperature. This allows
It is described that the insert material undergoes creep deformation during the above-mentioned holding period, and as a result, residual stress due to cooling after joining is relaxed and the joining strength of the joined body is improved.

[0006]

However, the above-mentioned conventional technique has the following problems. In the technique described in the above-mentioned prior art document 1, since the solder bumps are stacked in a plurality of layers, it is difficult to manufacture the solder bumps, the structure of the mounting structure becomes complicated, and the volume of the mounting structure and There is a problem that the cost increases.

Further, in the technique described in the above-mentioned prior art document 2, although the residual stress generated in the cooling process after joining can be removed, the mounting structure is used after the mounting structure is manufactured. The thermal stress applied to the solder bumps due to the heat generation cannot be relaxed.

Further, it is conceivable to form the substrate with a material having a coefficient of thermal expansion close to that of the electronic component, but this restricts the choice of the substrate material extremely, resulting in the cost of the mounting structure. There is a possibility that characteristics other than the connection reliability will decrease as the number increases.

The present invention has been made in view of the above problems, and without using a special structure and material,
An object of the present invention is to provide a mounting structure for an electronic component, which can suppress thermal stress applied to the solder bump due to heat generated by the use of the electronic component, and can be easily manufactured at low cost.

[0010]

According to a first aspect of the present invention, there is provided a mounting structure for an electronic component, wherein the first and second electronic components are connected to each other. A plurality of solder bumps, first and second temperature detecting means for detecting temperatures of the first and second electronic components, respectively, and first and second for cooling the first and second electronic components, respectively. The cooling means and the detection results of the first and second temperature detecting means are input, and the thermal expansion magnitudes of the first and second electronic components are made equal to each other based on the detection results. Temperature control means for controlling the operation of at least one of the first and second cooling means.

In the present invention, the first temperature detecting means detects the temperature of the first electronic component in real time, and the second temperature detecting means detects the temperature of the second electronic component in real time to obtain the temperature. The control means controls the temperature of at least one of the first and second electronic components by operating the first and second cooling means based on the temperature data. This temperature control is performed so that the difference between the thermal expansion magnitude of the first electronic component and the thermal expansion magnitude of the second electronic component is reduced. Thereby, the stress applied to the solder bump due to the difference between the thermal expansion of the first electronic component and the thermal expansion of the second electronic component can be relaxed. As a result, it is possible to prevent the solder bumps from being damaged by fatigue and improve the connection reliability of the mounting structure.

In this specification, an electronic component is L
In addition to SI chips and the like, substrates including LSI chips and the like are also included. In addition, the magnitude of thermal expansion of electronic parts is
The amount of thermal expansion of an electronic component in the direction orthogonal to the direction from the first electronic component to the second electronic component. This electronic component is connected to another electronic component via a solder bump, and If the deformation is not constrained,
Based on the case where the temperature of the electronic component is room temperature, it means the amount of thermal expansion observed when the electronic component is heated.

Further, at least one of the first and second cooling means is a heat sink attached to an electronic component to be cooled by the cooling means, and a fan for blowing air to the heat sink by rotating the heat sink. Or the cooling means may have a Peltier element attached to the electronic component to be cooled. This makes it possible to realize a highly efficient and low-cost cooling means.

According to a fourth aspect of the present invention, there is provided a mounting structure for another electronic component, wherein the degree of thermal expansion during operation of the first electronic component is the same as that during operation of the first electronic component. 1
A second electronic component having a smaller thermal expansion than that of the electronic component, a plurality of solder bumps for connecting the first and second electronic components to each other, and a temperature of the first and second electronic components. First and second temperature detecting means for respectively detecting, cooling means for cooling the first electronic component, and detection results of the first and second temperature detecting means are inputted, and based on this detection result, the Temperature control means for controlling the operation of the cooling means such that the thermal expansion magnitudes of the first and second electronic components are equal to each other.

In the present invention, as compared with the mounting structure for electronic parts according to the first aspect of the present invention, the cooling means for cooling the second electronic parts is omitted, so that the structure is improved. It can be simplified. However, the magnitude of thermal expansion during operation of the first electronic component needs to be larger than the magnitude of thermal expansion during operation of the second electronic component.

The temperature control means controls the temperature rise of the first and second electronic components during operation by T1.
(K) and T2 (K), and the linear expansion coefficients of the first and second electronic components are α1 and α2, respectively, (α1
It is preferable to control at least one of T1 and T2 so that the value of (× T1−α2 × T2) approaches 0.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a side view showing a mounting structure of an electronic component according to this embodiment. As shown in FIG. 1, an electronic component mounting structure according to the present embodiment is provided with an LSI chip 1 as an electronic component, and a large number of connection terminals 1a are formed in the LSI chip 1 in a matrix, for example. ing. Further, an alumina substrate 2 as an electronic component is provided so as to face the LSI chip 1, and a large number of connection terminals 2a are formed on the surface of the alumina substrate 2 in a matrix, for example. The connection terminal 2a of the alumina substrate 2 is the connection terminal 1 of the LSI chip 1.
It is provided at a position corresponding to a, and each one connection terminal 1a and one connection terminal 2a are connected to each other by one solder bump 3. As a result, the LSI chip 1 is mounted on the alumina substrate 2. Note that, in FIG. 1, for simplification of the drawing, the connection terminals 1a and 2a and the solder bumps 3 are shown in only five rows, but in the present embodiment, the number of rows of the connection terminals 1a, 2a and the solder bumps 3 is shown. May be 4 columns or less, or 6 columns or more.
Similarly, the number of rows of the connection terminals 1a, 2a and the solder bumps 3 is also arbitrary.

Temperature detecting means 4 is attached to the surface of the LSI chip 1 facing the alumina substrate 2, and cooling means is mounted on the surface of the LSI chip 1 opposite to the surface facing the alumina substrate 2. The Peltier element 7 is attached. Similarly, the temperature detecting means 5 is attached to the surface of the alumina substrate 2 facing the LSI chip 1, and the surface of the alumina substrate 2 opposite to the surface facing the LSI chip 1 serves as cooling means. A Peltier element 8 is attached. Further, the temperature detecting means 4 and 5 and the Peltier elements 7 and 8 are connected to the temperature control means 6. The temperature control means 6 comprises, for example, an integrated circuit, and controls the Peltier elements 7 and 8 based on the output signals of the temperature detection means 4 and 5. The temperature detecting means 4 and 5 are, for example, thermocouples.

Next, the operation of the mounting structure for electronic parts according to this embodiment will be described. When the LSI chip 1 operates, the LSI chip 1 generates heat and its temperature rises. This heat is transferred to the alumina substrate 2 via the solder bumps 3 by heat conduction, and the temperature of the alumina substrate 2 also rises. The temperature detecting means 4 detects the temperature of the LSI chip 1,
The result is output to the temperature control means 6 in real time. Similarly, the temperature detection means 5 detects the temperature of the alumina substrate 2 and outputs the result to the temperature control means 6 in real time.

At this time, the temperature rise of the LSI chip 1 is
1 (K), the temperature rise of the alumina substrate 2 is T2 (K)
And Further, in the direction orthogonal to the direction from the LSI chip 1 to the alumina substrate 2, the linear expansion coefficient of the LSI chip 1 is α1, and the linear expansion coefficient of the alumina substrate 2 is α.
Set to 2. Further, the distance between the central axis 9 of the LSI chip 1 and the center of the outermost peripheral connection terminal 1a is L. Then,
With reference to the non-operating state of the LSI chip 1, the distance over which the center of the outermost peripheral connection terminal 1a is to move due to thermal expansion of the LSI chip 1 when the LSI chip 1 is operating is (α1
XT1 × L), and the distance that the center of the outermost peripheral connecting terminal 2a moves due to thermal expansion of the alumina substrate 2 during the operation of the LSI chip 1 is (α2 × T2 × L). Therefore, the positional deviation between the outermost peripheral connection terminal 1a and the outermost peripheral connection terminal 2a is (α1 × T1−α2 × T2) × L
Due to this deviation, thermal stress is applied to the solder bumps 3.

Therefore, the temperature control means 6 uses (α1 × T1-
Set the LSI chip 1 so that the value of (α2 × T2) approaches 0.
And the temperature of the alumina substrate 2 is controlled. For example, the temperature rise T1 of the LSI chip 1 is fixed to a constant value by the cooling means 7, and the temperature rise T2 of the alumina substrate 2 is controlled by the cooling means 8 so that T2 = α2 / α1 × T1.

In this embodiment, (α1 × T1-α2
Since the temperature of the LSI chip 1 and the alumina substrate 2 is controlled so that the value of (× T2) approaches 0, the LSI chip 1 and the alumina substrate 2 during the operation of the LSI chip 1 are controlled.
The difference in thermal expansion between and becomes smaller. Thereby, the thermal stress applied to the solder bump 3 can be relaxed. As a result, fatigue failure of the solder bumps 3 can be prevented, and the connection life of the solder bumps 3 can be extended. Therefore, it is possible to prevent disconnection between the connection terminals 1a and 2a, and improve the connection reliability of the mounting structure of the electronic component. Further, since this mounting structure does not need to use a special solder bump structure and a substrate formed of a special material, it is low cost and easy to manufacture.

In this embodiment, the Peltier element is used as the cooling means, but the present invention is not limited to this, and for example, a heat sink with a fan or a heat pipe may be used. In this case, for example, a heat sink is attached to the LSI chip and the alumina substrate, and a fan that blows air to the heat sink is provided. Then, the temperature control means 6 controls the rotation speed of the fan to locally control the temperatures of the LSI chip and the alumina substrate.

In the present embodiment, the electronic component is L
Although the SI chip and the alumina substrate on which the LSI chip is mounted are shown as examples, the present invention is not limited to this. Further, although an example in which a thermocouple is used as the temperature detecting means has been shown, the present invention is not limited to this.

Furthermore, of the Peltier elements 7 and 8,
The Peltier element for cooling the electronic component having a smaller thermal expansion amount during operation may be omitted. That is, when the thermal expansion amount of the LSI chip 1 is smaller than that of the alumina substrate 2, the Peltier element 7 is omitted, and the thermal expansion amount of the alumina substrate 2 is set to the thermal expansion amount of the LSI chip 1. If it is smaller than the size of, the Peltier element 8 can be omitted. Then, only the electronic component having a larger thermal expansion is cooled to reduce the thermal expansion difference between the LSI chip 1 and the alumina substrate 2. Thereby, the structure of the mounting structure can be further simplified.

Next, a second embodiment of the present invention will be described. The electronic component mounting structure according to the present embodiment is compared with the electronic component mounting structure according to the first embodiment described above.
Peltier element 7 for cooling LSI chip 1 (see FIG. 1)
However, it is not controlled by the temperature control means 6. That is, although the LSI chip 1 is cooled by the Peltier device 7, the cooling is not controlled by the temperature control means 6. The temperature control means 6 controls only the operation of the Peltier element 8 and controls the temperature of the alumina substrate 2 to reduce the difference in thermal expansion between the LSI chip 1 and the alumina substrate 2. The temperature control means 6 may control only the operation of the Peltier element 7 and not the operation of the Peltier element 8.

[0027]

As described in detail above, according to the present invention,
In a mounting structure for electronic components, by reducing the difference in thermal expansion between the electronic components connected to each other by solder bumps, the thermal stress applied to the solder bumps due to the heat generated by the use of the electronic components can be relaxed. The connection life of the bump can be significantly improved. Further, since this mounting structure does not need to use a special solder bump structure and a special material, it is easy to manufacture at low cost.

[Brief description of drawings]

FIG. 1 is a side view showing a mounting structure of an electronic component according to a first embodiment of the present invention.

[Explanation of symbols]

1; LSI chips 1a, 2a; connection terminals 2; alumina substrate 3; solder bumps 4, 5; temperature detection means 6; temperature control means 7, 8; Peltier element 9; central axis L of LSI chip 1; central axis 9 Distance from the center of the outermost connection terminal 1a

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 1/18 H01L 23/56 D

Claims (8)

[Claims] 1. A first electronic component, a second electronic component, a plurality of solder bumps interconnecting the first electronic component and the second electronic component, and temperatures of the first electronic component and the second electronic component are respectively detected. First and second temperature detecting means, first and second cooling means for respectively cooling the first and second electronic components, and detection results of the first and second temperature detecting means are input. Based on the detection result, the first and second electronic components are controlled so that the thermal expansion magnitudes of the first and second electronic components become equal to each other.
And a temperature control means for controlling the operation of at least one of the cooling means of 1. and a mounting structure of an electronic component. 2. A fan in which at least one of the first and second cooling means rotates with a heat sink attached to an electronic component to be cooled by the cooling means, and which blows air to the heat sink. The mounting structure for an electronic component according to claim 1, further comprising: 3. The electron according to claim 1, wherein at least one of the first and second cooling means has a Peltier element attached to an electronic component to be cooled by the cooling means. Mounting structure of parts. 4. A first electronic component and a second electronic component whose thermal expansion amount during operation is smaller than the thermal expansion amount of the first electronic component during operation of the first electronic component. A plurality of solder bumps interconnecting the first and second electronic components, first and second temperature detecting means for detecting temperatures of the first and second electronic components, respectively, and Cooling means for cooling the first electronic component, and the first and second
The temperature detection means for inputting the detection result of the temperature detection means, and controlling the operation of the cooling means based on the detection result so that the thermal expansion magnitudes of the first and second electronic parts become equal to each other. A mounting structure for an electronic component, comprising: 5. The cooling means according to claim 4, further comprising a heat sink attached to the first electronic component, and a fan that rotates to blow air to the heat sink. Electronic component mounting structure. 6. The mounting structure for an electronic component according to claim 4, wherein the cooling unit has a Peltier element attached to the first electronic component. 7. The temperature control means includes the first and second temperature control means.
Temperature rise during operation of each electronic component of T1 (K)
And T2 (K) and the linear expansion coefficients of the first and second electronic components are α1 and α2, respectively, (α1 × T1
7. The electronic component mounting structure according to claim 1, wherein at least one of T1 and T2 is controlled so that the value of −α2 × T2) approaches 0. . 8. One of the first and second electronic components is an LSI chip, and the other is a substrate on which the LSI chip is mounted.
A mounting structure for an electronic component according to any one of 1.