JP2003188265A - Method of manufacturing MIM type capacitive element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance and high-reliability capacitive element with a high yield by facilitating processing of a metal layer for an upper electrode and a dielectric film, which has been difficult in the past, in a MIM type capacitive element. . SOLUTION: After successively depositing a metal layer for a lower electrode, a plasma Si ₃ N ₄ film and a metal layer for an upper electrode, the upper electrode metal layer is subjected to RIE using an etching gas for the metal layer using a resist film as a mask. To form an upper electrode. Next, after removing the resist film, the plasma Si ₃ N ₄ film is patterned by RIE using an etching gas for an insulating film using the upper electrode as a mask. Next, after forming a lower electrode, an interlayer insulating film is deposited to form a via hole. Next, after filling the via hole with tungsten to form a lead electrode, an upper wiring is formed in a predetermined region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance element having a metal-insulating film-metal (MIM) structure, and particularly to a method of manufacturing a capacitance element which realizes high capacitance value precision, high breakdown voltage characteristics and high reliability. Regarding

[0002]

2. Description of the Related Art In recent years, high-frequency analog integrated circuits used in mobile communication equipment such as mobile phones are equipped with passive elements such as capacitance elements, resistors and inductors. In order to operate the integrated circuit at high speed and reduce power consumption, extremely small parasitic capacitance and parasitic resistance are required for these passive elements, and this is particularly remarkable for the capacitive elements.

Conventionally, as a capacitive element used in an integrated circuit, a metal film or conductive polycrystalline silicon (poly S) is used.
i) A MOS type capacitor in which a thin silicon oxide (SiO ₂ ) film or the like is sandwiched between an electrode such as a film and a silicon (Si) substrate,
2 with a thin SiO ₂ film sandwiched between two layers of conductive poly-Si
There is a layer poly-Si type capacitor or the like. These capacitors have high parasitic resistance because one or both of the electrodes use an impurity diffusion layer or a conductive poly-Si film in the semiconductor substrate. Also,
Since the distance between the electrode and the Si substrate is only about the insulation film thickness for element isolation, the parasitic capacitance is large, and the depletion layer in the Si substrate changes depending on the applied voltage, so the parasitic capacitance value is not constant with respect to the voltage. was there. From this point of view, the upper and lower electrodes are made of a low-resistance metal film, and by using the upper layer wiring for the electrodes, it is possible to form them with a distance from the Si substrate, and the parasitic resistance and parasitic capacitance are extremely small. A possible MIM type capacitive element has been attracting attention.

Here, a method of manufacturing the conventional MIM type capacitive element disclosed in Japanese Patent Laid-Open No. 2001-203329 will be described with reference to the drawings. Fig.3 (a)-
(C) is sectional drawing which shows the manufacturing process of the conventional MIM type capacitive element.

First, as shown in FIG. 3A, the Si substrate 2
A metal layer for a lower electrode is deposited on the insulating film 22 formed on one surface and patterned to form a lower electrode 23 including a lower electrode region 23a and a lower wiring region 23b. After that, the dielectric film 24 is deposited on the entire surface, and the upper electrode metal layer 25 is continuously deposited.

Next, as shown in FIG. 3B, by using the photoresist film 26 as a mask, the dielectric film 24 and the upper electrode on the lower wiring region 23b are formed by reactive ion etching (RIE). Metal layer 25
Are simultaneously removed by etching to remove the lower electrode 2 in the region 23b.
3 Expose the surface.

Next, as shown in FIG. 3C, the lower electrode 2
3. An interlayer insulating film 28 is formed so as to cover the dielectric film 24 and the upper electrode 25. After that, the via hole 2 in which the surfaces of the lower electrode 22 and the upper electrode 25 are exposed
9 and 30 are formed on the interlayer insulating film 28 by RIE, and then a metal such as tungsten is buried in the via holes to form the first extraction electrode 31 and the second extraction electrode 32.
To form. Finally, the upper wiring metal layer 33 is deposited on the entire surface, patterned, and connected to the first extraction electrode 31 and the second extraction electrode 32, whereby the MIM type capacitive element is formed.

[0008]

However, in the manufacturing method of the MIM type capacitor described above, the dielectric film 24 and the upper electrode 25 as shown in the step of FIG.
It is extremely difficult to remove them simultaneously by etching.

In general, RIE of a metal layer such as aluminum
A mixed gas of Cl ₂ , BCl ₃ and CHF ₃ is used for the insulating gas, and a mixed gas of CHF ₃ , CF ₄ and Ar is used for the RIE of the insulating film such as the SiO ₂ film and the Si ₃ N ₄ film. And the etching characteristics of each are significantly different.

For example, when the above RIE is performed under the gas condition for the metal layer, there is a risk that the etching of the dielectric film 24 may deteriorate the uniformity of the etching rate or cause an etching residue. Furthermore, since the etching rate of the lower electrode 23 of the etching stopper layer is higher than that of the dielectric film 24 which is the layer to be etched, the film thickness control of the lower electrode and the lower wiring in the integrated circuit using the metal layer can be performed. It will be difficult.

When the above RIE is performed under the gas condition for the insulating film, Cl ₂ gas is indispensable for the etching of the metal layer in order to secure the etching rate and maintain the etching shape. Etching 25 is very difficult. Further, an etching gas for the metal layer and an etching gas for the insulating film are introduced into the same etching chamber, and the upper electrode metal layer 25 and the dielectric film 24 are introduced.
In the case of respectively etching and, since RIE of different types of films is performed in the same chamber, particles such as etching products frequently occur and the yield of integrated circuits is reduced. In addition, the frequency of maintenance of the RIE device increases, resulting in a significant decrease in productivity.

Further, in the above-described method of manufacturing the MIM type capacitor, after the RIE in the step of FIG. 3B, the lower electrode 23 and the side wall of the lower wiring (not shown) in the integrated circuit using the metal layer are formed. A sidewall film 27 including the dielectric film 24 and the upper electrode metal layer 25 is formed. Since the sidewall film 27 may cause an electrical short between lower wirings, fine wiring cannot be formed.

As described above, in the above-mentioned conventional technique, M
The processing of the metal layer for the upper electrode of the IM type capacitor and the dielectric film was extremely difficult and inappropriate. Further, there are problems in forming fine wiring.

An object of the present invention is to solve the above-mentioned problems of the prior art. In the MIM type capacitive element,
The present invention provides a manufacturing method that facilitates processing of a metal layer for an upper electrode and a dielectric film, and at the same time can form fine wiring.

[0015]

In order to achieve the above-mentioned object, a method of manufacturing an MIM type capacitor according to the present invention comprises a first metal layer on a first insulating film formed on a semiconductor substrate. A first step of continuously depositing a dielectric film and a second metal layer, a second step of selectively etching the second metal layer to form an upper electrode, and a dielectric film selection Third step of selectively etching the first metal layer, a fourth step of selectively etching the first metal layer to form a lower electrode, and a second insulation covering the upper electrode, the dielectric film, and the lower electrode. Fifth forming film
And a sixth step of selectively etching the second insulating film to form a via hole exposing the surfaces of the lower electrode and the upper electrode, and filling the via hole with a third metal layer. And a seventh step of forming an extraction electrode connected to the lower electrode and the upper electrode, and an eighth step of selectively forming a fourth metal layer on the extraction electrode to form an upper wiring connected to the extraction electrode. And a process.

With this structure, the second metal layer and the dielectric film can be easily processed, and the MIM type capacitive element having low parasitic capacitance and parasitic resistance and high reliability is realized. be able to. Further, it becomes possible to form fine wiring according to the design rule by using the metal layer that constitutes the MIM type capacitive element, and a semiconductor device equipped with a high performance, highly integrated and highly reliable MIM type capacitive element is provided. Obtainable.

In the method of manufacturing a semiconductor device described above, it is preferable that the dielectric film is etched in the third step by using the upper electrode formed in the second step as a mask.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 (a)-(c)
2A to 2C show MI according to the embodiment of the present invention.
FIG. 9 is a cross-sectional view showing the manufacturing process of the M-type capacitor.

First, in the step shown in FIG. 1A, the Si substrate 1
After the SiO ₂ film 2 (first insulating film) having a film thickness of about 1000 nm is formed on the upper surface, the lower electrode metal layer 3 is continuously formed on the entire surface.
(First metal layer) is deposited. This lower electrode metal layer 3
Is a Ti layer having a film thickness of about 30 nm from the lower layer, and a film thickness of about 10
0nm TiN layer, about 600nm thick AlCu layer,
It is a laminated film in which a TiN layer having a film thickness of about 30 nm is deposited by a continuous sputtering method. Next, a plasma S having a film thickness of about 60 nm is formed on the entire surface of the lower electrode metal layer 3 by the plasma CVD method.
The i ₃ N ₄ film 4 (dielectric film) is deposited, and the upper electrode metal layer 5 (second metal layer) is continuously deposited. The upper electrode metal layer 5 includes a TiN layer having a thickness of about 30 nm, an AlCu layer having a thickness of about 100 nm, and a Ti layer having a thickness of about 30 nm from the lower layer.
It is a laminated film in which an N layer is deposited by a continuous sputtering method.

The formation of the dielectric film and the metal layer for the upper electrode of the MIM type capacitive element in this embodiment is an example, and the plasma TEOS film is used for the dielectric film formation in addition to the plasma Si ₃ N ₄ film. Alternatively, a plasma oxide film or the like may be used, and TiN / AlCu / Ti may be used for forming the metal layer for the upper electrode.
In addition to the N laminated film, an AlCu single layer film, a TiN single layer film, a WSi ₂ single layer film, or the like may be used.

Next, in the step shown in FIG. 1B, the upper electrode metal layer 5 is patterned. First, a resist film 7 having a thickness of about 1.5 μm is formed on the capacitance region 6 of the upper electrode metal layer 5 by photolithography. Then
Using the resist film 7 as a mask, the metal layer 5 for the upper electrode other than the capacitor region 6 is removed by RIE using a mixed gas of Cl ₂ , BCl ₃ and CHF ₃ , and plasma Si ₃
The surface of the N ₄ film 4 is exposed and the upper electrode 5 is formed. Then, the resist film 7 is removed.

Next, in the step shown in FIG. 1C, plasma S
The i ₃ N ₄ film 4 is patterned. By using the upper electrode 5 as a mask, RIE using a mixed gas of CHF ₃ , CF _4, Ar, etc., plasma Si ₃ N ₄ other than the capacitive region 6 is formed.
The film 4 is removed to expose the surface of the lower electrode metal layer 3.
This RIE condition is a standard condition used for an insulating film, and the etching rate of plasma Si ₃ N ₄ is set sufficiently higher than the etching rate of a metal layer. 5 and the underlying lower electrode metal layer 3 are hardly etched.

Here, in the steps of FIGS. 1B to 1C, after removing the resist film 7, R of the plasma Si ₃ N ₄ film 4 is removed.
When performing the IE, there is a risk that ions such as Cl attached to the surface portion of the resist film 7 due to the RIE of the upper electrode metal layer 5 may corrode the chamber or the transport system of the RIE apparatus of the plasma Si ₃ N ₄ film 4. Because there is.

Next, in the step shown in FIG. 2A, the metal layer 3 for lower electrode is patterned. By photolithography, on the lower electrode region 3a (the plasma Si ₃ N ₄ film 4 and the upper electrode 5 are formed on the upper portion) of the capacitance region 6 and the lower electrode metal layer 3 in the lower wiring region 3b around the lower electrode region 3a. A resist film 8 having a thickness of about 1.5 μm is formed. afterwards,
R using a mixed gas of Cl ₂ , BCl ₃ and CHF ₃
The lower electrode 3 is formed by IE. Finally the resist film 8
To remove. At this time, although not shown, the device electrode and the lower wiring in the integrated circuit are simultaneously formed.

Next, in a step shown in FIG. 2B, the inter-layer insulating film 9 (second insulating film) and the lead electrode via holes 10 and 11 are formed. First, a TEOS film having a thickness of about 300 nm is grown by the plasma CVD method, and then A
The TEOS film is etched back by sputtering using r gas. Again, about 2200n by plasma CVD method
A TEOS film having a thickness of m is grown, and then a resist (not shown) having a thickness of about 1.5 μm is applied. Then CHF
_The resist is etched back by RF etching using a mixed gas of ₃ , CF ₄ , Ar and O ₂ , and the TEOS film is flattened to form an interlayer insulating film 9. The film thickness of the interlayer insulating film 9 is about 1 μm on the lower wiring region 3b and about 0.8 μm on the lower electrode region.

The method of flattening the underlying step formed in the integrated circuit in this embodiment is an example, and the interlayer insulating film may be formed by using a CMP (Chemical Mechanical Polishing) method or the like in addition to the etchback method. Good.

Next, using the resist film (not shown) formed on the interlayer insulating film 9 as a mask, the lower electrode 3 and the upper electrode 5 are formed by RIE using a mixed gas of CHF ₃ , CF ₄ and Ar. Via hole 1 with exposed surface
0 and 11 are formed on the interlayer insulating film 9. Finally, the resist film is removed. Here, the via hole has a diameter of 0.8μ.
A plurality of circles of about m are formed. Although not shown, at the same time, via holes for connecting to device electrodes and lower wirings in the integrated circuit are collectively formed.

Next, in the step shown in FIG. 2C, the extraction electrodes 12 and 13 (third metal layer) and the upper wiring 14 (fourth metal layer) are formed. First, the oxide layer on the surfaces of the lower electrode 3 and the upper electrode 5 at the bottom of the via holes 10 and 11 is removed by the reverse sputtering method using Ar gas. continue,
After depositing a Ti layer having a thickness of about 30 nm, TiN having a thickness of about 100 nm, and a tungsten layer having a thickness of about 700 nm in this order in the via holes 10 and 11 and on the interlayer insulating film 9, these films are deposited. Is etched back by RF etching, so that the lower electrode 3 composed of a tungsten layer, a TiN layer and a Ti layer is formed in the via holes 10 and 11.
The extraction electrode 12 and the extraction electrode 13 of the upper electrode 5 are formed respectively. Finally, after depositing the upper wiring metal layer 14 on the extraction electrodes 12 and 13 and the interlayer insulating film 9,
A resist film (not shown) is formed in a predetermined region on the lead electrodes 12 and 13, and the upper wiring metal layer 14 is patterned by the RIE method using the resist film as a mask.
An upper wiring 14a for leading the lower electrode and an upper wiring 14b for leading the upper electrode are formed respectively. In this way, the MIM type capacitive element of this embodiment is formed.

As described above, according to the method of manufacturing the MIM type capacitive element of the present invention, RIE between the metal layer for the upper electrode and the dielectric film, which has been very difficult in the prior art, can be easily realized, so that high performance is achieved. In addition, a highly reliable MIM type capacitive element can be manufactured with a higher yield.

[0030]

As described above, the MI according to the present invention
According to the method for manufacturing the M-type capacitor, the metal layer for the upper electrode and the dielectric film can be easily processed, the parasitic capacitance and the parasitic resistance are low, and the MIM-type capacitor has high reliability. The device can be realized. Further, it becomes possible to form fine wiring according to the design rule by using the metal layer that constitutes the MIM type capacitive element, and a semiconductor device equipped with a high performance, highly integrated and highly reliable MIM type capacitive element is provided. Obtainable.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an MIM type capacitive element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of an MIM type capacitive element according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a conventional MIM type capacitive element.

[Explanation of symbols]

1 Si Substrate 2 SiO ₂ Film 3 Lower Electrode Metal Layer (Lower Electrode) 3a Lower Electrode Metal Layer Lower Electrode Region 3b Lower Electrode Metal Layer Lower Wiring Region 4 Plasma Si ₃ N ₄ Film 5 Upper Electrode Metal Layer (Upper electrode) 6 Capacitance region 7 Resist film 8 Resist film 9 Interlayer insulating films 10 and 11 Via holes 12 and 13 Lead electrodes 14a and 14b Upper wiring

Continued front page    F term (reference) 4M104 AA01 BB02 BB14 BB28 BB30                       CC01 DD08 DD16 DD17 DD23                       DD37 DD65 DD71 DD72 EE08                       EE12 EE14 EE17 FF17 FF18                       FF22 GG19 HH12 HH14 HH20                 5F033 HH09 HH28 HH33 JJ18 JJ19                       JJ33 KK09 KK18 KK28 KK33                       MM05 MM08 MM13 NN06 NN07                       PP15 QQ08 QQ09 QQ13 QQ14                       QQ24 QQ25 QQ27 QQ28 QQ30                       QQ31 QQ37 QQ48 QQ94 RR04                       SS04 SS15 VV10 XX01 XX03                       XX31                 5F038 AC05 AC15 EZ14 EZ15

Claims (2)

[Claims] 1. A first step of continuously depositing a first metal layer, a dielectric film, and a second metal layer on a first insulating film formed on a semiconductor substrate, and the second step. A second step of selectively etching the metal layer to form an upper electrode; a third step of selectively etching the dielectric film; and a second step of selectively etching the first metal layer to form a lower layer. A fourth step of forming an electrode, a fifth step of forming a second insulating film covering the upper electrode, the dielectric film and the lower electrode; and a step of selectively etching the second insulating film. A sixth step of forming a via hole exposing the surfaces of the lower electrode and the upper electrode, and filling the inside of the via hole with a third metal layer to connect the lower electrode and the upper electrode. A seventh step of forming the extraction electrode, and a fourth metal layer on the extraction electrode. Method for producing a MIM capacitor, characterized in that it comprises an eighth step of forming an upper wiring formed on 択的 connected to said lead electrode. 2. The MI according to claim 1, wherein in the third step, the dielectric film is etched using the upper electrode formed in the second step as a mask.
Method for manufacturing M-type capacitor.